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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/phy/rockchip/phy-rockchip-dp.c
....@@ -1,72 +1,68 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Rockchip DP PHY driver
34  *
45  * Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
56  * Author: Yakir Yang <ykk@@rock-chips.com>
6
- *
7
- * This program is free software; you can redistribute it and/or modify
8
- * it under the terms of the GNU General Public License as published by
9
- * the Free Software Foundation; either version 2 of the License.
107  */
118 
129 #include <linux/clk.h>
13
-#include <linux/clk-provider.h>
1410 #include <linux/mfd/syscon.h>
1511 #include <linux/module.h>
1612 #include <linux/of.h>
17
-#include <linux/of_device.h>
1813 #include <linux/phy/phy.h>
1914 #include <linux/platform_device.h>
2015 #include <linux/regmap.h>
21
-#include <linux/reset.h>
2216 
23
-struct rockchip_dp_phy_data {
24
-	u32 grf_reg_offset;
25
-	u8 ref_clk_sel_shift;
26
-	u8 iddq_shift;
27
-};
17
+#define GRF_SOC_CON12                           0x0274
18
+
19
+#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK   BIT(20)
20
+#define GRF_EDP_REF_CLK_SEL_INTER               BIT(4)
21
+
22
+#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK           BIT(21)
23
+#define GRF_EDP_PHY_SIDDQ_ON                    0
24
+#define GRF_EDP_PHY_SIDDQ_OFF                   BIT(5)
2825 
2926 struct rockchip_dp_phy {
3027 	struct device  *dev;
3128 	struct regmap  *grf;
3229 	struct clk     *phy_24m;
33
-	struct reset_control *rst;
34
-	const struct rockchip_dp_phy_data *data;
3530 };
31
+
32
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
33
+{
34
+	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
35
+	int ret;
36
+
37
+	if (enable) {
38
+		ret = regmap_write(dp->grf, GRF_SOC_CON12,
39
+				   GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
40
+				   GRF_EDP_PHY_SIDDQ_ON);
41
+		if (ret < 0) {
42
+			dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
43
+			return ret;
44
+		}
45
+
46
+		ret = clk_prepare_enable(dp->phy_24m);
47
+	} else {
48
+		clk_disable_unprepare(dp->phy_24m);
49
+
50
+		ret = regmap_write(dp->grf, GRF_SOC_CON12,
51
+				   GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
52
+				   GRF_EDP_PHY_SIDDQ_OFF);
53
+	}
54
+
55
+	return ret;
56
+}
3657 
3758 static int rockchip_dp_phy_power_on(struct phy *phy)
3859 {
39
-	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
40
-	const struct rockchip_dp_phy_data *data = dp->data;
41
-
42
-	if (!__clk_is_enabled(dp->phy_24m))
43
-		clk_prepare_enable(dp->phy_24m);
44
-
45
-	if (dp->rst) {
46
-		/* EDP 24m clock domain software reset */
47
-		reset_control_assert(dp->rst);
48
-		usleep_range(20, 40);
49
-		reset_control_deassert(dp->rst);
50
-	}
51
-
52
-	regmap_write(dp->grf, data->grf_reg_offset,
53
-		     0 | BIT(16 + data->iddq_shift));
54
-
55
-	return 0;
60
+	return rockchip_set_phy_state(phy, true);
5661 }
5762 
5863 static int rockchip_dp_phy_power_off(struct phy *phy)
5964 {
60
-	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
61
-	const struct rockchip_dp_phy_data *data = dp->data;
62
-
63
-	regmap_write(dp->grf, data->grf_reg_offset,
64
-		     BIT(data->iddq_shift) | BIT(16 + data->iddq_shift));
65
-
66
-	if (__clk_is_enabled(dp->phy_24m))
67
-		clk_disable_unprepare(dp->phy_24m);
68
-
69
-	return 0;
65
+	return rockchip_set_phy_state(phy, false);
7066 }
7167 
7268 static const struct phy_ops rockchip_dp_phy_ops = {
....@@ -81,7 +77,6 @@
8177 	struct device_node *np = dev->of_node;
8278 	struct phy_provider *phy_provider;
8379 	struct rockchip_dp_phy *dp;
84
-	const struct rockchip_dp_phy_data *data = of_device_get_match_data(dev);
8580 	struct phy *phy;
8681 	int ret;
8782 
....@@ -96,7 +91,6 @@
9691 		return -ENOMEM;
9792 
9893 	dp->dev = dev;
99
-	dp->data = data;
10094 
10195 	dp->phy_24m = devm_clk_get(dev, "24m");
10296 	if (IS_ERR(dp->phy_24m)) {
....@@ -110,30 +104,15 @@
110104 		return ret;
111105 	}
112106 
113
-	ret = clk_prepare_enable(dp->phy_24m);
114
-	if (ret) {
115
-		dev_err(dev, "failed to enable phy 24m clock: %d\n", ret);
116
-		return ret;
117
-	}
118
-
119
-	dp->rst = devm_reset_control_get_optional(dev, "edp_24m");
120
-	if (IS_ERR(dp->rst)) {
121
-		ret = PTR_ERR(dp->rst);
122
-		dev_err(dev, "failed to get reset control: %d\n", ret);
123
-		return ret;
124
-	}
125
-
126107 	dp->grf = syscon_node_to_regmap(dev->parent->of_node);
127108 	if (IS_ERR(dp->grf)) {
128109 		dev_err(dev, "rk3288-dp needs the General Register Files syscon\n");
129110 		return PTR_ERR(dp->grf);
130111 	}
131112 
132
-	/* eDP PHY reference clock source from internal clock */
133
-	ret = regmap_write(dp->grf, data->grf_reg_offset,
134
-			   BIT(data->ref_clk_sel_shift) |
135
-			   BIT(16 + data->ref_clk_sel_shift));
136
-	if (ret) {
113
+	ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
114
+			   GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
115
+	if (ret != 0) {
137116 		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
138117 		return ret;
139118 	}
....@@ -150,21 +129,8 @@
150129 	return PTR_ERR_OR_ZERO(phy_provider);
151130 }
152131 
153
-static const struct rockchip_dp_phy_data rk3288_dp_phy_data = {
154
-	.grf_reg_offset = 0x274,
155
-	.ref_clk_sel_shift = 4,
156
-	.iddq_shift = 5,
157
-};
158
-
159
-static const struct rockchip_dp_phy_data rk3368_dp_phy_data = {
160
-	.grf_reg_offset = 0x410,
161
-	.ref_clk_sel_shift = 0,
162
-	.iddq_shift = 1,
163
-};
164
-
165132 static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
166
-	{ .compatible = "rockchip,rk3288-dp-phy", .data = &rk3288_dp_phy_data },
167
-	{ .compatible = "rockchip,rk3368-dp-phy", .data = &rk3368_dp_phy_data },
133
+	{ .compatible = "rockchip,rk3288-dp-phy" },
168134 	{}
169135 };
170136