~hc/RK356X_SDK_RELEASE.git

..	..	@@ -21,11 +21,24 @@
21	21	#include <media/v4l2-fwnode.h>
22	22	#include <media/v4l2-subdev.h>
23	23	#include <media/v4l2-device.h>
	24	+#include <linux/reset.h>
24	25	#include "phy-rockchip-csi2-dphy-common.h"
	26	+
	27	+/* RK3562 DPHY GRF REG OFFSET */
	28	+#define RK3562_GRF_VI_CON0 (0x0520)
	29	+#define RK3562_GRF_VI_CON1 (0x0524)
25	30
26	31	/* GRF REG OFFSET */
27	32	#define GRF_VI_CON0 (0x0340)
28	33	#define GRF_VI_CON1 (0x0344)
	34	+
	35	+/RK3588 DPHY GRF REG OFFSET /
	36	+#define GRF_DPHY_CON0 (0x0)
	37	+#define GRF_SOC_CON2 (0x0308)
	38	+
	39	+/RV1106 DPHY GRF REG OFFSET /
	40	+#define GRF_VI_MISC_CON0 (0x50000)
	41	+#define GRF_VI_CSIPHY_CON5 (0x50014)
29	42
30	43	/GRF REG BIT DEFINE /
31	44	#define GRF_CSI2PHY_LANE_SEL_SPLIT (0x1)
..	..	@@ -37,7 +50,11 @@
37	50	#define CSI2_DPHY_CTRL_PWRCTL \
38	51	CSI2_DPHY_CTRL_INVALID_OFFSET
39	52	#define CSI2_DPHY_CTRL_LANE_ENABLE (0x00)
	53	+#define CSI2_DPHY_CLK1_LANE_EN (0x2C)
40	54	#define CSI2_DPHY_DUAL_CAL_EN (0x80)
	55	+#define CSI2_DPHY_CLK_INV (0X84)
	56	+
	57	+#define CSI2_DPHY_CLK_CONTINUE_MODE (0x128)
41	58	#define CSI2_DPHY_CLK_WR_THS_SETTLE (0x160)
42	59	#define CSI2_DPHY_CLK_CALIB_EN (0x168)
43	60	#define CSI2_DPHY_LANE0_WR_THS_SETTLE (0x1e0)
..	..	@@ -48,8 +65,14 @@
48	65	#define CSI2_DPHY_LANE2_CALIB_EN (0x2e8)
49	66	#define CSI2_DPHY_LANE3_WR_THS_SETTLE (0x360)
50	67	#define CSI2_DPHY_LANE3_CALIB_EN (0x368)
	68	+#define CSI2_DPHY_CLK1_CONTINUE_MODE (0x3a8)
51	69	#define CSI2_DPHY_CLK1_WR_THS_SETTLE (0x3e0)
52	70	#define CSI2_DPHY_CLK1_CALIB_EN (0x3e8)
	71	+
	72	+#define CSI2_DPHY_PATH0_MODE_SEL (0x44C)
	73	+#define CSI2_DPHY_PATH0_LVDS_MODE_SEL (0x480)
	74	+#define CSI2_DPHY_PATH1_MODE_SEL (0x84C)
	75	+#define CSI2_DPHY_PATH1_LVDS_MODE_SEL (0x880)
53	76
54	77	/* PHY REG BIT DEFINE */
55	78	#define CSI2_DPHY_LANE_MODE_FULL (0x4)
..	..	@@ -128,8 +151,26 @@
128	151	GRF_DPHY_ISP_CSI2PHY_SEL,
129	152	GRF_DPHY_CIF_CSI2PHY_SEL,
130	153	GRF_DPHY_CSI2PHY_LANE_SEL,
	154	+ GRF_DPHY_CSI2PHY1_LANE_SEL,
131	155	GRF_DPHY_CSI2PHY_DATALANE_EN0,
132	156	GRF_DPHY_CSI2PHY_DATALANE_EN1,
	157	+ GRF_CPHY_MODE,
	158	+ GRF_DPHY_CSIHOST2_SEL,
	159	+ GRF_DPHY_CSIHOST3_SEL,
	160	+ GRF_DPHY_CSIHOST4_SEL,
	161	+ GRF_DPHY_CSIHOST5_SEL,
	162	+ /* below is for rv1106 only */
	163	+ GRF_MIPI_HOST0_SEL,
	164	+ GRF_LVDS_HOST0_SEL,
	165	+ /* below is for rk3562 */
	166	+ GRF_DPHY1_CLK_INV_SEL,
	167	+ GRF_DPHY1_CLK1_INV_SEL,
	168	+ GRF_DPHY1_CSI2PHY_CLKLANE1_EN,
	169	+ GRF_DPHY1_CSI2PHY_FORCERXMODE,
	170	+ GRF_DPHY1_CSI2PHY_CLKLANE_EN,
	171	+ GRF_DPHY1_CSI2PHY_DATALANE_EN,
	172	+ GRF_DPHY1_CSI2PHY_DATALANE_EN0,
	173	+ GRF_DPHY1_CSI2PHY_DATALANE_EN1,
133	174	};
134	175
135	176	enum csi2dphy_reg_id {
..	..	@@ -152,7 +193,30 @@
152	193	//rk3568 only
153	194	CSI2PHY_DUAL_CLK_EN,
154	195	CSI2PHY_CLK1_THS_SETTLE,
155		- CSI2PHY_CLK1_CALIB_ENABLE
	196	+ CSI2PHY_CLK1_CALIB_ENABLE,
	197	+ //rk3588
	198	+ CSI2PHY_CLK_LANE_ENABLE,
	199	+ CSI2PHY_CLK1_LANE_ENABLE,
	200	+ CSI2PHY_DATA_LANE0_ENABLE,
	201	+ CSI2PHY_DATA_LANE1_ENABLE,
	202	+ CSI2PHY_DATA_LANE2_ENABLE,
	203	+ CSI2PHY_DATA_LANE3_ENABLE,
	204	+ CSI2PHY_LANE0_ERR_SOT_SYNC,
	205	+ CSI2PHY_LANE1_ERR_SOT_SYNC,
	206	+ CSI2PHY_LANE2_ERR_SOT_SYNC,
	207	+ CSI2PHY_LANE3_ERR_SOT_SYNC,
	208	+ CSI2PHY_S0C_GNR_CON1,
	209	+ CSI2PHY_COMBO_S0D0_GNR_CON1,
	210	+ CSI2PHY_COMBO_S0D1_GNR_CON1,
	211	+ CSI2PHY_COMBO_S0D2_GNR_CON1,
	212	+ CSI2PHY_S0D3_GNR_CON1,
	213	+ CSI2PHY_PATH0_MODEL,
	214	+ CSI2PHY_PATH0_LVDS_MODEL,
	215	+ CSI2PHY_PATH1_MODEL,
	216	+ CSI2PHY_PATH1_LVDS_MODEL,
	217	+ CSI2PHY_CLK_INV,
	218	+ CSI2PHY_CLK_CONTINUE_MODE,
	219	+ CSI2PHY_CLK1_CONTINUE_MODE,
156	220	};
157	221
158	222	#define HIWORD_UPDATE(val, mask, shift) \
..	..	@@ -166,25 +230,49 @@
166	230
167	231	struct hsfreq_range {
168	232	u32 range_h;
169		- u8 cfg_bit;
	233	+ u16 cfg_bit;
170	234	};
	235	+
	236	+static inline void write_sys_grf_reg(struct csi2_dphy_hw *hw,
	237	+ int index, u8 value)
	238	+{
	239	+ const struct grf_reg *reg = NULL;
	240	+ unsigned int val = 0;
	241	+
	242	+ if (index >= hw->drv_data->num_grf_regs)
	243	+ return;
	244	+
	245	+ reg = &hw->grf_regs[index];
	246	+ val = HIWORD_UPDATE(value, reg->mask, reg->shift);
	247	+ if (reg->mask)
	248	+ regmap_write(hw->regmap_sys_grf, reg->offset, val);
	249	+}
171	250
172	251	static inline void write_grf_reg(struct csi2_dphy_hw *hw,
173	252	int index, u8 value)
174	253	{
175		- const struct grf_reg *reg = &hw->grf_regs[index];
176		- unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
	254	+ const struct grf_reg *reg = NULL;
	255	+ unsigned int val = 0;
177	256
178		- if (reg->offset)
	257	+ if (index >= hw->drv_data->num_grf_regs)
	258	+ return;
	259	+
	260	+ reg = &hw->grf_regs[index];
	261	+ val = HIWORD_UPDATE(value, reg->mask, reg->shift);
	262	+ if (reg->mask)
179	263	regmap_write(hw->regmap_grf, reg->offset, val);
180	264	}
181	265
182	266	static inline u32 read_grf_reg(struct csi2_dphy_hw *hw, int index)
183	267	{
184		- const struct grf_reg *reg = &hw->grf_regs[index];
	268	+ const struct grf_reg *reg = NULL;
185	269	unsigned int val = 0;
186	270
187		- if (reg->offset) {
	271	+ if (index >= hw->drv_data->num_grf_regs)
	272	+ return -EINVAL;
	273	+
	274	+ reg = &hw->grf_regs[index];
	275	+ if (reg->mask) {
188	276	regmap_read(hw->regmap_grf, reg->offset, &val);
189	277	val = (val >> reg->shift) & reg->mask;
190	278	}
..	..	@@ -195,20 +283,46 @@
195	283	static inline void write_csi2_dphy_reg(struct csi2_dphy_hw *hw,
196	284	int index, u32 value)
197	285	{
198		- const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
	286	+ const struct csi2dphy_reg *reg = NULL;
199	287
	288	+ if (index >= hw->drv_data->num_csi2dphy_regs)
	289	+ return;
	290	+
	291	+ reg = &hw->csi2dphy_regs[index];
200	292	if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) \|\|
	293	+ (index == CSI2PHY_CLK_LANE_ENABLE) \|\|
201	294	(index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
202	295	reg->offset != 0x0))
203	296	writel(value, hw->hw_base_addr + reg->offset);
204	297	}
205	298
	299	+static inline void write_csi2_dphy_reg_mask(struct csi2_dphy_hw *hw,
	300	+ int index, u32 value, u32 mask)
	301	+{
	302	+ const struct csi2dphy_reg *reg = NULL;
	303	+ u32 read_val = 0;
	304	+
	305	+ if (index >= hw->drv_data->num_csi2dphy_regs)
	306	+ return;
	307	+
	308	+ reg = &hw->csi2dphy_regs[index];
	309	+ read_val = readl(hw->hw_base_addr + reg->offset);
	310	+ read_val &= ~mask;
	311	+ read_val \|= value;
	312	+ writel(read_val, hw->hw_base_addr + reg->offset);
	313	+}
	314	+
206	315	static inline void read_csi2_dphy_reg(struct csi2_dphy_hw *hw,
207	316	int index, u32 *value)
208	317	{
209		- const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
	318	+ const struct csi2dphy_reg *reg = NULL;
210	319
	320	+ if (index >= hw->drv_data->num_csi2dphy_regs)
	321	+ return;
	322	+
	323	+ reg = &hw->csi2dphy_regs[index];
211	324	if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) \|\|
	325	+ (index == CSI2PHY_CLK_LANE_ENABLE) \|\|
212	326	(index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
213	327	reg->offset != 0x0))
214	328	*value = readl(hw->hw_base_addr + reg->offset);
..	..	@@ -280,8 +394,116 @@
280	394	[CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
281	395	};
282	396
283		-static const struct clk_bulk_data rk3568_csi2_dphy_hw_clks[] = {
284		- { .id = "pclk" },
	397	+static const struct grf_reg rk3588_grf_dphy_regs[] = {
	398	+ [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_DPHY_CON0, 4, 0),
	399	+ [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_DPHY_CON0, 4, 4),
	400	+ [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_DPHY_CON0, 2, 4),
	401	+ [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_DPHY_CON0, 2, 6),
	402	+ [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_DPHY_CON0, 1, 8),
	403	+ [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 9),
	404	+ [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_DPHY_CON0, 1, 10),
	405	+ [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 11),
	406	+ [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 6),
	407	+ [GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 7),
	408	+ [GRF_DPHY_CSIHOST2_SEL] = GRF_REG(GRF_SOC_CON2, 1, 8),
	409	+ [GRF_DPHY_CSIHOST3_SEL] = GRF_REG(GRF_SOC_CON2, 1, 9),
	410	+ [GRF_DPHY_CSIHOST4_SEL] = GRF_REG(GRF_SOC_CON2, 1, 10),
	411	+ [GRF_DPHY_CSIHOST5_SEL] = GRF_REG(GRF_SOC_CON2, 1, 11),
	412	+};
	413	+
	414	+static const struct csi2dphy_reg rk3588_csi2dphy_regs[] = {
	415	+ [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
	416	+ [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
	417	+ [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
	418	+ [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
	419	+ [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
	420	+ [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
	421	+ [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
	422	+ [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
	423	+ [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
	424	+ [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
	425	+ [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
	426	+ [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
	427	+ [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
	428	+ [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
	429	+ [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
	430	+ [CSI2PHY_CLK_CONTINUE_MODE] = CSI2PHY_REG(CSI2_DPHY_CLK_CONTINUE_MODE),
	431	+ [CSI2PHY_CLK1_CONTINUE_MODE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CONTINUE_MODE),
	432	+};
	433	+
	434	+static const struct grf_reg rv1106_grf_dphy_regs[] = {
	435	+ [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CSIPHY_CON5, 4, 0),
	436	+ [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 8),
	437	+ [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 4, 4),
	438	+ [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_VI_CSIPHY_CON5, 2, 4),
	439	+ [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_VI_CSIPHY_CON5, 2, 6),
	440	+ [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 9),
	441	+ [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 10),
	442	+ [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 11),
	443	+ [GRF_MIPI_HOST0_SEL] = GRF_REG(GRF_VI_MISC_CON0, 1, 0),
	444	+ [GRF_LVDS_HOST0_SEL] = GRF_REG(GRF_VI_MISC_CON0, 1, 2),
	445	+};
	446	+
	447	+static const struct csi2dphy_reg rv1106_csi2dphy_regs[] = {
	448	+ [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
	449	+ [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
	450	+ [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
	451	+ [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
	452	+ [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
	453	+ [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
	454	+ [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
	455	+ [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
	456	+ [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
	457	+ [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
	458	+ [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
	459	+ [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
	460	+ [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
	461	+ [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
	462	+ [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
	463	+ [CSI2PHY_PATH0_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH0_MODE_SEL),
	464	+ [CSI2PHY_PATH0_LVDS_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH0_LVDS_MODE_SEL),
	465	+ [CSI2PHY_PATH1_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH1_MODE_SEL),
	466	+ [CSI2PHY_PATH1_LVDS_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH1_LVDS_MODE_SEL),
	467	+ [CSI2PHY_CLK_INV] = CSI2PHY_REG(CSI2_DPHY_CLK_INV),
	468	+};
	469	+
	470	+static const struct grf_reg rk3562_grf_dphy_regs[] = {
	471	+ [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(RK3562_GRF_VI_CON0, 4, 0),
	472	+ [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(RK3562_GRF_VI_CON0, 4, 4),
	473	+ [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(RK3562_GRF_VI_CON0, 2, 4),
	474	+ [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(RK3562_GRF_VI_CON0, 2, 6),
	475	+ [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(RK3562_GRF_VI_CON0, 1, 8),
	476	+ [GRF_DPHY_CLK_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 9),
	477	+ [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(RK3562_GRF_VI_CON0, 1, 10),
	478	+ [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 11),
	479	+ [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 12),
	480	+ [GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 13),
	481	+ [GRF_DPHY1_CSI2PHY_FORCERXMODE] = GRF_REG(RK3562_GRF_VI_CON1, 4, 0),
	482	+ [GRF_DPHY1_CSI2PHY_DATALANE_EN] = GRF_REG(RK3562_GRF_VI_CON1, 4, 4),
	483	+ [GRF_DPHY1_CSI2PHY_DATALANE_EN0] = GRF_REG(RK3562_GRF_VI_CON1, 2, 4),
	484	+ [GRF_DPHY1_CSI2PHY_DATALANE_EN1] = GRF_REG(RK3562_GRF_VI_CON1, 2, 6),
	485	+ [GRF_DPHY1_CSI2PHY_CLKLANE_EN] = GRF_REG(RK3562_GRF_VI_CON1, 1, 8),
	486	+ [GRF_DPHY1_CLK_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON1, 1, 9),
	487	+ [GRF_DPHY1_CSI2PHY_CLKLANE1_EN] = GRF_REG(RK3562_GRF_VI_CON1, 1, 10),
	488	+ [GRF_DPHY1_CLK1_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON1, 1, 11),
	489	+};
	490	+
	491	+static const struct csi2dphy_reg rk3562_csi2dphy_regs[] = {
	492	+ [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
	493	+ [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
	494	+ [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
	495	+ [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
	496	+ [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
	497	+ [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
	498	+ [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
	499	+ [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
	500	+ [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
	501	+ [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
	502	+ [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
	503	+ [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
	504	+ [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
	505	+ [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
	506	+ [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
285	507	};
286	508
287	509	/* These tables must be sorted by .range_h ascending. */
..	..	@@ -321,6 +543,51 @@
321	543	return NULL;
322	544	}
323	545
	546	+static unsigned char get_lvds_data_width(u32 pixelformat)
	547	+{
	548	+ switch (pixelformat) {
	549	+ /* csi raw8 */
	550	+ case MEDIA_BUS_FMT_SBGGR8_1X8:
	551	+ case MEDIA_BUS_FMT_SGBRG8_1X8:
	552	+ case MEDIA_BUS_FMT_SGRBG8_1X8:
	553	+ case MEDIA_BUS_FMT_SRGGB8_1X8:
	554	+ return 0x2;
	555	+ /* csi raw10 */
	556	+ case MEDIA_BUS_FMT_SBGGR10_1X10:
	557	+ case MEDIA_BUS_FMT_SGBRG10_1X10:
	558	+ case MEDIA_BUS_FMT_SGRBG10_1X10:
	559	+ case MEDIA_BUS_FMT_SRGGB10_1X10:
	560	+ return 0x0;
	561	+ /* csi raw12 */
	562	+ case MEDIA_BUS_FMT_SBGGR12_1X12:
	563	+ case MEDIA_BUS_FMT_SGBRG12_1X12:
	564	+ case MEDIA_BUS_FMT_SGRBG12_1X12:
	565	+ case MEDIA_BUS_FMT_SRGGB12_1X12:
	566	+ return 0x1;
	567	+ /* csi uyvy 422 */
	568	+ case MEDIA_BUS_FMT_UYVY8_2X8:
	569	+ case MEDIA_BUS_FMT_VYUY8_2X8:
	570	+ case MEDIA_BUS_FMT_YUYV8_2X8:
	571	+ case MEDIA_BUS_FMT_YVYU8_2X8:
	572	+ case MEDIA_BUS_FMT_RGB888_1X24:
	573	+ return 0x2;
	574	+
	575	+ default:
	576	+ return 0x2;
	577	+ }
	578	+}
	579	+
	580	+static void csi2_dphy_hw_do_reset(struct csi2_dphy_hw *hw)
	581	+{
	582	+ if (hw->rsts_bulk)
	583	+ reset_control_assert(hw->rsts_bulk);
	584	+
	585	+ udelay(5);
	586	+
	587	+ if (hw->rsts_bulk)
	588	+ reset_control_deassert(hw->rsts_bulk);
	589	+}
	590	+
324	591	static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy,
325	592	struct csi2_sensor *sensor)
326	593	{
..	..	@@ -337,38 +604,108 @@
337	604	is_cif = false;
338	605
339	606	if (hw->lane_mode == LANE_MODE_FULL) {
340		- val = ~GRF_CSI2PHY_LANE_SEL_SPLIT;
341		- write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
342		- write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
343		- GENMASK(sensor->lanes - 1, 0));
344		- write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
	607	+ val = !GRF_CSI2PHY_LANE_SEL_SPLIT;
	608	+ if (dphy->phy_index < 3) {
	609	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
	610	+ GENMASK(sensor->lanes - 1, 0));
	611	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
	612	+ if (hw->drv_data->chip_id != CHIP_ID_RK3588)
	613	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
	614	+ else
	615	+ write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
	616	+ } else {
	617	+ if (hw->drv_data->chip_id <= CHIP_ID_RK3588) {
	618	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
	619	+ GENMASK(sensor->lanes - 1, 0));
	620	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
	621	+ } else {
	622	+ write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN,
	623	+ GENMASK(sensor->lanes - 1, 0));
	624	+ write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE_EN, 0x1);
	625	+ }
	626	+ if (hw->drv_data->chip_id != CHIP_ID_RK3588)
	627	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
	628	+ else
	629	+ write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
	630	+ }
345	631	} else {
346	632	val = GRF_CSI2PHY_LANE_SEL_SPLIT;
347		- write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
348	633
349		- if (dphy->phy_index == DPHY1) {
	634	+ switch (dphy->phy_index) {
	635	+ case 1:
350	636	write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0,
351	637	GENMASK(sensor->lanes - 1, 0));
352	638	write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
353		- if (is_cif)
354		- write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
355		- GRF_CSI2PHY_SEL_SPLIT_0_1);
356		- else
357		- write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
358		- GRF_CSI2PHY_SEL_SPLIT_0_1);
359		- }
360		-
361		- if (dphy->phy_index == DPHY2) {
	639	+ if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
	640	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
	641	+ if (is_cif)
	642	+ write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
	643	+ GRF_CSI2PHY_SEL_SPLIT_0_1);
	644	+ else
	645	+ write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
	646	+ GRF_CSI2PHY_SEL_SPLIT_0_1);
	647	+ } else if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
	648	+ write_sys_grf_reg(hw, GRF_DPHY_CSIHOST2_SEL, 0x0);
	649	+ write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
	650	+ } else if (hw->drv_data->chip_id == CHIP_ID_RV1106) {
	651	+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY)
	652	+ write_grf_reg(hw, GRF_MIPI_HOST0_SEL, 0x1);
	653	+ else
	654	+ write_grf_reg(hw, GRF_LVDS_HOST0_SEL, 0x1);
	655	+ } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
	656	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
	657	+ }
	658	+ break;
	659	+ case 2:
362	660	write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1,
363	661	GENMASK(sensor->lanes - 1, 0));
364	662	write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
365		- if (is_cif)
366		- write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
367		- GRF_CSI2PHY_SEL_SPLIT_2_3);
368		- else
369		- write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
370		- GRF_CSI2PHY_SEL_SPLIT_2_3);
371		- }
	663	+ if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
	664	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
	665	+ if (is_cif)
	666	+ write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
	667	+ GRF_CSI2PHY_SEL_SPLIT_2_3);
	668	+ else
	669	+ write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
	670	+ GRF_CSI2PHY_SEL_SPLIT_2_3);
	671	+ } else if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
	672	+ write_sys_grf_reg(hw, GRF_DPHY_CSIHOST3_SEL, 0x1);
	673	+ write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
	674	+ } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
	675	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
	676	+ }
	677	+ break;
	678	+ case 4:
	679	+ if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
	680	+ write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
	681	+ write_sys_grf_reg(hw, GRF_DPHY_CSIHOST4_SEL, 0x0);
	682	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0,
	683	+ GENMASK(sensor->lanes - 1, 0));
	684	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
	685	+ } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
	686	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
	687	+ write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN0,
	688	+ GENMASK(sensor->lanes - 1, 0));
	689	+ write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE_EN, 0x1);
	690	+ }
	691	+ break;
	692	+ case 5:
	693	+ if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
	694	+ write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
	695	+ write_sys_grf_reg(hw, GRF_DPHY_CSIHOST5_SEL, 0x1);
	696	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1,
	697	+ GENMASK(sensor->lanes - 1, 0));
	698	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
	699	+ } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
	700	+ write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
	701	+ write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN1,
	702	+ GENMASK(sensor->lanes - 1, 0));
	703	+ write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE1_EN, 0x1);
	704	+ }
	705	+ break;
	706	+ default:
	707	+ break;
	708	+ };
372	709	}
373	710	}
374	711
..	..	@@ -376,13 +713,20 @@
376	713	struct v4l2_subdev *sd)
377	714	{
378	715	struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
379		- struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
	716	+ struct csi2_sensor *sensor;
380	717	struct csi2_dphy_hw *hw = dphy->dphy_hw;
381	718	const struct dphy_hw_drv_data *drv_data = hw->drv_data;
382	719	const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
383	720	int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
384	721	int i, hsfreq = 0;
385	722	u32 val = 0, pre_val;
	723	+ u8 lvds_width = 0;
	724	+
	725	+ if (!sensor_sd)
	726	+ return -ENODEV;
	727	+ sensor = sd_to_sensor(dphy, sensor_sd);
	728	+ if (!sensor)
	729	+ return -ENODEV;
386	730
387	731	mutex_lock(&hw->mutex);
388	732
..	..	@@ -397,35 +741,47 @@
397	741	val \|= (GENMASK(sensor->lanes - 1, 0) <<
398	742	CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) \|
399	743	(0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
	744	+ if (sensor->mbus.flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK)
	745	+ write_csi2_dphy_reg(hw, CSI2PHY_CLK_CONTINUE_MODE, 0x30);
400	746	} else {
401	747	if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
402	748	val \|= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
403	749
404		- if (dphy->phy_index == DPHY1)
	750	+ if (dphy->phy_index % 3 == DPHY1) {
405	751	val \|= (GENMASK(sensor->lanes - 1, 0) <<
406	752	CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
	753	+ if (sensor->mbus.flags &
	754	+ V4L2_MBUS_CSI2_CONTINUOUS_CLOCK)
	755	+ write_csi2_dphy_reg(
	756	+ hw, CSI2PHY_CLK_CONTINUE_MODE, 0x30);
	757	+ }
407	758
408		- if (dphy->phy_index == DPHY2)
	759	+ if (dphy->phy_index % 3 == DPHY2) {
409	760	val \|= (GENMASK(sensor->lanes - 1, 0) <<
410	761	CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT);
	762	+ if (hw->drv_data->chip_id >= CHIP_ID_RK3588)
	763	+ write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(6));
	764	+ if (sensor->mbus.flags &
	765	+ V4L2_MBUS_CSI2_CONTINUOUS_CLOCK)
	766	+ write_csi2_dphy_reg(
	767	+ hw, CSI2PHY_CLK1_CONTINUE_MODE, 0x30);
	768	+ }
411	769	}
412	770	val \|= pre_val;
413	771	write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, val);
414	772
415		- if (sensor->mbus.type == V4L2_MBUS_CSI2) {
416		- /* Reset dphy digital part */
417		- if (hw->lane_mode == LANE_MODE_FULL) {
418		- write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1e);
419		- write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1f);
420		- } else {
421		- read_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, &val);
422		- if (!(val & CSI2_DPHY_LANE_DUAL_MODE_EN)) {
423		- write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5e);
424		- write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
425		- }
	773	+ /* Reset dphy digital part */
	774	+ if (hw->lane_mode == LANE_MODE_FULL) {
	775	+ write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1e);
	776	+ write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1f);
	777	+ } else {
	778	+ read_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, &val);
	779	+ if (!(val & CSI2_DPHY_LANE_DUAL_MODE_EN)) {
	780	+ write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5e);
	781	+ write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
426	782	}
427		- csi2_dphy_config_dual_mode(dphy, sensor);
428	783	}
	784	+ csi2_dphy_config_dual_mode(dphy, sensor);
429	785
430	786	/* not into receive mode/wait stopstate */
431	787	write_grf_reg(hw, GRF_DPHY_CSI2PHY_FORCERXMODE, 0x0);
..	..	@@ -443,7 +799,7 @@
443	799	if (sensor->lanes > 0x03)
444	800	write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
445	801	} else {
446		- if (dphy->phy_index == DPHY1) {
	802	+ if (dphy->phy_index % 3 == DPHY1) {
447	803	write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
448	804	if (sensor->lanes > 0x00)
449	805	write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
..	..	@@ -451,7 +807,7 @@
451	807	write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
452	808	}
453	809
454		- if (dphy->phy_index == DPHY2) {
	810	+ if (dphy->phy_index % 3 == DPHY2) {
455	811	write_csi2_dphy_reg(hw, CSI2PHY_CLK1_CALIB_ENABLE, 0x80);
456	812	if (sensor->lanes > 0x00)
457	813	write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
..	..	@@ -487,16 +843,43 @@
487	843	if (sensor->lanes > 0x03)
488	844	csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
489	845	} else {
490		- if (dphy->phy_index == DPHY1) {
	846	+ if (dphy->phy_index % 3 == DPHY1) {
491	847	csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
492	848	csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
493	849	csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
494	850	}
495	851
496		- if (dphy->phy_index == DPHY2) {
	852	+ if (dphy->phy_index % 3 == DPHY2) {
497	853	csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK1);
498	854	csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
499	855	csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
	856	+ }
	857	+ }
	858	+
	859	+ if (hw->drv_data->chip_id == CHIP_ID_RV1106) {
	860	+ if (dphy->phy_index % 3 == DPHY0 \|\|
	861	+ dphy->phy_index % 3 == DPHY1) {
	862	+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
	863	+ write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x2);
	864	+ } else {
	865	+ write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x4);
	866	+ lvds_width = get_lvds_data_width(sensor->format.code);
	867	+ write_csi2_dphy_reg(hw, CSI2PHY_PATH0_LVDS_MODEL, (lvds_width << 4) \| 0X0f);
	868	+ }
	869	+ } else {
	870	+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
	871	+ write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x2);
	872	+ } else {
	873	+ write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x4);
	874	+ lvds_width = get_lvds_data_width(sensor->format.code);
	875	+ write_csi2_dphy_reg(hw, CSI2PHY_PATH1_LVDS_MODEL, (lvds_width << 4) \| 0X0f);
	876	+ }
	877	+ }
	878	+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
	879	+ if (hw->lane_mode == LANE_MODE_FULL)
	880	+ write_csi2_dphy_reg(hw, CSI2PHY_CLK_INV, 0x04);
	881	+ else
	882	+ write_csi2_dphy_reg(hw, CSI2PHY_CLK_INV, 0x14);
500	883	}
501	884	}
502	885
..	..	@@ -518,11 +901,112 @@
518	901	mutex_lock(&hw->mutex);
519	902
520	903	write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
521		- usleep_range(500, 1000);
	904	+ csi2_dphy_hw_do_reset(hw);
522	905
523	906	mutex_unlock(&hw->mutex);
524	907
525	908	return 0;
	909	+}
	910	+
	911	+static int csi2_dphy_hw_quick_stream_on(struct csi2_dphy *dphy,
	912	+ struct v4l2_subdev *sd)
	913	+{
	914	+ struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
	915	+ struct csi2_sensor *sensor;
	916	+ struct csi2_dphy_hw *hw = dphy->dphy_hw;
	917	+ u32 val = 0, pre_val = 0;
	918	+
	919	+ if (!sensor_sd)
	920	+ return -ENODEV;
	921	+ sensor = sd_to_sensor(dphy, sensor_sd);
	922	+ if (!sensor)
	923	+ return -ENODEV;
	924	+
	925	+ read_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, &pre_val);
	926	+ if (hw->lane_mode == LANE_MODE_FULL) {
	927	+ val \|= (GENMASK(sensor->lanes - 1, 0) <<
	928	+ CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) \|
	929	+ (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
	930	+ } else {
	931	+ if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
	932	+ val \|= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
	933	+
	934	+ if (dphy->phy_index % 3 == DPHY1)
	935	+ val \|= (GENMASK(sensor->lanes - 1, 0) <<
	936	+ CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
	937	+
	938	+ if (dphy->phy_index % 3 == DPHY2) {
	939	+ val \|= (GENMASK(sensor->lanes - 1, 0) <<
	940	+ CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT);
	941	+ if (hw->drv_data->chip_id >= CHIP_ID_RK3588)
	942	+ write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(6));
	943	+ }
	944	+ }
	945	+ pre_val \|= val;
	946	+ write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, pre_val);
	947	+ return 0;
	948	+}
	949	+
	950	+static int csi2_dphy_hw_quick_stream_off(struct csi2_dphy *dphy,
	951	+ struct v4l2_subdev *sd)
	952	+{
	953	+ struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
	954	+ struct csi2_sensor *sensor;
	955	+ struct csi2_dphy_hw *hw = dphy->dphy_hw;
	956	+ u32 val = 0, pre_val = 0;
	957	+
	958	+ if (!sensor_sd)
	959	+ return -ENODEV;
	960	+ sensor = sd_to_sensor(dphy, sensor_sd);
	961	+ if (!sensor)
	962	+ return -ENODEV;
	963	+
	964	+ read_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, &pre_val);
	965	+ if (hw->lane_mode == LANE_MODE_FULL) {
	966	+ val \|= (GENMASK(sensor->lanes - 1, 0) <<
	967	+ CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) \|
	968	+ (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
	969	+ } else {
	970	+ if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
	971	+ val \|= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
	972	+
	973	+ if (dphy->phy_index % 3 == DPHY1)
	974	+ val \|= (GENMASK(sensor->lanes - 1, 0) <<
	975	+ CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
	976	+
	977	+ if (dphy->phy_index % 3 == DPHY2) {
	978	+ val \|= (GENMASK(sensor->lanes - 1, 0) <<
	979	+ CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT);
	980	+ if (hw->drv_data->chip_id >= CHIP_ID_RK3588)
	981	+ write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(6));
	982	+ }
	983	+ }
	984	+ pre_val &= ~val;
	985	+ write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, pre_val);
	986	+ return 0;
	987	+}
	988	+
	989	+static int csi2_dphy_hw_ttl_mode_enable(struct csi2_dphy_hw *hw)
	990	+{
	991	+ int ret = 0;
	992	+
	993	+ ret = clk_bulk_prepare_enable(hw->num_clks, hw->clks_bulk);
	994	+ if (ret) {
	995	+ dev_err(hw->dev, "failed to enable clks\n");
	996	+ return ret;
	997	+ }
	998	+
	999	+ write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x7d);
	1000	+ write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
	1001	+ write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x1);
	1002	+ write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x1);
	1003	+ return ret;
	1004	+}
	1005	+
	1006	+static void csi2_dphy_hw_ttl_mode_disable(struct csi2_dphy_hw *hw)
	1007	+{
	1008	+ write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
	1009	+ clk_bulk_disable_unprepare(hw->num_clks, hw->clks_bulk);
526	1010	}
527	1011
528	1012	static void rk3568_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
..	..	@@ -530,21 +1014,89 @@
530	1014	hw->grf_regs = rk3568_grf_dphy_regs;
531	1015	}
532	1016
	1017	+static void rk3588_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
	1018	+{
	1019	+ hw->grf_regs = rk3588_grf_dphy_regs;
	1020	+}
	1021	+
	1022	+static void rv1106_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
	1023	+{
	1024	+ hw->grf_regs = rv1106_grf_dphy_regs;
	1025	+}
	1026	+
	1027	+static void rk3562_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
	1028	+{
	1029	+ hw->grf_regs = rk3562_grf_dphy_regs;
	1030	+}
	1031	+
533	1032	static const struct dphy_hw_drv_data rk3568_csi2_dphy_hw_drv_data = {
534		- .clks = rk3568_csi2_dphy_hw_clks,
535		- .num_clks = ARRAY_SIZE(rk3568_csi2_dphy_hw_clks),
536	1033	.hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
537	1034	.num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
538	1035	.csi2dphy_regs = rk3568_csi2dphy_regs,
	1036	+ .num_csi2dphy_regs = ARRAY_SIZE(rk3568_csi2dphy_regs),
539	1037	.grf_regs = rk3568_grf_dphy_regs,
	1038	+ .num_grf_regs = ARRAY_SIZE(rk3568_grf_dphy_regs),
540	1039	.individual_init = rk3568_csi2_dphy_hw_individual_init,
541	1040	.chip_id = CHIP_ID_RK3568,
	1041	+ .stream_on = csi2_dphy_hw_stream_on,
	1042	+ .stream_off = csi2_dphy_hw_stream_off,
	1043	+};
	1044	+
	1045	+static const struct dphy_hw_drv_data rk3588_csi2_dphy_hw_drv_data = {
	1046	+ .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
	1047	+ .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
	1048	+ .csi2dphy_regs = rk3588_csi2dphy_regs,
	1049	+ .num_csi2dphy_regs = ARRAY_SIZE(rk3588_csi2dphy_regs),
	1050	+ .grf_regs = rk3588_grf_dphy_regs,
	1051	+ .num_grf_regs = ARRAY_SIZE(rk3588_grf_dphy_regs),
	1052	+ .individual_init = rk3588_csi2_dphy_hw_individual_init,
	1053	+ .chip_id = CHIP_ID_RK3588,
	1054	+ .stream_on = csi2_dphy_hw_stream_on,
	1055	+ .stream_off = csi2_dphy_hw_stream_off,
	1056	+};
	1057	+
	1058	+static const struct dphy_hw_drv_data rv1106_csi2_dphy_hw_drv_data = {
	1059	+ .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
	1060	+ .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
	1061	+ .csi2dphy_regs = rv1106_csi2dphy_regs,
	1062	+ .num_csi2dphy_regs = ARRAY_SIZE(rv1106_csi2dphy_regs),
	1063	+ .grf_regs = rv1106_grf_dphy_regs,
	1064	+ .num_grf_regs = ARRAY_SIZE(rv1106_grf_dphy_regs),
	1065	+ .individual_init = rv1106_csi2_dphy_hw_individual_init,
	1066	+ .chip_id = CHIP_ID_RV1106,
	1067	+ .stream_on = csi2_dphy_hw_stream_on,
	1068	+ .stream_off = csi2_dphy_hw_stream_off,
	1069	+};
	1070	+
	1071	+static const struct dphy_hw_drv_data rk3562_csi2_dphy_hw_drv_data = {
	1072	+ .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
	1073	+ .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
	1074	+ .csi2dphy_regs = rk3562_csi2dphy_regs,
	1075	+ .num_csi2dphy_regs = ARRAY_SIZE(rk3562_csi2dphy_regs),
	1076	+ .grf_regs = rk3562_grf_dphy_regs,
	1077	+ .num_grf_regs = ARRAY_SIZE(rk3562_grf_dphy_regs),
	1078	+ .individual_init = rk3562_csi2_dphy_hw_individual_init,
	1079	+ .chip_id = CHIP_ID_RK3562,
	1080	+ .stream_on = csi2_dphy_hw_stream_on,
	1081	+ .stream_off = csi2_dphy_hw_stream_off,
542	1082	};
543	1083
544	1084	static const struct of_device_id rockchip_csi2_dphy_hw_match_id[] = {
545	1085	{
546	1086	.compatible = "rockchip,rk3568-csi2-dphy-hw",
547	1087	.data = &rk3568_csi2_dphy_hw_drv_data,
	1088	+ },
	1089	+ {
	1090	+ .compatible = "rockchip,rk3588-csi2-dphy-hw",
	1091	+ .data = &rk3588_csi2_dphy_hw_drv_data,
	1092	+ },
	1093	+ {
	1094	+ .compatible = "rockchip,rv1106-csi2-dphy-hw",
	1095	+ .data = &rv1106_csi2_dphy_hw_drv_data,
	1096	+ },
	1097	+ {
	1098	+ .compatible = "rockchip,rk3562-csi2-dphy-hw",
	1099	+ .data = &rk3562_csi2_dphy_hw_drv_data,
548	1100	},
549	1101	{}
550	1102	};
..	..	@@ -558,7 +1110,6 @@
558	1110	struct resource *res;
559	1111	const struct of_device_id *of_id;
560	1112	const struct dphy_hw_drv_data *drv_data;
561		- int ret;
562	1113
563	1114	dphy_hw = devm_kzalloc(dev, sizeof(*dphy_hw), GFP_KERNEL);
564	1115	if (!dphy_hw)
..	..	@@ -569,39 +1120,38 @@
569	1120	if (!of_id)
570	1121	return -EINVAL;
571	1122
572		- grf = syscon_node_to_regmap(dev->parent->of_node);
	1123	+ drv_data = of_id->data;
	1124	+
	1125	+ grf = syscon_regmap_lookup_by_phandle(dev->of_node,
	1126	+ "rockchip,grf");
573	1127	if (IS_ERR(grf)) {
574		- grf = syscon_regmap_lookup_by_phandle(dev->of_node,
575		- "rockchip,grf");
576		- if (IS_ERR(grf)) {
577		- dev_err(dev, "Can't find GRF syscon\n");
578		- return -ENODEV;
579		- }
	1128	+ dev_err(dev, "Can't find GRF syscon\n");
	1129	+ return -ENODEV;
580	1130	}
581	1131	dphy_hw->regmap_grf = grf;
582	1132
583		- drv_data = of_id->data;
584		- dphy_hw->num_clks = drv_data->num_clks;
585		- dphy_hw->clks = devm_kmemdup(dev, drv_data->clks,
586		- drv_data->num_clks * sizeof(struct clk_bulk_data),
587		- GFP_KERNEL);
588		- if (!dphy_hw->clks) {
589		- dev_err(dev, "failed to acquire csi2 dphy clks mem\n");
590		- return -ENOMEM;
	1133	+ if (drv_data->chip_id == CHIP_ID_RK3588) {
	1134	+ grf = syscon_regmap_lookup_by_phandle(dev->of_node,
	1135	+ "rockchip,sys_grf");
	1136	+ if (IS_ERR(grf)) {
	1137	+ dev_err(dev, "Can't find SYS GRF syscon\n");
	1138	+ return -ENODEV;
	1139	+ }
	1140	+ dphy_hw->regmap_sys_grf = grf;
591	1141	}
592		- ret = devm_clk_bulk_get(dev, dphy_hw->num_clks, dphy_hw->clks);
593		- if (ret == -EPROBE_DEFER) {
594		- dev_err(dev, "get csi2 dphy clks failed\n");
595		- return -EPROBE_DEFER;
596		- }
597		- if (ret)
598		- dphy_hw->num_clks = 0;
	1142	+
	1143	+ dphy_hw->num_clks = devm_clk_bulk_get_all(dev, &dphy_hw->clks_bulk);
	1144	+ if (dphy_hw->num_clks < 0)
	1145	+ dev_err(dev, "failed to get csi2 clks\n");
	1146	+
	1147	+ dphy_hw->rsts_bulk = devm_reset_control_array_get_optional_exclusive(dev);
	1148	+ if (IS_ERR(dphy_hw->rsts_bulk))
	1149	+ dev_err_probe(dev, PTR_ERR(dphy_hw->rsts_bulk), "failed to get dphy reset\n");
599	1150
600	1151	dphy_hw->dphy_dev_num = 0;
601	1152	dphy_hw->drv_data = drv_data;
602	1153	dphy_hw->lane_mode = LANE_MODE_UNDEF;
603	1154	dphy_hw->grf_regs = drv_data->grf_regs;
604		- dphy_hw->txrx_regs = drv_data->txrx_regs;
605	1155	dphy_hw->csi2dphy_regs = drv_data->csi2dphy_regs;
606	1156
607	1157	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
..	..	@@ -616,8 +1166,18 @@
616	1166	return -ENODEV;
617	1167	}
618	1168	}
619		- dphy_hw->stream_on = csi2_dphy_hw_stream_on;
620		- dphy_hw->stream_off = csi2_dphy_hw_stream_off;
	1169	+ dphy_hw->stream_on = drv_data->stream_on;
	1170	+ dphy_hw->stream_off = drv_data->stream_off;
	1171	+ dphy_hw->quick_stream_on = csi2_dphy_hw_quick_stream_on;
	1172	+ dphy_hw->quick_stream_off = csi2_dphy_hw_quick_stream_off;
	1173	+
	1174	+ if (drv_data->chip_id == CHIP_ID_RV1106) {
	1175	+ dphy_hw->ttl_mode_enable = csi2_dphy_hw_ttl_mode_enable;
	1176	+ dphy_hw->ttl_mode_disable = csi2_dphy_hw_ttl_mode_disable;
	1177	+ } else {
	1178	+ dphy_hw->ttl_mode_enable = NULL;
	1179	+ dphy_hw->ttl_mode_disable = NULL;
	1180	+ }
621	1181
622	1182	atomic_set(&dphy_hw->stream_cnt, 0);
623	1183
..	..	@@ -626,8 +1186,6 @@
626	1186	platform_set_drvdata(pdev, dphy_hw);
627	1187
628	1188	pm_runtime_enable(&pdev->dev);
629		-
630		- platform_driver_register(&rockchip_csi2_dphy_driver);
631	1189
632	1190	dev_info(dev, "csi2 dphy hw probe successfully!\n");
633	1191
..	..	@@ -652,7 +1210,19 @@
652	1210	.of_match_table = rockchip_csi2_dphy_hw_match_id,
653	1211	},
654	1212	};
	1213	+
	1214	+int rockchip_csi2_dphy_hw_init(void)
	1215	+{
	1216	+ return platform_driver_register(&rockchip_csi2_dphy_hw_driver);
	1217	+}
	1218	+
	1219	+#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
	1220	+subsys_initcall(rockchip_csi2_dphy_hw_init);
	1221	+#else
	1222	+#if !defined(CONFIG_VIDEO_REVERSE_IMAGE)
655	1223	module_platform_driver(rockchip_csi2_dphy_hw_driver);
	1224	+#endif
	1225	+#endif
656	1226
657	1227	MODULE_AUTHOR("Rockchip Camera/ISP team");
658	1228	MODULE_DESCRIPTION("Rockchip MIPI CSI2 DPHY HW driver");