forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811
kernel/drivers/phy/rockchip/phy-rockchip-csi2-dphy-common.h
....@@ -8,9 +8,23 @@
88 #ifndef _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_
99 #define _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_
1010
11
+#include <linux/rk-camera-module.h>
12
+#include <linux/rkcif-config.h>
13
+
14
+#define PHY_MAX 16
15
+#define MAX_DEV_NAME_LEN 32
16
+
17
+#define MAX_SAMSUNG_PHY_NUM 2
18
+
19
+#define MAX_INNO_PHY_NUM 2
20
+
1121 /* add new chip id in tail by time order */
1222 enum csi2_dphy_chip_id {
1323 CHIP_ID_RK3568 = 0x0,
24
+ CHIP_ID_RK3588 = 0x1,
25
+ CHIP_ID_RK3588_DCPHY = 0x2,
26
+ CHIP_ID_RV1106 = 0x3,
27
+ CHIP_ID_RK3562 = 0x4,
1428 };
1529
1630 enum csi2_dphy_rx_pads {
....@@ -46,11 +60,22 @@
4660 };
4761
4862 struct csi2_dphy_hw;
63
+struct samsung_mipi_dcphy;
64
+
65
+struct dphy_drv_data {
66
+ const char dev_name[MAX_DEV_NAME_LEN];
67
+ enum csi2_dphy_chip_id chip_id;
68
+ char num_inno_phy;
69
+ char num_samsung_phy;
70
+};
4971
5072 struct csi2_dphy {
5173 struct device *dev;
5274 struct list_head list;
5375 struct csi2_dphy_hw *dphy_hw;
76
+ struct csi2_dphy_hw *dphy_hw_group[MAX_INNO_PHY_NUM];
77
+ struct samsung_mipi_dcphy *samsung_phy;
78
+ struct samsung_mipi_dcphy *samsung_phy_group[MAX_SAMSUNG_PHY_NUM];
5479 struct v4l2_async_notifier notifier;
5580 struct v4l2_subdev sd;
5681 struct mutex mutex; /* lock for updating protection */
....@@ -59,31 +84,39 @@
5984 u64 data_rate_mbps;
6085 int num_sensors;
6186 int phy_index;
87
+ struct rkcif_csi_info csi_info;
88
+ void *phy_hw[RKMODULE_MULTI_DEV_NUM];
6289 bool is_streaming;
63
- enum csi2_dphy_lane_mode lane_mode;
90
+ int lane_mode;
91
+ const struct dphy_drv_data *drv_data;
92
+ struct rkmodule_csi_dphy_param dphy_param;
6493 };
6594
6695 struct dphy_hw_drv_data {
67
- const struct clk_bulk_data *clks;
68
- int num_clks;
6996 const struct hsfreq_range *hsfreq_ranges;
7097 int num_hsfreq_ranges;
98
+ const struct hsfreq_range *hsfreq_ranges_cphy;
99
+ int num_hsfreq_ranges_cphy;
71100 const struct grf_reg *grf_regs;
72
- const struct txrx_reg *txrx_regs;
101
+ int num_grf_regs;
73102 const struct csi2dphy_reg *csi2dphy_regs;
103
+ int num_csi2dphy_regs;
74104 void (*individual_init)(struct csi2_dphy_hw *hw);
105
+ int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
106
+ int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
75107 enum csi2_dphy_chip_id chip_id;
76108 };
77109
78110 struct csi2_dphy_hw {
79111 struct device *dev;
80112 struct regmap *regmap_grf;
113
+ struct regmap *regmap_sys_grf;
81114 const struct grf_reg *grf_regs;
82
- const struct txrx_reg *txrx_regs;
83115 const struct csi2dphy_reg *csi2dphy_regs;
84116 const struct dphy_hw_drv_data *drv_data;
85117 void __iomem *hw_base_addr;
86
- struct clk_bulk_data *clks;
118
+ struct clk_bulk_data *clks_bulk;
119
+ struct reset_control *rsts_bulk;
87120 struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY];
88121 struct v4l2_subdev sd;
89122 struct mutex mutex; /* lock for updating protection */
....@@ -95,8 +128,13 @@
95128
96129 int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
97130 int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
131
+ int (*ttl_mode_enable)(struct csi2_dphy_hw *hw);
132
+ void (*ttl_mode_disable)(struct csi2_dphy_hw *hw);
133
+ int (*quick_stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
134
+ int (*quick_stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
98135 };
99136
100
-extern struct platform_driver rockchip_csi2_dphy_driver;
137
+int rockchip_csi2_dphy_hw_init(void);
138
+int rockchip_csi2_dphy_init(void);
101139
102140 #endif