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| 8 | 8 | #ifndef _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_ |
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| 9 | 9 | #define _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_ |
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| 10 | 10 | |
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| 11 | +#include <linux/rk-camera-module.h> |
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| 12 | +#include <linux/rkcif-config.h> |
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| 13 | + |
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| 14 | +#define PHY_MAX 16 |
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| 15 | +#define MAX_DEV_NAME_LEN 32 |
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| 16 | + |
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| 17 | +#define MAX_SAMSUNG_PHY_NUM 2 |
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| 18 | + |
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| 19 | +#define MAX_INNO_PHY_NUM 2 |
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| 20 | + |
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| 11 | 21 | /* add new chip id in tail by time order */ |
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| 12 | 22 | enum csi2_dphy_chip_id { |
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| 13 | 23 | CHIP_ID_RK3568 = 0x0, |
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| 24 | + CHIP_ID_RK3588 = 0x1, |
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| 25 | + CHIP_ID_RK3588_DCPHY = 0x2, |
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| 26 | + CHIP_ID_RV1106 = 0x3, |
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| 27 | + CHIP_ID_RK3562 = 0x4, |
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| 14 | 28 | }; |
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| 15 | 29 | |
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| 16 | 30 | enum csi2_dphy_rx_pads { |
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| .. | .. |
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| 46 | 60 | }; |
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| 47 | 61 | |
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| 48 | 62 | struct csi2_dphy_hw; |
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| 63 | +struct samsung_mipi_dcphy; |
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| 64 | + |
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| 65 | +struct dphy_drv_data { |
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| 66 | + const char dev_name[MAX_DEV_NAME_LEN]; |
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| 67 | + enum csi2_dphy_chip_id chip_id; |
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| 68 | + char num_inno_phy; |
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| 69 | + char num_samsung_phy; |
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| 70 | +}; |
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| 49 | 71 | |
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| 50 | 72 | struct csi2_dphy { |
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| 51 | 73 | struct device *dev; |
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| 52 | 74 | struct list_head list; |
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| 53 | 75 | struct csi2_dphy_hw *dphy_hw; |
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| 76 | + struct csi2_dphy_hw *dphy_hw_group[MAX_INNO_PHY_NUM]; |
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| 77 | + struct samsung_mipi_dcphy *samsung_phy; |
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| 78 | + struct samsung_mipi_dcphy *samsung_phy_group[MAX_SAMSUNG_PHY_NUM]; |
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| 54 | 79 | struct v4l2_async_notifier notifier; |
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| 55 | 80 | struct v4l2_subdev sd; |
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| 56 | 81 | struct mutex mutex; /* lock for updating protection */ |
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| .. | .. |
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| 59 | 84 | u64 data_rate_mbps; |
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| 60 | 85 | int num_sensors; |
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| 61 | 86 | int phy_index; |
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| 87 | + struct rkcif_csi_info csi_info; |
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| 88 | + void *phy_hw[RKMODULE_MULTI_DEV_NUM]; |
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| 62 | 89 | bool is_streaming; |
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| 63 | | - enum csi2_dphy_lane_mode lane_mode; |
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| 90 | + int lane_mode; |
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| 91 | + const struct dphy_drv_data *drv_data; |
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| 92 | + struct rkmodule_csi_dphy_param dphy_param; |
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| 64 | 93 | }; |
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| 65 | 94 | |
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| 66 | 95 | struct dphy_hw_drv_data { |
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| 67 | | - const struct clk_bulk_data *clks; |
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| 68 | | - int num_clks; |
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| 69 | 96 | const struct hsfreq_range *hsfreq_ranges; |
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| 70 | 97 | int num_hsfreq_ranges; |
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| 98 | + const struct hsfreq_range *hsfreq_ranges_cphy; |
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| 99 | + int num_hsfreq_ranges_cphy; |
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| 71 | 100 | const struct grf_reg *grf_regs; |
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| 72 | | - const struct txrx_reg *txrx_regs; |
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| 101 | + int num_grf_regs; |
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| 73 | 102 | const struct csi2dphy_reg *csi2dphy_regs; |
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| 103 | + int num_csi2dphy_regs; |
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| 74 | 104 | void (*individual_init)(struct csi2_dphy_hw *hw); |
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| 105 | + int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); |
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| 106 | + int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); |
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| 75 | 107 | enum csi2_dphy_chip_id chip_id; |
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| 76 | 108 | }; |
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| 77 | 109 | |
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| 78 | 110 | struct csi2_dphy_hw { |
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| 79 | 111 | struct device *dev; |
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| 80 | 112 | struct regmap *regmap_grf; |
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| 113 | + struct regmap *regmap_sys_grf; |
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| 81 | 114 | const struct grf_reg *grf_regs; |
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| 82 | | - const struct txrx_reg *txrx_regs; |
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| 83 | 115 | const struct csi2dphy_reg *csi2dphy_regs; |
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| 84 | 116 | const struct dphy_hw_drv_data *drv_data; |
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| 85 | 117 | void __iomem *hw_base_addr; |
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| 86 | | - struct clk_bulk_data *clks; |
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| 118 | + struct clk_bulk_data *clks_bulk; |
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| 119 | + struct reset_control *rsts_bulk; |
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| 87 | 120 | struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY]; |
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| 88 | 121 | struct v4l2_subdev sd; |
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| 89 | 122 | struct mutex mutex; /* lock for updating protection */ |
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| .. | .. |
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| 95 | 128 | |
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| 96 | 129 | int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); |
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| 97 | 130 | int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); |
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| 131 | + int (*ttl_mode_enable)(struct csi2_dphy_hw *hw); |
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| 132 | + void (*ttl_mode_disable)(struct csi2_dphy_hw *hw); |
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| 133 | + int (*quick_stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); |
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| 134 | + int (*quick_stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); |
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| 98 | 135 | }; |
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| 99 | 136 | |
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| 100 | | -extern struct platform_driver rockchip_csi2_dphy_driver; |
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| 137 | +int rockchip_csi2_dphy_hw_init(void); |
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| 138 | +int rockchip_csi2_dphy_init(void); |
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| 101 | 139 | |
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| 102 | 140 | #endif |
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