~hc/RK356X_SDK_RELEASE.git

..	..	@@ -20,9 +20,29 @@
20	20	#define PCIE_DMA_DATA_FREE_ACK_TABLE_OFFSET 0x10
21	21	#define PCIE_DMA_DATA_READ_REMOTE_TABLE_OFFSET 0x18
22	22
	23	+/* DMA linked list register filed */
	24	+#define PCIE_DWC_DMA_CB BIT(0)
	25	+#define PCIE_DWC_DMA_TCB BIT(1)
	26	+#define PCIE_DWC_DMA_LLP BIT(2)
	27	+#define PCIE_DWC_DMA_LIE BIT(3)
	28	+#define PCIE_DWC_DMA_RIE BIT(4)
	29	+#define PCIE_DWC_DMA_CCS BIT(8)
	30	+#define PCIE_DWC_DMA_LLE BIT(9)
	31	+
	32	+#define SET_LL_32(ll, value) \
	33	+ writel(value, ll)
	34	+
	35	+#define SET_LL_64(ll, value) \
	36	+ writeq(value, ll)
	37	+
23	38	enum dma_dir {
24	39	DMA_FROM_BUS,
25	40	DMA_TO_BUS,
	41	+};
	42	+
	43	+enum dma_mode {
	44	+ RK_PCIE_DMA_BLOCK,
	45	+ RK_PCIE_DMA_LL,
26	46	};
27	47
28	48	/**
..	..	@@ -155,7 +175,39 @@
155	175	phys_addr_t local;
156	176	phys_addr_t bus;
157	177	size_t buf_size;
	178	+ u32 dma_mode;
158	179	};
	180	+
	181	+struct rk_edma_lli {
	182	+ u32 control;
	183	+ u32 transfer_size;
	184	+ union {
	185	+ u64 reg;
	186	+ struct {
	187	+ u32 lsb;
	188	+ u32 msb;
	189	+ };
	190	+ } sar;
	191	+ union {
	192	+ u64 reg;
	193	+ struct {
	194	+ u32 lsb;
	195	+ u32 msb;
	196	+ };
	197	+ } dar;
	198	+} __packed;
	199	+
	200	+struct rk_edma_llp {
	201	+ u32 control;
	202	+ u32 reserved;
	203	+ union {
	204	+ u64 reg;
	205	+ struct {
	206	+ u32 lsb;
	207	+ u32 msb;
	208	+ };
	209	+ } llp;
	210	+} __packed;
159	211
160	212	struct dma_trx_obj {
161	213	struct device *dev;
..	..	@@ -190,7 +242,9 @@
190	242	struct pcie_misc_dev *pcie_dev;
191	243	void (start_dma_func)(struct dma_trx_obj obj, struct dma_table *table);
192	244	void (config_dma_func)(struct dma_table table);
	245	+ int (get_dma_status)(struct dma_trx_obj obj, u8 chn, enum dma_dir dir);
193	246	int (cb)(struct dma_trx_obj obj, u32 chn, enum dma_dir dir);
	247	+ void (dma_debug)(struct dma_trx_obj obj, struct dma_table *table);
194	248	ktime_t begin;
195	249	ktime_t end;
196	250	u64 cache_time_total;