| .. | .. |
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| 256 | 256 | return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1); |
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| 257 | 257 | } |
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| 258 | 258 | |
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| 259 | | -struct pci_ecam_ops xgene_v1_pcie_ecam_ops = { |
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| 259 | +const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = { |
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| 260 | 260 | .bus_shift = 16, |
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| 261 | 261 | .init = xgene_v1_pcie_ecam_init, |
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| 262 | 262 | .pci_ops = { |
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| .. | .. |
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| 271 | 271 | return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2); |
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| 272 | 272 | } |
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| 273 | 273 | |
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| 274 | | -struct pci_ecam_ops xgene_v2_pcie_ecam_ops = { |
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| 274 | +const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = { |
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| 275 | 275 | .bus_shift = 16, |
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| 276 | 276 | .init = xgene_v2_pcie_ecam_init, |
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| 277 | 277 | .pci_ops = { |
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| .. | .. |
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| 405 | 405 | xgene_pcie_writel(port, CFGCTL, EN_REG); |
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| 406 | 406 | } |
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| 407 | 407 | |
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| 408 | | -static int xgene_pcie_map_ranges(struct xgene_pcie_port *port, |
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| 409 | | - struct list_head *res, |
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| 410 | | - resource_size_t io_base) |
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| 408 | +static int xgene_pcie_map_ranges(struct xgene_pcie_port *port) |
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| 411 | 409 | { |
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| 410 | + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port); |
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| 412 | 411 | struct resource_entry *window; |
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| 413 | 412 | struct device *dev = port->dev; |
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| 414 | | - int ret; |
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| 415 | 413 | |
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| 416 | | - resource_list_for_each_entry(window, res) { |
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| 414 | + resource_list_for_each_entry(window, &bridge->windows) { |
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| 417 | 415 | struct resource *res = window->res; |
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| 418 | 416 | u64 restype = resource_type(res); |
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| 419 | 417 | |
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| .. | .. |
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| 421 | 419 | |
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| 422 | 420 | switch (restype) { |
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| 423 | 421 | case IORESOURCE_IO: |
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| 424 | | - xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base, |
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| 422 | + xgene_pcie_setup_ob_reg(port, res, OMR3BARL, |
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| 423 | + pci_pio_to_address(res->start), |
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| 425 | 424 | res->start - window->offset); |
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| 426 | | - ret = devm_pci_remap_iospace(dev, res, io_base); |
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| 427 | | - if (ret < 0) |
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| 428 | | - return ret; |
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| 429 | 425 | break; |
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| 430 | 426 | case IORESOURCE_MEM: |
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| 431 | 427 | if (res->flags & IORESOURCE_PREFETCH) |
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| .. | .. |
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| 567 | 563 | xgene_pcie_writel(port, i, 0); |
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| 568 | 564 | } |
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| 569 | 565 | |
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| 570 | | -static int xgene_pcie_setup(struct xgene_pcie_port *port, struct list_head *res, |
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| 571 | | - resource_size_t io_base) |
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| 566 | +static int xgene_pcie_setup(struct xgene_pcie_port *port) |
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| 572 | 567 | { |
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| 573 | 568 | struct device *dev = port->dev; |
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| 574 | 569 | u32 val, lanes = 0, speed = 0; |
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| .. | .. |
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| 580 | 575 | val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID; |
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| 581 | 576 | xgene_pcie_writel(port, BRIDGE_CFG_0, val); |
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| 582 | 577 | |
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| 583 | | - ret = xgene_pcie_map_ranges(port, res, io_base); |
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| 578 | + ret = xgene_pcie_map_ranges(port); |
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| 584 | 579 | if (ret) |
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| 585 | 580 | return ret; |
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| 586 | 581 | |
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| .. | .. |
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| 607 | 602 | struct device *dev = &pdev->dev; |
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| 608 | 603 | struct device_node *dn = dev->of_node; |
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| 609 | 604 | struct xgene_pcie_port *port; |
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| 610 | | - resource_size_t iobase = 0; |
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| 611 | | - struct pci_bus *bus, *child; |
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| 612 | 605 | struct pci_host_bridge *bridge; |
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| 613 | 606 | int ret; |
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| 614 | | - LIST_HEAD(res); |
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| 615 | 607 | |
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| 616 | 608 | bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port)); |
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| 617 | 609 | if (!bridge) |
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| .. | .. |
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| 634 | 626 | if (ret) |
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| 635 | 627 | return ret; |
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| 636 | 628 | |
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| 637 | | - ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res, |
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| 638 | | - &iobase); |
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| 629 | + ret = xgene_pcie_setup(port); |
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| 639 | 630 | if (ret) |
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| 640 | 631 | return ret; |
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| 641 | 632 | |
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| 642 | | - ret = devm_request_pci_bus_resources(dev, &res); |
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| 643 | | - if (ret) |
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| 644 | | - goto error; |
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| 645 | | - |
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| 646 | | - ret = xgene_pcie_setup(port, &res, iobase); |
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| 647 | | - if (ret) |
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| 648 | | - goto error; |
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| 649 | | - |
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| 650 | | - list_splice_init(&res, &bridge->windows); |
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| 651 | | - bridge->dev.parent = dev; |
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| 652 | 633 | bridge->sysdata = port; |
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| 653 | | - bridge->busnr = 0; |
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| 654 | 634 | bridge->ops = &xgene_pcie_ops; |
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| 655 | | - bridge->map_irq = of_irq_parse_and_map_pci; |
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| 656 | | - bridge->swizzle_irq = pci_common_swizzle; |
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| 657 | 635 | |
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| 658 | | - ret = pci_scan_root_bus_bridge(bridge); |
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| 659 | | - if (ret < 0) |
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| 660 | | - goto error; |
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| 661 | | - |
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| 662 | | - bus = bridge->bus; |
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| 663 | | - |
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| 664 | | - pci_assign_unassigned_bus_resources(bus); |
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| 665 | | - list_for_each_entry(child, &bus->children, node) |
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| 666 | | - pcie_bus_configure_settings(child); |
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| 667 | | - pci_bus_add_devices(bus); |
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| 668 | | - return 0; |
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| 669 | | - |
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| 670 | | -error: |
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| 671 | | - pci_free_resource_list(&res); |
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| 672 | | - return ret; |
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| 636 | + return pci_host_probe(bridge); |
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| 673 | 637 | } |
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| 674 | 638 | |
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| 675 | 639 | static const struct of_device_id xgene_pcie_match_table[] = { |
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