forked from ~ljy/RK356X_SDK_RELEASE
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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/pci/controller/pci-mvebu.c
....@@ -12,7 +12,6 @@
1212 #include <linux/gpio.h>
1313 #include <linux/init.h>
1414 #include <linux/mbus.h>
15
-#include <linux/msi.h>
1615 #include <linux/slab.h>
1716 #include <linux/platform_device.h>
1817 #include <linux/of_address.h>
....@@ -22,6 +21,7 @@
2221 #include <linux/of_platform.h>
2322 
2423 #include "../pci.h"
24
+#include "../pci-bridge-emul.h"
2525 
2626 /*
2727  * PCIe unit register offsets.
....@@ -63,69 +63,12 @@
6363 #define PCIE_DEBUG_CTRL         0x1a60
6464 #define  PCIE_DEBUG_SOFT_RESET		BIT(20)
6565 
66
-enum {
67
-	PCISWCAP = PCI_BRIDGE_CONTROL + 2,
68
-	PCISWCAP_EXP_LIST_ID	= PCISWCAP + PCI_CAP_LIST_ID,
69
-	PCISWCAP_EXP_DEVCAP	= PCISWCAP + PCI_EXP_DEVCAP,
70
-	PCISWCAP_EXP_DEVCTL	= PCISWCAP + PCI_EXP_DEVCTL,
71
-	PCISWCAP_EXP_LNKCAP	= PCISWCAP + PCI_EXP_LNKCAP,
72
-	PCISWCAP_EXP_LNKCTL	= PCISWCAP + PCI_EXP_LNKCTL,
73
-	PCISWCAP_EXP_SLTCAP	= PCISWCAP + PCI_EXP_SLTCAP,
74
-	PCISWCAP_EXP_SLTCTL	= PCISWCAP + PCI_EXP_SLTCTL,
75
-	PCISWCAP_EXP_RTCTL	= PCISWCAP + PCI_EXP_RTCTL,
76
-	PCISWCAP_EXP_RTSTA	= PCISWCAP + PCI_EXP_RTSTA,
77
-	PCISWCAP_EXP_DEVCAP2	= PCISWCAP + PCI_EXP_DEVCAP2,
78
-	PCISWCAP_EXP_DEVCTL2	= PCISWCAP + PCI_EXP_DEVCTL2,
79
-	PCISWCAP_EXP_LNKCAP2	= PCISWCAP + PCI_EXP_LNKCAP2,
80
-	PCISWCAP_EXP_LNKCTL2	= PCISWCAP + PCI_EXP_LNKCTL2,
81
-	PCISWCAP_EXP_SLTCAP2	= PCISWCAP + PCI_EXP_SLTCAP2,
82
-	PCISWCAP_EXP_SLTCTL2	= PCISWCAP + PCI_EXP_SLTCTL2,
83
-};
84
-
85
-/* PCI configuration space of a PCI-to-PCI bridge */
86
-struct mvebu_sw_pci_bridge {
87
-	u16 vendor;
88
-	u16 device;
89
-	u16 command;
90
-	u16 status;
91
-	u16 class;
92
-	u8 interface;
93
-	u8 revision;
94
-	u8 bist;
95
-	u8 header_type;
96
-	u8 latency_timer;
97
-	u8 cache_line_size;
98
-	u32 bar[2];
99
-	u8 primary_bus;
100
-	u8 secondary_bus;
101
-	u8 subordinate_bus;
102
-	u8 secondary_latency_timer;
103
-	u8 iobase;
104
-	u8 iolimit;
105
-	u16 secondary_status;
106
-	u16 membase;
107
-	u16 memlimit;
108
-	u16 iobaseupper;
109
-	u16 iolimitupper;
110
-	u32 romaddr;
111
-	u8 intline;
112
-	u8 intpin;
113
-	u16 bridgectrl;
114
-
115
-	/* PCI express capability */
116
-	u32 pcie_sltcap;
117
-	u16 pcie_devctl;
118
-	u16 pcie_rtctl;
119
-};
120
-
12166 struct mvebu_pcie_port;
12267 
12368 /* Structure representing all PCIe interfaces */
12469 struct mvebu_pcie {
12570 	struct platform_device *pdev;
12671 	struct mvebu_pcie_port *ports;
127
-	struct msi_controller *msi;
128
-	struct list_head resources;
12972 	struct resource io;
13073 	struct resource realio;
13174 	struct resource mem;
....@@ -153,12 +96,13 @@
15396 	struct clk *clk;
15497 	struct gpio_desc *reset_gpio;
15598 	char *reset_name;
156
-	struct mvebu_sw_pci_bridge bridge;
99
+	struct pci_bridge_emul bridge;
157100 	struct device_node *dn;
158101 	struct mvebu_pcie *pcie;
159102 	struct mvebu_pcie_window memwin;
160103 	struct mvebu_pcie_window iowin;
161104 	u32 saved_pcie_stat;
105
+	struct resource regs;
162106 };
163107 
164108 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
....@@ -203,7 +147,9 @@
203147 
204148 /*
205149  * Setup PCIE BARs and Address Decode Wins:
206
- * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
150
+ * BAR[0] -> internal registers (needed for MSI)
151
+ * BAR[1] -> covers all DRAM banks
152
+ * BAR[2] -> Disabled
207153  * WIN[0-3] -> DRAM bank[0-3]
208154  */
209155 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
....@@ -257,6 +203,12 @@
257203 	mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
258204 	mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
259205 		     PCIE_BAR_CTRL_OFF(1));
206
+
207
+	/*
208
+	 * Point BAR[0] to the device's internal registers.
209
+	 */
210
+	mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0));
211
+	mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
260212 }
261213 
262214 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
....@@ -415,11 +367,12 @@
415367 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
416368 {
417369 	struct mvebu_pcie_window desired = {};
370
+	struct pci_bridge_emul_conf *conf = &port->bridge.conf;
418371 
419372 	/* Are the new iobase/iolimit values invalid? */
420
-	if (port->bridge.iolimit < port->bridge.iobase ||
421
-	    port->bridge.iolimitupper < port->bridge.iobaseupper ||
422
-	    !(port->bridge.command & PCI_COMMAND_IO)) {
373
+	if (conf->iolimit < conf->iobase ||
374
+	    conf->iolimitupper < conf->iobaseupper ||
375
+	    !(conf->command & PCI_COMMAND_IO)) {
423376 		mvebu_pcie_set_window(port, port->io_target, port->io_attr,
424377 				      &desired, &port->iowin);
425378 		return;
....@@ -438,11 +391,11 @@
438391 	 * specifications. iobase is the bus address, port->iowin_base
439392 	 * is the CPU address.
440393 	 */
441
-	desired.remap = ((port->bridge.iobase & 0xF0) << 8) |
442
-			(port->bridge.iobaseupper << 16);
394
+	desired.remap = ((conf->iobase & 0xF0) << 8) |
395
+			(conf->iobaseupper << 16);
443396 	desired.base = port->pcie->io.start + desired.remap;
444
-	desired.size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
445
-			 (port->bridge.iolimitupper << 16)) -
397
+	desired.size = ((0xFFF | ((conf->iolimit & 0xF0) << 8) |
398
+			 (conf->iolimitupper << 16)) -
446399 			desired.remap) +
447400 		       1;
448401 
....@@ -453,10 +406,11 @@
453406 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
454407 {
455408 	struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP};
409
+	struct pci_bridge_emul_conf *conf = &port->bridge.conf;
456410 
457411 	/* Are the new membase/memlimit values invalid? */
458
-	if (port->bridge.memlimit < port->bridge.membase ||
459
-	    !(port->bridge.command & PCI_COMMAND_MEMORY)) {
412
+	if (conf->memlimit < conf->membase ||
413
+	    !(conf->command & PCI_COMMAND_MEMORY)) {
460414 		mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
461415 				      &desired, &port->memwin);
462416 		return;
....@@ -468,130 +422,32 @@
468422 	 * window to setup, according to the PCI-to-PCI bridge
469423 	 * specifications.
470424 	 */
471
-	desired.base = ((port->bridge.membase & 0xFFF0) << 16);
472
-	desired.size = (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
425
+	desired.base = ((conf->membase & 0xFFF0) << 16);
426
+	desired.size = (((conf->memlimit & 0xFFF0) << 16) | 0xFFFFF) -
473427 		       desired.base + 1;
474428 
475429 	mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
476430 			      &port->memwin);
477431 }
478432 
479
-/*
480
- * Initialize the configuration space of the PCI-to-PCI bridge
481
- * associated with the given PCIe interface.
482
- */
483
-static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
433
+static pci_bridge_emul_read_status_t
434
+mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
435
+				     int reg, u32 *value)
484436 {
485
-	struct mvebu_sw_pci_bridge *bridge = &port->bridge;
437
+	struct mvebu_pcie_port *port = bridge->data;
486438 
487
-	memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
488
-
489
-	bridge->class = PCI_CLASS_BRIDGE_PCI;
490
-	bridge->vendor = PCI_VENDOR_ID_MARVELL;
491
-	bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
492
-	bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
493
-	bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
494
-	bridge->cache_line_size = 0x10;
495
-
496
-	/* We support 32 bits I/O addressing */
497
-	bridge->iobase = PCI_IO_RANGE_TYPE_32;
498
-	bridge->iolimit = PCI_IO_RANGE_TYPE_32;
499
-
500
-	/* Add capabilities */
501
-	bridge->status = PCI_STATUS_CAP_LIST;
502
-}
503
-
504
-/*
505
- * Read the configuration space of the PCI-to-PCI bridge associated to
506
- * the given PCIe interface.
507
- */
508
-static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
509
-				  unsigned int where, int size, u32 *value)
510
-{
511
-	struct mvebu_sw_pci_bridge *bridge = &port->bridge;
512
-
513
-	switch (where & ~3) {
514
-	case PCI_VENDOR_ID:
515
-		*value = bridge->device << 16 | bridge->vendor;
516
-		break;
517
-
518
-	case PCI_COMMAND:
519
-		*value = bridge->command | bridge->status << 16;
520
-		break;
521
-
522
-	case PCI_CLASS_REVISION:
523
-		*value = bridge->class << 16 | bridge->interface << 8 |
524
-			 bridge->revision;
525
-		break;
526
-
527
-	case PCI_CACHE_LINE_SIZE:
528
-		*value = bridge->bist << 24 | bridge->header_type << 16 |
529
-			 bridge->latency_timer << 8 | bridge->cache_line_size;
530
-		break;
531
-
532
-	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
533
-		*value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
534
-		break;
535
-
536
-	case PCI_PRIMARY_BUS:
537
-		*value = (bridge->secondary_latency_timer << 24 |
538
-			  bridge->subordinate_bus         << 16 |
539
-			  bridge->secondary_bus           <<  8 |
540
-			  bridge->primary_bus);
541
-		break;
542
-
543
-	case PCI_IO_BASE:
544
-		if (!mvebu_has_ioport(port))
545
-			*value = bridge->secondary_status << 16;
546
-		else
547
-			*value = (bridge->secondary_status << 16 |
548
-				  bridge->iolimit          <<  8 |
549
-				  bridge->iobase);
550
-		break;
551
-
552
-	case PCI_MEMORY_BASE:
553
-		*value = (bridge->memlimit << 16 | bridge->membase);
554
-		break;
555
-
556
-	case PCI_PREF_MEMORY_BASE:
557
-		*value = 0;
558
-		break;
559
-
560
-	case PCI_IO_BASE_UPPER16:
561
-		*value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
562
-		break;
563
-
564
-	case PCI_CAPABILITY_LIST:
565
-		*value = PCISWCAP;
566
-		break;
567
-
568
-	case PCI_ROM_ADDRESS1:
569
-		*value = 0;
570
-		break;
571
-
572
-	case PCI_INTERRUPT_LINE:
573
-		/* LINE PIN MIN_GNT MAX_LAT */
574
-		*value = 0;
575
-		break;
576
-
577
-	case PCISWCAP_EXP_LIST_ID:
578
-		/* Set PCIe v2, root port, slot support */
579
-		*value = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
580
-			  PCI_EXP_FLAGS_SLOT) << 16 | PCI_CAP_ID_EXP;
581
-		break;
582
-
583
-	case PCISWCAP_EXP_DEVCAP:
439
+	switch (reg) {
440
+	case PCI_EXP_DEVCAP:
584441 		*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
585442 		break;
586443 
587
-	case PCISWCAP_EXP_DEVCTL:
444
+	case PCI_EXP_DEVCTL:
588445 		*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) &
589446 				 ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
590447 				   PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
591
-		*value |= bridge->pcie_devctl;
592448 		break;
593449 
594
-	case PCISWCAP_EXP_LNKCAP:
450
+	case PCI_EXP_LNKCAP:
595451 		/*
596452 		 * PCIe requires the clock power management capability to be
597453 		 * hard-wired to zero for downstream ports
....@@ -600,176 +456,148 @@
600456 			 ~PCI_EXP_LNKCAP_CLKPM;
601457 		break;
602458 
603
-	case PCISWCAP_EXP_LNKCTL:
459
+	case PCI_EXP_LNKCTL:
604460 		*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
605461 		break;
606462 
607
-	case PCISWCAP_EXP_SLTCAP:
608
-		*value = bridge->pcie_sltcap;
609
-		break;
610
-
611
-	case PCISWCAP_EXP_SLTCTL:
463
+	case PCI_EXP_SLTCTL:
612464 		*value = PCI_EXP_SLTSTA_PDS << 16;
613465 		break;
614466 
615
-	case PCISWCAP_EXP_RTCTL:
616
-		*value = bridge->pcie_rtctl;
617
-		break;
618
-
619
-	case PCISWCAP_EXP_RTSTA:
467
+	case PCI_EXP_RTSTA:
620468 		*value = mvebu_readl(port, PCIE_RC_RTSTA);
621469 		break;
622470 
623
-	/* PCIe requires the v2 fields to be hard-wired to zero */
624
-	case PCISWCAP_EXP_DEVCAP2:
625
-	case PCISWCAP_EXP_DEVCTL2:
626
-	case PCISWCAP_EXP_LNKCAP2:
627
-	case PCISWCAP_EXP_LNKCTL2:
628
-	case PCISWCAP_EXP_SLTCAP2:
629
-	case PCISWCAP_EXP_SLTCTL2:
630471 	default:
631
-		/*
632
-		 * PCI defines configuration read accesses to reserved or
633
-		 * unimplemented registers to read as zero and complete
634
-		 * normally.
635
-		 */
636
-		*value = 0;
637
-		return PCIBIOS_SUCCESSFUL;
472
+		return PCI_BRIDGE_EMUL_NOT_HANDLED;
638473 	}
639474 
640
-	if (size == 2)
641
-		*value = (*value >> (8 * (where & 3))) & 0xffff;
642
-	else if (size == 1)
643
-		*value = (*value >> (8 * (where & 3))) & 0xff;
644
-
645
-	return PCIBIOS_SUCCESSFUL;
475
+	return PCI_BRIDGE_EMUL_HANDLED;
646476 }
647477 
648
-/* Write to the PCI-to-PCI bridge configuration space */
649
-static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
650
-				     unsigned int where, int size, u32 value)
478
+static void
479
+mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
480
+				      int reg, u32 old, u32 new, u32 mask)
651481 {
652
-	struct mvebu_sw_pci_bridge *bridge = &port->bridge;
653
-	u32 mask, reg;
654
-	int err;
482
+	struct mvebu_pcie_port *port = bridge->data;
483
+	struct pci_bridge_emul_conf *conf = &bridge->conf;
655484 
656
-	if (size == 4)
657
-		mask = 0x0;
658
-	else if (size == 2)
659
-		mask = ~(0xffff << ((where & 3) * 8));
660
-	else if (size == 1)
661
-		mask = ~(0xff << ((where & 3) * 8));
662
-	else
663
-		return PCIBIOS_BAD_REGISTER_NUMBER;
664
-
665
-	err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
666
-	if (err)
667
-		return err;
668
-
669
-	value = (reg & mask) | value << ((where & 3) * 8);
670
-
671
-	switch (where & ~3) {
485
+	switch (reg) {
672486 	case PCI_COMMAND:
673487 	{
674
-		u32 old = bridge->command;
675
-
676488 		if (!mvebu_has_ioport(port))
677
-			value &= ~PCI_COMMAND_IO;
489
+			conf->command &= ~PCI_COMMAND_IO;
678490 
679
-		bridge->command = value & 0xffff;
680
-		if ((old ^ bridge->command) & PCI_COMMAND_IO)
491
+		if ((old ^ new) & PCI_COMMAND_IO)
681492 			mvebu_pcie_handle_iobase_change(port);
682
-		if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
493
+		if ((old ^ new) & PCI_COMMAND_MEMORY)
683494 			mvebu_pcie_handle_membase_change(port);
495
+
684496 		break;
685497 	}
686
-
687
-	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
688
-		bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
689
-		break;
690498 
691499 	case PCI_IO_BASE:
692500 		/*
693
-		 * We also keep bit 1 set, it is a read-only bit that
501
+		 * We keep bit 1 set, it is a read-only bit that
694502 		 * indicates we support 32 bits addressing for the
695503 		 * I/O
696504 		 */
697
-		bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
698
-		bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
505
+		conf->iobase |= PCI_IO_RANGE_TYPE_32;
506
+		conf->iolimit |= PCI_IO_RANGE_TYPE_32;
699507 		mvebu_pcie_handle_iobase_change(port);
700508 		break;
701509 
702510 	case PCI_MEMORY_BASE:
703
-		bridge->membase = value & 0xffff;
704
-		bridge->memlimit = value >> 16;
705511 		mvebu_pcie_handle_membase_change(port);
706512 		break;
707513 
708514 	case PCI_IO_BASE_UPPER16:
709
-		bridge->iobaseupper = value & 0xffff;
710
-		bridge->iolimitupper = value >> 16;
711515 		mvebu_pcie_handle_iobase_change(port);
712516 		break;
713517 
714518 	case PCI_PRIMARY_BUS:
715
-		bridge->primary_bus             = value & 0xff;
716
-		bridge->secondary_bus           = (value >> 8) & 0xff;
717
-		bridge->subordinate_bus         = (value >> 16) & 0xff;
718
-		bridge->secondary_latency_timer = (value >> 24) & 0xff;
719
-		mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
519
+		mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
720520 		break;
721521 
722
-	case PCISWCAP_EXP_DEVCTL:
522
+	default:
523
+		break;
524
+	}
525
+}
526
+
527
+static void
528
+mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
529
+				      int reg, u32 old, u32 new, u32 mask)
530
+{
531
+	struct mvebu_pcie_port *port = bridge->data;
532
+
533
+	switch (reg) {
534
+	case PCI_EXP_DEVCTL:
723535 		/*
724536 		 * Armada370 data says these bits must always
725537 		 * be zero when in root complex mode.
726538 		 */
727
-		value &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
728
-			   PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
539
+		new &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
540
+			 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
729541 
730
-		/*
731
-		 * If the mask is 0xffff0000, then we only want to write
732
-		 * the device control register, rather than clearing the
733
-		 * RW1C bits in the device status register.  Mask out the
734
-		 * status register bits.
735
-		 */
736
-		if (mask == 0xffff0000)
737
-			value &= 0xffff;
738
-
739
-		mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
542
+		mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
740543 		break;
741544 
742
-	case PCISWCAP_EXP_LNKCTL:
545
+	case PCI_EXP_LNKCTL:
743546 		/*
744547 		 * If we don't support CLKREQ, we must ensure that the
745548 		 * CLKREQ enable bit always reads zero.  Since we haven't
746549 		 * had this capability, and it's dependent on board wiring,
747550 		 * disable it for the time being.
748551 		 */
749
-		value &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
552
+		new &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
750553 
751
-		/*
752
-		 * If the mask is 0xffff0000, then we only want to write
753
-		 * the link control register, rather than clearing the
754
-		 * RW1C bits in the link status register.  Mask out the
755
-		 * RW1C status register bits.
756
-		 */
757
-		if (mask == 0xffff0000)
758
-			value &= ~((PCI_EXP_LNKSTA_LABS |
759
-				    PCI_EXP_LNKSTA_LBMS) << 16);
760
-
761
-		mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
554
+		mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
762555 		break;
763556 
764
-	case PCISWCAP_EXP_RTSTA:
765
-		mvebu_writel(port, value, PCIE_RC_RTSTA);
766
-		break;
767
-
768
-	default:
557
+	case PCI_EXP_RTSTA:
558
+		mvebu_writel(port, new, PCIE_RC_RTSTA);
769559 		break;
770560 	}
561
+}
771562 
772
-	return PCIBIOS_SUCCESSFUL;
563
+static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
564
+	.write_base = mvebu_pci_bridge_emul_base_conf_write,
565
+	.read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
566
+	.write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
567
+};
568
+
569
+/*
570
+ * Initialize the configuration space of the PCI-to-PCI bridge
571
+ * associated with the given PCIe interface.
572
+ */
573
+static void mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
574
+{
575
+	struct pci_bridge_emul *bridge = &port->bridge;
576
+	u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP);
577
+	u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS);
578
+
579
+	bridge->conf.vendor = PCI_VENDOR_ID_MARVELL;
580
+	bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
581
+	bridge->conf.class_revision =
582
+		mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
583
+
584
+	if (mvebu_has_ioport(port)) {
585
+		/* We support 32 bits I/O addressing */
586
+		bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
587
+		bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
588
+	}
589
+
590
+	/*
591
+	 * Older mvebu hardware provides PCIe Capability structure only in
592
+	 * version 1. New hardware provides it in version 2.
593
+	 */
594
+	bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver);
595
+
596
+	bridge->has_pcie = true;
597
+	bridge->data = port;
598
+	bridge->ops = &mvebu_pci_bridge_emul_ops;
599
+
600
+	pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR);
773601 }
774602 
775603 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
....@@ -789,8 +617,8 @@
789617 		if (bus->number == 0 && port->devfn == devfn)
790618 			return port;
791619 		if (bus->number != 0 &&
792
-		    bus->number >= port->bridge.secondary_bus &&
793
-		    bus->number <= port->bridge.subordinate_bus)
620
+		    bus->number >= port->bridge.conf.secondary_bus &&
621
+		    bus->number <= port->bridge.conf.subordinate_bus)
794622 			return port;
795623 	}
796624 
....@@ -811,7 +639,8 @@
811639 
812640 	/* Access the emulated PCI-to-PCI bridge */
813641 	if (bus->number == 0)
814
-		return mvebu_sw_pci_bridge_write(port, where, size, val);
642
+		return pci_bridge_emul_conf_write(&port->bridge, where,
643
+						  size, val);
815644 
816645 	if (!mvebu_pcie_link_up(port))
817646 		return PCIBIOS_DEVICE_NOT_FOUND;
....@@ -839,7 +668,8 @@
839668 
840669 	/* Access the emulated PCI-to-PCI bridge */
841670 	if (bus->number == 0)
842
-		return mvebu_sw_pci_bridge_read(port, where, size, val);
671
+		return pci_bridge_emul_conf_read(&port->bridge, where,
672
+						 size, val);
843673 
844674 	if (!mvebu_pcie_link_up(port)) {
845675 		*val = 0xffffffff;
....@@ -892,14 +722,13 @@
892722 					      struct device_node *np,
893723 					      struct mvebu_pcie_port *port)
894724 {
895
-	struct resource regs;
896725 	int ret = 0;
897726 
898
-	ret = of_address_to_resource(np, 0, &regs);
727
+	ret = of_address_to_resource(np, 0, &port->regs);
899728 	if (ret)
900
-		return ERR_PTR(ret);
729
+		return (void __iomem *)ERR_PTR(ret);
901730 
902
-	return devm_ioremap_resource(&pdev->dev, &regs);
731
+	return devm_ioremap_resource(&pdev->dev, &port->regs);
903732 }
904733 
905734 #define DT_FLAGS_TO_TYPE(flags)       (((flags) >> 24) & 0x03)
....@@ -1137,25 +966,15 @@
1137966 }
1138967 
1139968 /*
1140
- * We can't use devm_of_pci_get_host_bridge_resources() because we
1141
- * need to parse our special DT properties encoding the MEM and IO
1142
- * apertures.
969
+ * devm_of_pci_get_host_bridge_resources() only sets up translateable resources,
970
+ * so we need extra resource setup parsing our special DT properties encoding
971
+ * the MEM and IO apertures.
1143972  */
1144973 static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
1145974 {
1146975 	struct device *dev = &pcie->pdev->dev;
1147
-	struct device_node *np = dev->of_node;
976
+	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1148977 	int ret;
1149
-
1150
-	INIT_LIST_HEAD(&pcie->resources);
1151
-
1152
-	/* Get the bus range */
1153
-	ret = of_pci_parse_bus_range(np, &pcie->busn);
1154
-	if (ret) {
1155
-		dev_err(dev, "failed to parse bus-range property: %d\n", ret);
1156
-		return ret;
1157
-	}
1158
-	pci_add_resource(&pcie->resources, &pcie->busn);
1159978 
1160979 	/* Get the PCIe memory aperture */
1161980 	mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
....@@ -1165,7 +984,10 @@
1165984 	}
1166985 
1167986 	pcie->mem.name = "PCI MEM";
1168
-	pci_add_resource(&pcie->resources, &pcie->mem);
987
+	pci_add_resource(&bridge->windows, &pcie->mem);
988
+	ret = devm_request_resource(dev, &iomem_resource, &pcie->mem);
989
+	if (ret)
990
+		return ret;
1169991 
1170992 	/* Get the PCIe IO aperture */
1171993 	mvebu_mbus_get_pcie_io_aperture(&pcie->io);
....@@ -1178,10 +1000,13 @@
11781000 					 resource_size(&pcie->io) - 1);
11791001 		pcie->realio.name = "PCI I/O";
11801002 
1181
-		pci_add_resource(&pcie->resources, &pcie->realio);
1003
+		pci_add_resource(&bridge->windows, &pcie->realio);
1004
+		ret = devm_request_resource(dev, &ioport_resource, &pcie->realio);
1005
+		if (ret)
1006
+			return ret;
11821007 	}
11831008 
1184
-	return devm_request_pci_bus_resources(dev, &pcie->resources);
1009
+	return 0;
11851010 }
11861011 
11871012 /*
....@@ -1297,20 +1122,14 @@
12971122 
12981123 		mvebu_pcie_setup_hw(port);
12991124 		mvebu_pcie_set_local_dev_nr(port, 1);
1300
-		mvebu_sw_pci_bridge_init(port);
1125
+		mvebu_pci_bridge_emul_init(port);
13011126 	}
13021127 
13031128 	pcie->nports = i;
13041129 
1305
-	list_splice_init(&pcie->resources, &bridge->windows);
1306
-	bridge->dev.parent = dev;
13071130 	bridge->sysdata = pcie;
1308
-	bridge->busnr = 0;
13091131 	bridge->ops = &mvebu_pcie_ops;
1310
-	bridge->map_irq = of_irq_parse_and_map_pci;
1311
-	bridge->swizzle_irq = pci_common_swizzle;
13121132 	bridge->align_resource = mvebu_pcie_align_resource;
1313
-	bridge->msi = pcie->msi;
13141133 
13151134 	return mvebu_pci_host_probe(bridge);
13161135 }