| .. | .. |
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| 140 | 140 | #define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1) |
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| 141 | 141 | #define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2) |
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| 142 | 142 | #define NTB_HWERR_MSIX_VECTOR32_BAD BIT_ULL(3) |
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| 143 | +#define NTB_HWERR_BAR_ALIGN BIT_ULL(4) |
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| 143 | 144 | |
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| 144 | 145 | extern struct intel_b2b_addr xeon_b2b_usd_addr; |
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| 145 | 146 | extern struct intel_b2b_addr xeon_b2b_dsd_addr; |
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| .. | .. |
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| 147 | 148 | int ndev_init_isr(struct intel_ntb_dev *ndev, int msix_min, int msix_max, |
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| 148 | 149 | int msix_shift, int total_shift); |
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| 149 | 150 | enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd); |
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| 151 | +void ndev_db_addr(struct intel_ntb_dev *ndev, |
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| 152 | + phys_addr_t *db_addr, resource_size_t *db_size, |
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| 153 | + phys_addr_t reg_addr, unsigned long reg); |
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| 150 | 154 | u64 ndev_db_read(struct intel_ntb_dev *ndev, void __iomem *mmio); |
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| 151 | 155 | int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits, |
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| 152 | 156 | void __iomem *mmio); |
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| .. | .. |
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| 166 | 170 | u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector); |
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| 167 | 171 | int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits); |
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| 168 | 172 | int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits); |
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| 169 | | -int intel_ntb_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr, |
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| 170 | | - resource_size_t *db_size); |
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| 171 | 173 | int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb); |
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| 172 | 174 | int intel_ntb_spad_count(struct ntb_dev *ntb); |
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| 173 | 175 | u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx); |
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