~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,10 +1,10 @@
1	1	/*
2		- * Marvell Wireless LAN device driver: PCIE specific handling
	2	+ * NXP Wireless LAN device driver: PCIE specific handling
3	3	*
4		- * Copyright (C) 2011-2014, Marvell International Ltd.
	4	+ * Copyright 2011-2020 NXP
5	5	*
6		- * This software file (the "File") is distributed by Marvell International
7		- * Ltd. under the terms of the GNU General Public License Version 2, June 1991
	6	+ * This software file (the "File") is distributed by NXP
	7	+ * under the terms of the GNU General Public License Version 2, June 1991
8	8	* (the "License"). You may use, redistribute and/or modify this File in
9	9	* accordance with the terms and conditions of the License, a copy of which
10	10	* is available by writing to the Free Software Foundation, Inc.,
..	..	@@ -17,6 +17,7 @@
17	17	* this warranty disclaimer.
18	18	*/
19	19
	20	+#include <linux/iopoll.h>
20	21	#include <linux/firmware.h>
21	22
22	23	#include "decl.h"
..	..	@@ -33,7 +34,156 @@
33	34
34	35	static struct mwifiex_if_ops pcie_ops;
35	36
36		-static const struct of_device_id mwifiex_pcie_of_match_table[] = {
	37	+static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
	38	+ .cmd_addr_lo = PCIE_SCRATCH_0_REG,
	39	+ .cmd_addr_hi = PCIE_SCRATCH_1_REG,
	40	+ .cmd_size = PCIE_SCRATCH_2_REG,
	41	+ .fw_status = PCIE_SCRATCH_3_REG,
	42	+ .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	43	+ .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	44	+ .tx_rdptr = PCIE_SCRATCH_6_REG,
	45	+ .tx_wrptr = PCIE_SCRATCH_7_REG,
	46	+ .rx_rdptr = PCIE_SCRATCH_8_REG,
	47	+ .rx_wrptr = PCIE_SCRATCH_9_REG,
	48	+ .evt_rdptr = PCIE_SCRATCH_10_REG,
	49	+ .evt_wrptr = PCIE_SCRATCH_11_REG,
	50	+ .drv_rdy = PCIE_SCRATCH_12_REG,
	51	+ .tx_start_ptr = 0,
	52	+ .tx_mask = MWIFIEX_TXBD_MASK,
	53	+ .tx_wrap_mask = 0,
	54	+ .rx_mask = MWIFIEX_RXBD_MASK,
	55	+ .rx_wrap_mask = 0,
	56	+ .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	57	+ .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	58	+ .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	59	+ .ring_flag_sop = 0,
	60	+ .ring_flag_eop = 0,
	61	+ .ring_flag_xs_sop = 0,
	62	+ .ring_flag_xs_eop = 0,
	63	+ .ring_tx_start_ptr = 0,
	64	+ .pfu_enabled = 0,
	65	+ .sleep_cookie = 1,
	66	+ .msix_support = 0,
	67	+};
	68	+
	69	+static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
	70	+ .cmd_addr_lo = PCIE_SCRATCH_0_REG,
	71	+ .cmd_addr_hi = PCIE_SCRATCH_1_REG,
	72	+ .cmd_size = PCIE_SCRATCH_2_REG,
	73	+ .fw_status = PCIE_SCRATCH_3_REG,
	74	+ .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	75	+ .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	76	+ .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
	77	+ .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
	78	+ .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
	79	+ .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
	80	+ .evt_rdptr = PCIE_SCRATCH_10_REG,
	81	+ .evt_wrptr = PCIE_SCRATCH_11_REG,
	82	+ .drv_rdy = PCIE_SCRATCH_12_REG,
	83	+ .tx_start_ptr = 16,
	84	+ .tx_mask = 0x03FF0000,
	85	+ .tx_wrap_mask = 0x07FF0000,
	86	+ .rx_mask = 0x000003FF,
	87	+ .rx_wrap_mask = 0x000007FF,
	88	+ .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
	89	+ .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
	90	+ .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	91	+ .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	92	+ .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	93	+ .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	94	+ .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	95	+ .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	96	+ .pfu_enabled = 1,
	97	+ .sleep_cookie = 0,
	98	+ .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
	99	+ .fw_dump_start = PCIE_SCRATCH_14_REG,
	100	+ .fw_dump_end = 0xcff,
	101	+ .fw_dump_host_ready = 0xee,
	102	+ .fw_dump_read_done = 0xfe,
	103	+ .msix_support = 0,
	104	+};
	105	+
	106	+static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
	107	+ .cmd_addr_lo = PCIE_SCRATCH_0_REG,
	108	+ .cmd_addr_hi = PCIE_SCRATCH_1_REG,
	109	+ .cmd_size = PCIE_SCRATCH_2_REG,
	110	+ .fw_status = PCIE_SCRATCH_3_REG,
	111	+ .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	112	+ .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	113	+ .tx_rdptr = 0xC1A4,
	114	+ .tx_wrptr = 0xC174,
	115	+ .rx_rdptr = 0xC174,
	116	+ .rx_wrptr = 0xC1A4,
	117	+ .evt_rdptr = PCIE_SCRATCH_10_REG,
	118	+ .evt_wrptr = PCIE_SCRATCH_11_REG,
	119	+ .drv_rdy = PCIE_SCRATCH_12_REG,
	120	+ .tx_start_ptr = 16,
	121	+ .tx_mask = 0x0FFF0000,
	122	+ .tx_wrap_mask = 0x1FFF0000,
	123	+ .rx_mask = 0x00000FFF,
	124	+ .rx_wrap_mask = 0x00001FFF,
	125	+ .tx_rollover_ind = BIT(28),
	126	+ .rx_rollover_ind = BIT(12),
	127	+ .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	128	+ .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	129	+ .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	130	+ .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	131	+ .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	132	+ .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	133	+ .pfu_enabled = 1,
	134	+ .sleep_cookie = 0,
	135	+ .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
	136	+ .fw_dump_start = PCIE_SCRATCH_14_REG,
	137	+ .fw_dump_end = 0xcff,
	138	+ .fw_dump_host_ready = 0xcc,
	139	+ .fw_dump_read_done = 0xdd,
	140	+ .msix_support = 0,
	141	+};
	142	+
	143	+static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
	144	+ {"ITCM", NULL, 0, 0xF0},
	145	+ {"DTCM", NULL, 0, 0xF1},
	146	+ {"SQRAM", NULL, 0, 0xF2},
	147	+ {"IRAM", NULL, 0, 0xF3},
	148	+ {"APU", NULL, 0, 0xF4},
	149	+ {"CIU", NULL, 0, 0xF5},
	150	+ {"ICU", NULL, 0, 0xF6},
	151	+ {"MAC", NULL, 0, 0xF7},
	152	+};
	153	+
	154	+static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
	155	+ {"DUMP", NULL, 0, 0xDD},
	156	+};
	157	+
	158	+static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
	159	+ .reg = &mwifiex_reg_8766,
	160	+ .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	161	+ .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	162	+ .can_dump_fw = false,
	163	+ .can_ext_scan = true,
	164	+};
	165	+
	166	+static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
	167	+ .reg = &mwifiex_reg_8897,
	168	+ .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	169	+ .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
	170	+ .can_dump_fw = true,
	171	+ .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
	172	+ .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
	173	+ .can_ext_scan = true,
	174	+};
	175	+
	176	+static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
	177	+ .reg = &mwifiex_reg_8997,
	178	+ .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	179	+ .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
	180	+ .can_dump_fw = true,
	181	+ .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
	182	+ .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
	183	+ .can_ext_scan = true,
	184	+};
	185	+
	186	+static const struct of_device_id mwifiex_pcie_of_match_table[] __maybe_unused = {
37	187	{ .compatible = "pci11ab,2b42" },
38	188	{ .compatible = "pci1b4b,2b42" },
39	189	{ }
..	..	@@ -50,6 +200,8 @@
50	200	}
51	201
52	202	static void mwifiex_pcie_work(struct work_struct *work);
	203	+static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter);
	204	+static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter);
53	205
54	206	static int
55	207	mwifiex_map_pci_memory(struct mwifiex_adapter adapter, struct sk_buff skb,
..	..	@@ -58,8 +210,8 @@
58	210	struct pcie_service_card *card = adapter->card;
59	211	struct mwifiex_dma_mapping mapping;
60	212
61		- mapping.addr = pci_map_single(card->dev, skb->data, size, flags);
62		- if (pci_dma_mapping_error(card->dev, mapping.addr)) {
	213	+ mapping.addr = dma_map_single(&card->dev->dev, skb->data, size, flags);
	214	+ if (dma_mapping_error(&card->dev->dev, mapping.addr)) {
63	215	mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n");
64	216	return -1;
65	217	}
..	..	@@ -75,7 +227,7 @@
75	227	struct mwifiex_dma_mapping mapping;
76	228
77	229	mwifiex_get_mapping(skb, &mapping);
78		- pci_unmap_single(card->dev, mapping.addr, mapping.len, flags);
	230	+ dma_unmap_single(&card->dev->dev, mapping.addr, mapping.len, flags);
79	231	}
80	232
81	233	/*
..	..	@@ -150,10 +302,8 @@
150	302	static int mwifiex_pcie_suspend(struct device *dev)
151	303	{
152	304	struct mwifiex_adapter *adapter;
153		- struct pcie_service_card *card;
154		- struct pci_dev *pdev = to_pci_dev(dev);
	305	+ struct pcie_service_card *card = dev_get_drvdata(dev);
155	306
156		- card = pci_get_drvdata(pdev);
157	307
158	308	/* Might still be loading firmware */
159	309	wait_for_completion(&card->fw_done);
..	..	@@ -195,10 +345,8 @@
195	345	static int mwifiex_pcie_resume(struct device *dev)
196	346	{
197	347	struct mwifiex_adapter *adapter;
198		- struct pcie_service_card *card;
199		- struct pci_dev *pdev = to_pci_dev(dev);
	348	+ struct pcie_service_card *card = dev_get_drvdata(dev);
200	349
201		- card = pci_get_drvdata(pdev);
202	350
203	351	if (!card->adapter) {
204	352	dev_err(dev, "adapter structure is not valid\n");
..	..	@@ -469,10 +617,9 @@
469	617	struct sk_buff *cmdrsp = card->cmdrsp_buf;
470	618
471	619	for (count = 0; count < max_delay_loop_cnt; count++) {
472		- pci_dma_sync_single_for_cpu(card->dev,
473		- MWIFIEX_SKB_DMA_ADDR(cmdrsp),
474		- sizeof(sleep_cookie),
475		- PCI_DMA_FROMDEVICE);
	620	+ dma_sync_single_for_cpu(&card->dev->dev,
	621	+ MWIFIEX_SKB_DMA_ADDR(cmdrsp),
	622	+ sizeof(sleep_cookie), DMA_FROM_DEVICE);
476	623	buffer = cmdrsp->data;
477	624	sleep_cookie = get_unaligned_le32(buffer);
478	625
..	..	@@ -481,10 +628,10 @@
481	628	"sleep cookie found at count %d\n", count);
482	629	break;
483	630	}
484		- pci_dma_sync_single_for_device(card->dev,
485		- MWIFIEX_SKB_DMA_ADDR(cmdrsp),
486		- sizeof(sleep_cookie),
487		- PCI_DMA_FROMDEVICE);
	631	+ dma_sync_single_for_device(&card->dev->dev,
	632	+ MWIFIEX_SKB_DMA_ADDR(cmdrsp),
	633	+ sizeof(sleep_cookie),
	634	+ DMA_FROM_DEVICE);
488	635	usleep_range(20, 30);
489	636	}
490	637
..	..	@@ -493,11 +640,15 @@
493	640	"max count reached while accessing sleep cookie\n");
494	641	}
495	642
	643	+#define N_WAKEUP_TRIES_SHORT_INTERVAL 15
	644	+#define N_WAKEUP_TRIES_LONG_INTERVAL 35
	645	+
496	646	/* This function wakes up the card by reading fw_status register. */
497	647	static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter)
498	648	{
499	649	struct pcie_service_card *card = adapter->card;
500	650	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
	651	+ int retval;
501	652
502	653	mwifiex_dbg(adapter, EVENT,
503	654	"event: Wakeup device...\n");
..	..	@@ -505,11 +656,24 @@
505	656	if (reg->sleep_cookie)
506	657	mwifiex_pcie_dev_wakeup_delay(adapter);
507	658
508		- /* Accessing fw_status register will wakeup device */
509		- if (mwifiex_write_reg(adapter, reg->fw_status, FIRMWARE_READY_PCIE)) {
510		- mwifiex_dbg(adapter, ERROR,
511		- "Writing fw_status register failed\n");
512		- return -1;
	659	+ /* The 88W8897 PCIe+USB firmware (latest version 15.68.19.p21) sometimes
	660	+ * appears to ignore or miss our wakeup request, so we continue trying
	661	+ * until we receive an interrupt from the card.
	662	+ */
	663	+ if (read_poll_timeout(mwifiex_write_reg, retval,
	664	+ READ_ONCE(adapter->int_status) != 0,
	665	+ 500, 500 * N_WAKEUP_TRIES_SHORT_INTERVAL,
	666	+ false,
	667	+ adapter, reg->fw_status, FIRMWARE_READY_PCIE)) {
	668	+ if (read_poll_timeout(mwifiex_write_reg, retval,
	669	+ READ_ONCE(adapter->int_status) != 0,
	670	+ 10000, 10000 * N_WAKEUP_TRIES_LONG_INTERVAL,
	671	+ false,
	672	+ adapter, reg->fw_status, FIRMWARE_READY_PCIE)) {
	673	+ mwifiex_dbg(adapter, ERROR,
	674	+ "Firmware didn't wake up\n");
	675	+ return -EIO;
	676	+ }
513	677	}
514	678
515	679	if (reg->sleep_cookie) {
..	..	@@ -632,14 +796,15 @@
632	796	if (!skb) {
633	797	mwifiex_dbg(adapter, ERROR,
634	798	"Unable to allocate skb for RX ring.\n");
635		- kfree(card->rxbd_ring_vbase);
636	799	return -ENOMEM;
637	800	}
638	801
639	802	if (mwifiex_map_pci_memory(adapter, skb,
640	803	MWIFIEX_RX_DATA_BUF_SIZE,
641		- PCI_DMA_FROMDEVICE))
642		- return -1;
	804	+ DMA_FROM_DEVICE)) {
	805	+ kfree_skb(skb);
	806	+ return -ENOMEM;
	807	+ }
643	808
644	809	buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
645	810
..	..	@@ -689,16 +854,14 @@
689	854	if (!skb) {
690	855	mwifiex_dbg(adapter, ERROR,
691	856	"Unable to allocate skb for EVENT buf.\n");
692		- kfree(card->evtbd_ring_vbase);
693	857	return -ENOMEM;
694	858	}
695	859	skb_put(skb, MAX_EVENT_SIZE);
696	860
697	861	if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE,
698		- PCI_DMA_FROMDEVICE)) {
	862	+ DMA_FROM_DEVICE)) {
699	863	kfree_skb(skb);
700		- kfree(card->evtbd_ring_vbase);
701		- return -1;
	864	+ return -ENOMEM;
702	865	}
703	866
704	867	buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
..	..	@@ -738,7 +901,7 @@
738	901	if (card->tx_buf_list[i]) {
739	902	skb = card->tx_buf_list[i];
740	903	mwifiex_unmap_pci_memory(adapter, skb,
741		- PCI_DMA_TODEVICE);
	904	+ DMA_TO_DEVICE);
742	905	dev_kfree_skb_any(skb);
743	906	}
744	907	memset(desc2, 0, sizeof(*desc2));
..	..	@@ -747,7 +910,7 @@
747	910	if (card->tx_buf_list[i]) {
748	911	skb = card->tx_buf_list[i];
749	912	mwifiex_unmap_pci_memory(adapter, skb,
750		- PCI_DMA_TODEVICE);
	913	+ DMA_TO_DEVICE);
751	914	dev_kfree_skb_any(skb);
752	915	}
753	916	memset(desc, 0, sizeof(*desc));
..	..	@@ -777,7 +940,7 @@
777	940	if (card->rx_buf_list[i]) {
778	941	skb = card->rx_buf_list[i];
779	942	mwifiex_unmap_pci_memory(adapter, skb,
780		- PCI_DMA_FROMDEVICE);
	943	+ DMA_FROM_DEVICE);
781	944	dev_kfree_skb_any(skb);
782	945	}
783	946	memset(desc2, 0, sizeof(*desc2));
..	..	@@ -786,7 +949,7 @@
786	949	if (card->rx_buf_list[i]) {
787	950	skb = card->rx_buf_list[i];
788	951	mwifiex_unmap_pci_memory(adapter, skb,
789		- PCI_DMA_FROMDEVICE);
	952	+ DMA_FROM_DEVICE);
790	953	dev_kfree_skb_any(skb);
791	954	}
792	955	memset(desc, 0, sizeof(*desc));
..	..	@@ -812,7 +975,7 @@
812	975	if (card->evt_buf_list[i]) {
813	976	skb = card->evt_buf_list[i];
814	977	mwifiex_unmap_pci_memory(adapter, skb,
815		- PCI_DMA_FROMDEVICE);
	978	+ DMA_FROM_DEVICE);
816	979	dev_kfree_skb_any(skb);
817	980	}
818	981	card->evt_buf_list[i] = NULL;
..	..	@@ -853,18 +1016,20 @@
853	1016	mwifiex_dbg(adapter, INFO,
854	1017	"info: txbd_ring: Allocating %d bytes\n",
855	1018	card->txbd_ring_size);
856		- card->txbd_ring_vbase = pci_alloc_consistent(card->dev,
857		- card->txbd_ring_size,
858		- &card->txbd_ring_pbase);
	1019	+ card->txbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
	1020	+ card->txbd_ring_size,
	1021	+ &card->txbd_ring_pbase,
	1022	+ GFP_KERNEL);
859	1023	if (!card->txbd_ring_vbase) {
860	1024	mwifiex_dbg(adapter, ERROR,
861		- "allocate consistent memory (%d bytes) failed!\n",
	1025	+ "allocate coherent memory (%d bytes) failed!\n",
862	1026	card->txbd_ring_size);
863	1027	return -ENOMEM;
864	1028	}
	1029	+
865	1030	mwifiex_dbg(adapter, DATA,
866		- "info: txbd_ring - base: %p, pbase: %#x:%x, len: %x\n",
867		- card->txbd_ring_vbase, (unsigned int)card->txbd_ring_pbase,
	1031	+ "info: txbd_ring - base: %p, pbase: %#x:%x, len: %#x\n",
	1032	+ card->txbd_ring_vbase, (u32)card->txbd_ring_pbase,
868	1033	(u32)((u64)card->txbd_ring_pbase >> 32),
869	1034	card->txbd_ring_size);
870	1035
..	..	@@ -879,9 +1044,9 @@
879	1044	mwifiex_cleanup_txq_ring(adapter);
880	1045
881	1046	if (card->txbd_ring_vbase)
882		- pci_free_consistent(card->dev, card->txbd_ring_size,
883		- card->txbd_ring_vbase,
884		- card->txbd_ring_pbase);
	1047	+ dma_free_coherent(&card->dev->dev, card->txbd_ring_size,
	1048	+ card->txbd_ring_vbase,
	1049	+ card->txbd_ring_pbase);
885	1050	card->txbd_ring_size = 0;
886	1051	card->txbd_wrptr = 0;
887	1052	card->txbd_rdptr = 0 \| reg->tx_rollover_ind;
..	..	@@ -896,6 +1061,7 @@
896	1061	*/
897	1062	static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter)
898	1063	{
	1064	+ int ret;
899	1065	struct pcie_service_card *card = adapter->card;
900	1066	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
901	1067
..	..	@@ -917,12 +1083,13 @@
917	1083	mwifiex_dbg(adapter, INFO,
918	1084	"info: rxbd_ring: Allocating %d bytes\n",
919	1085	card->rxbd_ring_size);
920		- card->rxbd_ring_vbase = pci_alloc_consistent(card->dev,
921		- card->rxbd_ring_size,
922		- &card->rxbd_ring_pbase);
	1086	+ card->rxbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
	1087	+ card->rxbd_ring_size,
	1088	+ &card->rxbd_ring_pbase,
	1089	+ GFP_KERNEL);
923	1090	if (!card->rxbd_ring_vbase) {
924	1091	mwifiex_dbg(adapter, ERROR,
925		- "allocate consistent memory (%d bytes) failed!\n",
	1092	+ "allocate coherent memory (%d bytes) failed!\n",
926	1093	card->rxbd_ring_size);
927	1094	return -ENOMEM;
928	1095	}
..	..	@@ -933,7 +1100,10 @@
933	1100	(u32)((u64)card->rxbd_ring_pbase >> 32),
934	1101	card->rxbd_ring_size);
935	1102
936		- return mwifiex_init_rxq_ring(adapter);
	1103	+ ret = mwifiex_init_rxq_ring(adapter);
	1104	+ if (ret)
	1105	+ mwifiex_pcie_delete_rxbd_ring(adapter);
	1106	+ return ret;
937	1107	}
938	1108
939	1109	/*
..	..	@@ -947,9 +1117,9 @@
947	1117	mwifiex_cleanup_rxq_ring(adapter);
948	1118
949	1119	if (card->rxbd_ring_vbase)
950		- pci_free_consistent(card->dev, card->rxbd_ring_size,
951		- card->rxbd_ring_vbase,
952		- card->rxbd_ring_pbase);
	1120	+ dma_free_coherent(&card->dev->dev, card->rxbd_ring_size,
	1121	+ card->rxbd_ring_vbase,
	1122	+ card->rxbd_ring_pbase);
953	1123	card->rxbd_ring_size = 0;
954	1124	card->rxbd_wrptr = 0;
955	1125	card->rxbd_rdptr = 0 \| reg->rx_rollover_ind;
..	..	@@ -964,6 +1134,7 @@
964	1134	*/
965	1135	static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter)
966	1136	{
	1137	+ int ret;
967	1138	struct pcie_service_card *card = adapter->card;
968	1139	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
969	1140
..	..	@@ -980,13 +1151,14 @@
980	1151
981	1152	mwifiex_dbg(adapter, INFO,
982	1153	"info: evtbd_ring: Allocating %d bytes\n",
983		- card->evtbd_ring_size);
984		- card->evtbd_ring_vbase = pci_alloc_consistent(card->dev,
985		- card->evtbd_ring_size,
986		- &card->evtbd_ring_pbase);
	1154	+ card->evtbd_ring_size);
	1155	+ card->evtbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
	1156	+ card->evtbd_ring_size,
	1157	+ &card->evtbd_ring_pbase,
	1158	+ GFP_KERNEL);
987	1159	if (!card->evtbd_ring_vbase) {
988	1160	mwifiex_dbg(adapter, ERROR,
989		- "allocate consistent memory (%d bytes) failed!\n",
	1161	+ "allocate coherent memory (%d bytes) failed!\n",
990	1162	card->evtbd_ring_size);
991	1163	return -ENOMEM;
992	1164	}
..	..	@@ -997,7 +1169,10 @@
997	1169	(u32)((u64)card->evtbd_ring_pbase >> 32),
998	1170	card->evtbd_ring_size);
999	1171
1000		- return mwifiex_pcie_init_evt_ring(adapter);
	1172	+ ret = mwifiex_pcie_init_evt_ring(adapter);
	1173	+ if (ret)
	1174	+ mwifiex_pcie_delete_evtbd_ring(adapter);
	1175	+ return ret;
1001	1176	}
1002	1177
1003	1178	/*
..	..	@@ -1011,9 +1186,9 @@
1011	1186	mwifiex_cleanup_evt_ring(adapter);
1012	1187
1013	1188	if (card->evtbd_ring_vbase)
1014		- pci_free_consistent(card->dev, card->evtbd_ring_size,
1015		- card->evtbd_ring_vbase,
1016		- card->evtbd_ring_pbase);
	1189	+ dma_free_coherent(&card->dev->dev, card->evtbd_ring_size,
	1190	+ card->evtbd_ring_vbase,
	1191	+ card->evtbd_ring_pbase);
1017	1192	card->evtbd_wrptr = 0;
1018	1193	card->evtbd_rdptr = 0 \| reg->evt_rollover_ind;
1019	1194	card->evtbd_ring_size = 0;
..	..	@@ -1040,7 +1215,7 @@
1040	1215	}
1041	1216	skb_put(skb, MWIFIEX_UPLD_SIZE);
1042	1217	if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1043		- PCI_DMA_FROMDEVICE)) {
	1218	+ DMA_FROM_DEVICE)) {
1044	1219	kfree_skb(skb);
1045	1220	return -1;
1046	1221	}
..	..	@@ -1064,14 +1239,14 @@
1064	1239
1065	1240	if (card && card->cmdrsp_buf) {
1066	1241	mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf,
1067		- PCI_DMA_FROMDEVICE);
	1242	+ DMA_FROM_DEVICE);
1068	1243	dev_kfree_skb_any(card->cmdrsp_buf);
1069	1244	card->cmdrsp_buf = NULL;
1070	1245	}
1071	1246
1072	1247	if (card && card->cmd_buf) {
1073	1248	mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
1074		- PCI_DMA_TODEVICE);
	1249	+ DMA_TO_DEVICE);
1075	1250	dev_kfree_skb_any(card->cmd_buf);
1076	1251	card->cmd_buf = NULL;
1077	1252	}
..	..	@@ -1086,11 +1261,13 @@
1086	1261	struct pcie_service_card *card = adapter->card;
1087	1262	u32 *cookie;
1088	1263
1089		- card->sleep_cookie_vbase = pci_alloc_consistent(card->dev, sizeof(u32),
1090		- &card->sleep_cookie_pbase);
	1264	+ card->sleep_cookie_vbase = dma_alloc_coherent(&card->dev->dev,
	1265	+ sizeof(u32),
	1266	+ &card->sleep_cookie_pbase,
	1267	+ GFP_KERNEL);
1091	1268	if (!card->sleep_cookie_vbase) {
1092	1269	mwifiex_dbg(adapter, ERROR,
1093		- "pci_alloc_consistent failed!\n");
	1270	+ "dma_alloc_coherent failed!\n");
1094	1271	return -ENOMEM;
1095	1272	}
1096	1273	cookie = (u32 *)card->sleep_cookie_vbase;
..	..	@@ -1115,9 +1292,9 @@
1115	1292	card = adapter->card;
1116	1293
1117	1294	if (card && card->sleep_cookie_vbase) {
1118		- pci_free_consistent(card->dev, sizeof(u32),
1119		- card->sleep_cookie_vbase,
1120		- card->sleep_cookie_pbase);
	1295	+ dma_free_coherent(&card->dev->dev, sizeof(u32),
	1296	+ card->sleep_cookie_vbase,
	1297	+ card->sleep_cookie_pbase);
1121	1298	card->sleep_cookie_vbase = NULL;
1122	1299	}
1123	1300
..	..	@@ -1189,7 +1366,7 @@
1189	1366	"SEND COMP: Detach skb %p at txbd_rdidx=%d\n",
1190	1367	skb, wrdoneidx);
1191	1368	mwifiex_unmap_pci_memory(adapter, skb,
1192		- PCI_DMA_TODEVICE);
	1369	+ DMA_TO_DEVICE);
1193	1370
1194	1371	unmap_count++;
1195	1372
..	..	@@ -1282,7 +1459,7 @@
1282	1459	put_unaligned_le16(MWIFIEX_TYPE_DATA, payload + 2);
1283	1460
1284	1461	if (mwifiex_map_pci_memory(adapter, skb, skb->len,
1285		- PCI_DMA_TODEVICE))
	1462	+ DMA_TO_DEVICE))
1286	1463	return -1;
1287	1464
1288	1465	wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr;
..	..	@@ -1372,7 +1549,7 @@
1372	1549
1373	1550	return -EINPROGRESS;
1374	1551	done_unmap:
1375		- mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
	1552	+ mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1376	1553	card->tx_buf_list[wrindx] = NULL;
1377	1554	atomic_dec(&adapter->tx_hw_pending);
1378	1555	if (reg->pfu_enabled)
..	..	@@ -1426,7 +1603,7 @@
1426	1603	if (!skb_data)
1427	1604	return -ENOMEM;
1428	1605
1429		- mwifiex_unmap_pci_memory(adapter, skb_data, PCI_DMA_FROMDEVICE);
	1606	+ mwifiex_unmap_pci_memory(adapter, skb_data, DMA_FROM_DEVICE);
1430	1607	card->rx_buf_list[rd_index] = NULL;
1431	1608
1432	1609	/* Get data length from interface header -
..	..	@@ -1464,7 +1641,7 @@
1464	1641
1465	1642	if (mwifiex_map_pci_memory(adapter, skb_tmp,
1466	1643	MWIFIEX_RX_DATA_BUF_SIZE,
1467		- PCI_DMA_FROMDEVICE))
	1644	+ DMA_FROM_DEVICE))
1468	1645	return -1;
1469	1646
1470	1647	buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp);
..	..	@@ -1541,7 +1718,7 @@
1541	1718	return -1;
1542	1719	}
1543	1720
1544		- if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE))
	1721	+ if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE))
1545	1722	return -1;
1546	1723
1547	1724	buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
..	..	@@ -1553,7 +1730,7 @@
1553	1730	mwifiex_dbg(adapter, ERROR,
1554	1731	"%s: failed to write download command to boot code.\n",
1555	1732	__func__);
1556		- mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
	1733	+ mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1557	1734	return -1;
1558	1735	}
1559	1736
..	..	@@ -1565,7 +1742,7 @@
1565	1742	mwifiex_dbg(adapter, ERROR,
1566	1743	"%s: failed to write download command to boot code.\n",
1567	1744	__func__);
1568		- mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
	1745	+ mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1569	1746	return -1;
1570	1747	}
1571	1748
..	..	@@ -1574,7 +1751,7 @@
1574	1751	mwifiex_dbg(adapter, ERROR,
1575	1752	"%s: failed to write command len to cmd_size scratch reg\n",
1576	1753	__func__);
1577		- mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
	1754	+ mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1578	1755	return -1;
1579	1756	}
1580	1757
..	..	@@ -1583,7 +1760,7 @@
1583	1760	CPU_INTR_DOOR_BELL)) {
1584	1761	mwifiex_dbg(adapter, ERROR,
1585	1762	"%s: failed to assert door-bell intr\n", __func__);
1586		- mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
	1763	+ mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1587	1764	return -1;
1588	1765	}
1589	1766
..	..	@@ -1642,7 +1819,7 @@
1642	1819	put_unaligned_le16((u16)skb->len, &payload[0]);
1643	1820	put_unaligned_le16(MWIFIEX_TYPE_CMD, &payload[2]);
1644	1821
1645		- if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE))
	1822	+ if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE))
1646	1823	return -1;
1647	1824
1648	1825	card->cmd_buf = skb;
..	..	@@ -1742,17 +1919,16 @@
1742	1919	"info: Rx CMD Response\n");
1743	1920
1744	1921	if (adapter->curr_cmd)
1745		- mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_FROMDEVICE);
	1922	+ mwifiex_unmap_pci_memory(adapter, skb, DMA_FROM_DEVICE);
1746	1923	else
1747		- pci_dma_sync_single_for_cpu(card->dev,
1748		- MWIFIEX_SKB_DMA_ADDR(skb),
1749		- MWIFIEX_UPLD_SIZE,
1750		- PCI_DMA_FROMDEVICE);
	1924	+ dma_sync_single_for_cpu(&card->dev->dev,
	1925	+ MWIFIEX_SKB_DMA_ADDR(skb),
	1926	+ MWIFIEX_UPLD_SIZE, DMA_FROM_DEVICE);
1751	1927
1752	1928	/* Unmap the command as a response has been received. */
1753	1929	if (card->cmd_buf) {
1754	1930	mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
1755		- PCI_DMA_TODEVICE);
	1931	+ DMA_TO_DEVICE);
1756	1932	dev_kfree_skb_any(card->cmd_buf);
1757	1933	card->cmd_buf = NULL;
1758	1934	}
..	..	@@ -1763,10 +1939,10 @@
1763	1939
1764	1940	if (!adapter->curr_cmd) {
1765	1941	if (adapter->ps_state == PS_STATE_SLEEP_CFM) {
1766		- pci_dma_sync_single_for_device(card->dev,
1767		- MWIFIEX_SKB_DMA_ADDR(skb),
1768		- MWIFIEX_SLEEP_COOKIE_SIZE,
1769		- PCI_DMA_FROMDEVICE);
	1942	+ dma_sync_single_for_device(&card->dev->dev,
	1943	+ MWIFIEX_SKB_DMA_ADDR(skb),
	1944	+ MWIFIEX_SLEEP_COOKIE_SIZE,
	1945	+ DMA_FROM_DEVICE);
1770	1946	if (mwifiex_write_reg(adapter,
1771	1947	PCIE_CPU_INT_EVENT,
1772	1948	CPU_INTR_SLEEP_CFM_DONE)) {
..	..	@@ -1777,7 +1953,7 @@
1777	1953	mwifiex_delay_for_sleep_cookie(adapter,
1778	1954	MWIFIEX_MAX_DELAY_COUNT);
1779	1955	mwifiex_unmap_pci_memory(adapter, skb,
1780		- PCI_DMA_FROMDEVICE);
	1956	+ DMA_FROM_DEVICE);
1781	1957	skb_pull(skb, adapter->intf_hdr_len);
1782	1958	while (reg->sleep_cookie && (count++ < 10) &&
1783	1959	mwifiex_pcie_ok_to_access_hw(adapter))
..	..	@@ -1793,7 +1969,7 @@
1793	1969	min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len));
1794	1970	skb_push(skb, adapter->intf_hdr_len);
1795	1971	if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1796		- PCI_DMA_FROMDEVICE))
	1972	+ DMA_FROM_DEVICE))
1797	1973	return -1;
1798	1974	} else if (mwifiex_pcie_ok_to_access_hw(adapter)) {
1799	1975	skb_pull(skb, adapter->intf_hdr_len);
..	..	@@ -1835,7 +2011,7 @@
1835	2011	card->cmdrsp_buf = skb;
1836	2012	skb_push(card->cmdrsp_buf, adapter->intf_hdr_len);
1837	2013	if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1838		- PCI_DMA_FROMDEVICE))
	2014	+ DMA_FROM_DEVICE))
1839	2015	return -1;
1840	2016	}
1841	2017
..	..	@@ -1890,7 +2066,7 @@
1890	2066	mwifiex_dbg(adapter, INFO,
1891	2067	"info: Read Index: %d\n", rdptr);
1892	2068	skb_cmd = card->evt_buf_list[rdptr];
1893		- mwifiex_unmap_pci_memory(adapter, skb_cmd, PCI_DMA_FROMDEVICE);
	2069	+ mwifiex_unmap_pci_memory(adapter, skb_cmd, DMA_FROM_DEVICE);
1894	2070
1895	2071	/* Take the pointer and set it to event pointer in adapter
1896	2072	and will return back after event handling callback */
..	..	@@ -1970,7 +2146,7 @@
1970	2146	skb_put(skb, MAX_EVENT_SIZE - skb->len);
1971	2147	if (mwifiex_map_pci_memory(adapter, skb,
1972	2148	MAX_EVENT_SIZE,
1973		- PCI_DMA_FROMDEVICE))
	2149	+ DMA_FROM_DEVICE))
1974	2150	return -1;
1975	2151	card->evt_buf_list[rdptr] = skb;
1976	2152	desc = card->evtbd_ring[rdptr];
..	..	@@ -2252,7 +2428,7 @@
2252	2428	"interrupt status during fw dnld.\n",
2253	2429	__func__);
2254	2430	mwifiex_unmap_pci_memory(adapter, skb,
2255		- PCI_DMA_TODEVICE);
	2431	+ DMA_TO_DEVICE);
2256	2432	ret = -1;
2257	2433	goto done;
2258	2434	}
..	..	@@ -2264,12 +2440,12 @@
2264	2440	mwifiex_dbg(adapter, ERROR, "%s: Card failed to ACK download\n",
2265	2441	__func__);
2266	2442	mwifiex_unmap_pci_memory(adapter, skb,
2267		- PCI_DMA_TODEVICE);
	2443	+ DMA_TO_DEVICE);
2268	2444	ret = -1;
2269	2445	goto done;
2270	2446	}
2271	2447
2272		- mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
	2448	+ mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
2273	2449
2274	2450	offset += txlen;
2275	2451	} while (true);
..	..	@@ -2939,16 +3115,9 @@
2939	3115
2940	3116	pci_set_master(pdev);
2941	3117
2942		- pr_notice("try set_consistent_dma_mask(32)\n");
2943		- ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	3118	+ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2944	3119	if (ret) {
2945		- pr_err("set_dma_mask(32) failed\n");
2946		- goto err_set_dma_mask;
2947		- }
2948		-
2949		- ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2950		- if (ret) {
2951		- pr_err("set_consistent_dma_mask(64) failed\n");
	3120	+ pr_err("dma_set_mask(32) failed: %d\n", ret);
2952	3121	goto err_set_dma_mask;
2953	3122	}
2954	3123
..	..	@@ -2975,13 +3144,16 @@
2975	3144	goto err_iomap2;
2976	3145	}
2977	3146
2978		- pr_notice("PCI memory map Virt0: %p PCI memory map Virt2: %p\n",
	3147	+ pr_notice("PCI memory map Virt0: %pK PCI memory map Virt2: %pK\n",
2979	3148	card->pci_mmap, card->pci_mmap1);
2980	3149
2981	3150	ret = mwifiex_pcie_alloc_buffers(adapter);
2982	3151	if (ret)
2983	3152	goto err_alloc_buffers;
2984	3153
	3154	+ if (pdev->device == PCIE_DEVICE_ID_MARVELL_88W8897)
	3155	+ adapter->ignore_btcoex_events = true;
	3156	+
2985	3157	return 0;
2986	3158
2987	3159	err_alloc_buffers: