| .. | .. |
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| 5 | 5 | * |
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| 6 | 6 | * GPL LICENSE SUMMARY |
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| 7 | 7 | * |
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| 8 | | - * Copyright(c) 2018 Intel Corporation |
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| 8 | + * Copyright(c) 2018, 2020 Intel Corporation |
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| 9 | 9 | * |
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| 10 | 10 | * This program is free software; you can redistribute it and/or modify |
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| 11 | 11 | * it under the terms of version 2 of the GNU General Public License as |
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| .. | .. |
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| 18 | 18 | * |
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| 19 | 19 | * BSD LICENSE |
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| 20 | 20 | * |
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| 21 | | - * Copyright(c) 2018 Intel Corporation |
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| 21 | + * Copyright(c) 2018, 2020 Intel Corporation |
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| 22 | 22 | * All rights reserved. |
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| 23 | 23 | * |
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| 24 | 24 | * Redistribution and use in source and binary forms, with or without |
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| .. | .. |
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| 93 | 93 | * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. |
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| 94 | 94 | * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, |
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| 95 | 95 | * 3: 256 bit. |
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| 96 | + * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored |
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| 97 | + * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K |
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| 98 | + * appropriately; use the below values for this. |
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| 99 | + * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size |
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| 100 | + * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size |
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| 96 | 101 | */ |
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| 97 | 102 | enum iwl_prph_scratch_flags { |
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| 98 | 103 | IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), |
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| .. | .. |
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| 103 | 108 | IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), |
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| 104 | 109 | IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), |
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| 105 | 110 | IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), |
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| 111 | + IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20, |
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| 112 | + IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20, |
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| 113 | + IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20, |
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| 106 | 114 | }; |
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| 107 | 115 | |
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| 108 | 116 | /* |
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| .. | .. |
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| 130 | 138 | } __packed; /* PERIPH_SCRATCH_CONTROL_S */ |
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| 131 | 139 | |
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| 132 | 140 | /* |
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| 133 | | - * struct iwl_prph_scratch_ror_cfg - ror config |
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| 134 | | - * @ror_base_addr: ror start address |
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| 135 | | - * @ror_size: ror size in DWs |
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| 141 | + * struct iwl_prph_scratch_pnvm_cfg - ror config |
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| 142 | + * @pnvm_base_addr: PNVM start address |
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| 143 | + * @pnvm_size: PNVM size in DWs |
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| 136 | 144 | * @reserved: reserved |
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| 137 | 145 | */ |
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| 138 | | -struct iwl_prph_scratch_ror_cfg { |
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| 139 | | - __le64 ror_base_addr; |
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| 140 | | - __le32 ror_size; |
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| 146 | +struct iwl_prph_scratch_pnvm_cfg { |
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| 147 | + __le64 pnvm_base_addr; |
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| 148 | + __le32 pnvm_size; |
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| 141 | 149 | __le32 reserved; |
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| 142 | | -} __packed; /* PERIPH_SCRATCH_ROR_CFG_S */ |
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| 150 | +} __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ |
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| 143 | 151 | |
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| 144 | 152 | /* |
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| 145 | 153 | * struct iwl_prph_scratch_hwm_cfg - hwm config |
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| .. | .. |
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| 167 | 175 | * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config |
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| 168 | 176 | * @version: version information of context info and HW |
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| 169 | 177 | * @control: control flags of FH configurations |
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| 170 | | - * @ror_cfg: ror configuration |
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| 178 | + * @pnvm_cfg: ror configuration |
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| 171 | 179 | * @hwm_cfg: hwm configuration |
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| 172 | 180 | * @rbd_cfg: default RX queue configuration |
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| 173 | 181 | */ |
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| 174 | 182 | struct iwl_prph_scratch_ctrl_cfg { |
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| 175 | 183 | struct iwl_prph_scratch_version version; |
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| 176 | 184 | struct iwl_prph_scratch_control control; |
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| 177 | | - struct iwl_prph_scratch_ror_cfg ror_cfg; |
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| 185 | + struct iwl_prph_scratch_pnvm_cfg pnvm_cfg; |
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| 178 | 186 | struct iwl_prph_scratch_hwm_cfg hwm_cfg; |
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| 179 | 187 | struct iwl_prph_scratch_rbd_cfg rbd_cfg; |
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| 180 | 188 | } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ |
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| .. | .. |
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| 283 | 291 | const struct fw_img *fw); |
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| 284 | 292 | void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans); |
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| 285 | 293 | |
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| 294 | +int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, |
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| 295 | + const void *data, u32 len); |
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| 296 | + |
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| 286 | 297 | #endif /* __iwl_context_info_file_gen3_h__ */ |
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