| .. | .. |
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| 1328 | 1328 | {0x0000c284, 0x00000000, 0x00000000, 0x00000150, 0x00000150}, |
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| 1329 | 1329 | }; |
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| 1330 | 1330 | |
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| 1331 | | -static const u32 ar9580_1p0_pcie_phy_clkreq_enable_L1[][2] = { |
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| 1332 | | - /* Addr allmodes */ |
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| 1333 | | - {0x00004040, 0x0835365e}, |
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| 1334 | | - {0x00004040, 0x0008003b}, |
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| 1335 | | - {0x00004044, 0x00000000}, |
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| 1336 | | -}; |
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| 1337 | | - |
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| 1338 | | -static const u32 ar9580_1p0_pcie_phy_clkreq_disable_L1[][2] = { |
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| 1339 | | - /* Addr allmodes */ |
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| 1340 | | - {0x00004040, 0x0831365e}, |
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| 1341 | | - {0x00004040, 0x0008003b}, |
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| 1342 | | - {0x00004044, 0x00000000}, |
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| 1343 | | -}; |
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| 1344 | | - |
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| 1345 | | -static const u32 ar9580_1p0_pcie_phy_pll_on_clkreq[][2] = { |
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| 1346 | | - /* Addr allmodes */ |
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| 1347 | | - {0x00004040, 0x0831265e}, |
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| 1348 | | - {0x00004040, 0x0008003b}, |
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| 1349 | | - {0x00004044, 0x00000000}, |
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| 1350 | | -}; |
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| 1351 | | - |
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| 1352 | 1331 | static const u32 ar9580_1p0_baseband_postamble_dfs_channel[][3] = { |
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| 1353 | 1332 | /* Addr 5G 2G */ |
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| 1354 | 1333 | {0x00009814, 0x3400c00f, 0x3400c00f}, |
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