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2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/net/vmxnet3/vmxnet3_defs.h
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@@ -1,7 +1,7 @@
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 /*
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  * Linux driver for VMware's vmxnet3 ethernet NIC.
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  *
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- * Copyright (C) 2008-2016, VMware, Inc. All Rights Reserved.
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+ * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
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  *
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  * This program is free software; you can redistribute it and/or modify it
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  * under the terms of the GNU General Public License as published by the
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@@ -82,6 +82,7 @@
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 	VMXNET3_CMD_RESERVED3,
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 	VMXNET3_CMD_SET_COALESCE,
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 	VMXNET3_CMD_REGISTER_MEMREGS,
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+	VMXNET3_CMD_SET_RSS_FIELDS,
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 	VMXNET3_CMD_FIRST_GET = 0xF00D0000,
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 	VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
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@@ -96,19 +97,20 @@
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 	VMXNET3_CMD_GET_RESERVED1,
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 	VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
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 	VMXNET3_CMD_GET_COALESCE,
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+	VMXNET3_CMD_GET_RSS_FIELDS,
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 };
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 /*
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  *	Little Endian layout of bitfields -
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  *	Byte 0 :	7.....len.....0
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- *	Byte 1 :	rsvd gen 13.len.8
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+ *	Byte 1 :	oco gen 13.len.8
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  *	Byte 2 : 	5.msscof.0 ext1  dtype
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  *	Byte 3 : 	13...msscof...6
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  *
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  *	Big Endian layout of bitfields -
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  *	Byte 0:		13...msscof...6
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  *	Byte 1 : 	5.msscof.0 ext1  dtype
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- *	Byte 2 :	rsvd gen 13.len.8
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+ *	Byte 2 :	oco gen 13.len.8
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  *	Byte 3 :	7.....len.....0
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  *
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  *	Thus, le32_to_cpu on the dword will allow the big endian driver to read
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@@ -123,13 +125,13 @@
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 	u32 msscof:14;  /* MSS, checksum offset, flags */
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 	u32 ext1:1;
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 	u32 dtype:1;    /* descriptor type */
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-	u32 rsvd:1;
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+	u32 oco:1;
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 	u32 gen:1;      /* generation bit */
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 	u32 len:14;
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 #else
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 	u32 len:14;
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 	u32 gen:1;      /* generation bit */
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-	u32 rsvd:1;
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+	u32 oco:1;
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 	u32 dtype:1;    /* descriptor type */
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 	u32 ext1:1;
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 	u32 msscof:14;  /* MSS, checksum offset, flags */
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@@ -155,9 +157,10 @@
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 };
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 /* TxDesc.OM values */
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-#define VMXNET3_OM_NONE		0
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-#define VMXNET3_OM_CSUM		2
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-#define VMXNET3_OM_TSO		3
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+#define VMXNET3_OM_NONE         0
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+#define VMXNET3_OM_ENCAP        1
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+#define VMXNET3_OM_CSUM         2
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+#define VMXNET3_OM_TSO          3
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 /* fields in TxDesc we access w/o using bit fields */
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 #define VMXNET3_TXD_EOP_SHIFT	12
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@@ -223,6 +226,8 @@
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 /* fields in RxDesc we access w/o using bit fields */
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 #define VMXNET3_RXD_BTYPE_SHIFT  14
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 #define VMXNET3_RXD_GEN_SHIFT    31
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+
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+#define VMXNET3_RCD_HDR_INNER_SHIFT  13
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 struct Vmxnet3_RxCompDesc {
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 #ifdef __BIG_ENDIAN_BITFIELD
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@@ -685,12 +690,22 @@
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 	struct Vmxnet3_MemoryRegion		memRegs[1];
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 };
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+enum Vmxnet3_RSSField {
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+	VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001,
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+	VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002,
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+	VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004,
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+	VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008,
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+	VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010,
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+	VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020,
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+};
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+
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 /* If the command data <= 16 bytes, use the shared memory directly.
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  * otherwise, use variable length configuration descriptor.
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  */
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 union Vmxnet3_CmdInfo {
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 	struct Vmxnet3_VariableLenConfDesc	varConf;
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 	struct Vmxnet3_SetPolling		setPolling;
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+	enum   Vmxnet3_RSSField                 setRssFields;
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 	__le64					data[2];
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 };
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