| .. | .. |
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| 139 | 139 | value &= ~DP83811_WOL_SECURE_ON; |
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| 140 | 140 | } |
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| 141 | 141 | |
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| 142 | | - value |= (DP83811_WOL_EN | DP83811_WOL_INDICATION_SEL | |
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| 143 | | - DP83811_WOL_CLR_INDICATION); |
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| 144 | | - phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, |
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| 145 | | - value); |
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| 142 | + /* Clear any pending WoL interrupt */ |
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| 143 | + phy_read(phydev, MII_DP83811_INT_STAT1); |
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| 144 | + |
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| 145 | + value |= DP83811_WOL_EN | DP83811_WOL_INDICATION_SEL | |
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| 146 | + DP83811_WOL_CLR_INDICATION; |
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| 147 | + |
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| 148 | + return phy_write_mmd(phydev, DP83811_DEVADDR, |
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| 149 | + MII_DP83811_WOL_CFG, value); |
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| 146 | 150 | } else { |
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| 147 | | - value = phy_read_mmd(phydev, DP83811_DEVADDR, |
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| 148 | | - MII_DP83811_WOL_CFG); |
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| 149 | | - value &= ~DP83811_WOL_EN; |
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| 150 | | - phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, |
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| 151 | | - value); |
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| 151 | + return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, |
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| 152 | + MII_DP83811_WOL_CFG, DP83811_WOL_EN); |
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| 152 | 153 | } |
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| 153 | 154 | |
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| 154 | | - return 0; |
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| 155 | 155 | } |
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| 156 | 156 | |
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| 157 | 157 | static void dp83811_get_wol(struct phy_device *phydev, |
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| .. | .. |
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| 280 | 280 | { |
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| 281 | 281 | int value, err; |
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| 282 | 282 | |
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| 283 | | - err = genphy_config_init(phydev); |
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| 284 | | - if (err < 0) |
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| 285 | | - return err; |
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| 286 | | - |
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| 287 | 283 | value = phy_read(phydev, MII_DP83811_SGMII_CTRL); |
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| 288 | 284 | if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { |
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| 289 | 285 | err = phy_write(phydev, MII_DP83811_SGMII_CTRL, |
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| .. | .. |
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| 299 | 295 | |
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| 300 | 296 | value = DP83811_WOL_MAGIC_EN | DP83811_WOL_SECURE_ON | DP83811_WOL_EN; |
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| 301 | 297 | |
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| 302 | | - return phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, |
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| 303 | | - value); |
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| 298 | + return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, |
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| 299 | + value); |
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| 304 | 300 | } |
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| 305 | 301 | |
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| 306 | 302 | static int dp83811_phy_reset(struct phy_device *phydev) |
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| .. | .. |
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| 328 | 324 | |
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| 329 | 325 | static int dp83811_resume(struct phy_device *phydev) |
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| 330 | 326 | { |
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| 331 | | - int value; |
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| 332 | | - |
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| 333 | 327 | genphy_resume(phydev); |
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| 334 | 328 | |
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| 335 | | - value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG); |
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| 336 | | - |
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| 337 | | - phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, value | |
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| 338 | | - DP83811_WOL_CLR_INDICATION); |
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| 329 | + phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, |
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| 330 | + DP83811_WOL_CLR_INDICATION); |
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| 339 | 331 | |
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| 340 | 332 | return 0; |
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| 341 | 333 | } |
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| .. | .. |
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| 345 | 337 | .phy_id = DP83TC811_PHY_ID, |
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| 346 | 338 | .phy_id_mask = 0xfffffff0, |
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| 347 | 339 | .name = "TI DP83TC811", |
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| 348 | | - .features = PHY_BASIC_FEATURES, |
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| 349 | | - .flags = PHY_HAS_INTERRUPT, |
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| 340 | + /* PHY_BASIC_FEATURES */ |
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| 350 | 341 | .config_init = dp83811_config_init, |
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| 351 | 342 | .config_aneg = dp83811_config_aneg, |
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| 352 | 343 | .soft_reset = dp83811_phy_reset, |
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