forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
....@@ -27,6 +27,9 @@
2727 	if (dma_cfg->aal)
2828 		value |= XGMAC_AAL;
2929 
30
+	if (dma_cfg->eame)
31
+		value |= XGMAC_EAME;
32
+
3033 	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
3134 }
3235 
....@@ -44,7 +47,7 @@
4447 
4548 static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
4649 				      struct stmmac_dma_cfg *dma_cfg,
47
-				      u32 dma_rx_phy, u32 chan)
50
+				      dma_addr_t phy, u32 chan)
4851 {
4952 	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
5053 	u32 value;
....@@ -54,12 +57,13 @@
5457 	value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
5558 	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
5659 
57
-	writel(dma_rx_phy, ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
60
+	writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
61
+	writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
5862 }
5963 
6064 static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
6165 				      struct stmmac_dma_cfg *dma_cfg,
62
-				      u32 dma_tx_phy, u32 chan)
66
+				      dma_addr_t phy, u32 chan)
6367 {
6468 	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
6569 	u32 value;
....@@ -70,7 +74,8 @@
7074 	value |= XGMAC_OSP;
7175 	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
7276 
73
-	writel(dma_tx_phy, ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
77
+	writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
78
+	writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
7479 }
7580 
7681 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
....@@ -91,11 +96,11 @@
9196 	value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
9297 		XGMAC_RD_OSR_LMT;
9398 
99
+	if (!axi->axi_fb)
100
+		value |= XGMAC_UNDEF;
101
+
94102 	value &= ~XGMAC_BLEN;
95103 	for (i = 0; i < AXI_BLEN; i++) {
96
-		if (axi->axi_blen[i])
97
-			value &= ~XGMAC_UNDEF;
98
-
99104 		switch (axi->axi_blen[i]) {
100105 		case 256:
101106 			value |= XGMAC_BLEN256;
....@@ -122,6 +127,16 @@
122127 	}
123128 
124129 	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
130
+	writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL);
131
+	writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL);
132
+}
133
+
134
+static void dwxgmac2_dma_dump_regs(void __iomem *ioaddr, u32 *reg_space)
135
+{
136
+	int i;
137
+
138
+	for (i = (XGMAC_DMA_MODE / 4); i < XGMAC_REGSIZE; i++)
139
+		reg_space[i] = readl(ioaddr + i * 4);
125140 }
126141 
127142 static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
....@@ -146,6 +161,42 @@
146161 
147162 	value &= ~XGMAC_RQS;
148163 	value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
164
+
165
+	if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
166
+		u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
167
+		unsigned int rfd, rfa;
168
+
169
+		value |= XGMAC_EHFC;
170
+
171
+		/* Set Threshold for Activating Flow Control to min 2 frames,
172
+		 * i.e. 1500 * 2 = 3000 bytes.
173
+		 *
174
+		 * Set Threshold for Deactivating Flow Control to min 1 frame,
175
+		 * i.e. 1500 bytes.
176
+		 */
177
+		switch (fifosz) {
178
+		case 4096:
179
+			/* This violates the above formula because of FIFO size
180
+			 * limit therefore overflow may occur in spite of this.
181
+			 */
182
+			rfd = 0x03; /* Full-2.5K */
183
+			rfa = 0x01; /* Full-1.5K */
184
+			break;
185
+
186
+		default:
187
+			rfd = 0x07; /* Full-4.5K */
188
+			rfa = 0x04; /* Full-3K */
189
+			break;
190
+		}
191
+
192
+		flow &= ~XGMAC_RFD;
193
+		flow |= rfd << XGMAC_RFD_SHIFT;
194
+
195
+		flow &= ~XGMAC_RFA;
196
+		flow |= rfa << XGMAC_RFA_SHIFT;
197
+
198
+		writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
199
+	}
149200 
150201 	writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
151202 
....@@ -182,6 +233,9 @@
182233 			value |= 0x7 << XGMAC_TTC_SHIFT;
183234 	}
184235 
236
+	/* Use static TC to Queue mapping */
237
+	value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP;
238
+
185239 	value &= ~XGMAC_TXQEN;
186240 	if (qmode != MTL_QUEUE_AVB)
187241 		value |= 0x2 << XGMAC_TXQEN_SHIFT;
....@@ -194,14 +248,30 @@
194248 	writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
195249 }
196250 
197
-static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan)
251
+static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan,
252
+				    bool rx, bool tx)
198253 {
199
-	writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
254
+	u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
255
+
256
+	if (rx)
257
+		value |= XGMAC_DMA_INT_DEFAULT_RX;
258
+	if (tx)
259
+		value |= XGMAC_DMA_INT_DEFAULT_TX;
260
+
261
+	writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
200262 }
201263 
202
-static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan)
264
+static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan,
265
+				     bool rx, bool tx)
203266 {
204
-	writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
267
+	u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
268
+
269
+	if (rx)
270
+		value &= ~XGMAC_DMA_INT_DEFAULT_RX;
271
+	if (tx)
272
+		value &= ~XGMAC_DMA_INT_DEFAULT_TX;
273
+
274
+	writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
205275 }
206276 
207277 static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)
....@@ -250,10 +320,6 @@
250320 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
251321 	value &= ~XGMAC_RXST;
252322 	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
253
-
254
-	value = readl(ioaddr + XGMAC_RX_CONFIG);
255
-	value &= ~XGMAC_CONFIG_RE;
256
-	writel(value, ioaddr + XGMAC_RX_CONFIG);
257323 }
258324 
259325 static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
....@@ -265,6 +331,10 @@
265331 
266332 	/* ABNORMAL interrupts */
267333 	if (unlikely(intr_status & XGMAC_AIS)) {
334
+		if (unlikely(intr_status & XGMAC_RBU)) {
335
+			x->rx_buf_unav_irq++;
336
+			ret |= handle_rx;
337
+		}
268338 		if (unlikely(intr_status & XGMAC_TPS)) {
269339 			x->tx_process_stopped_irq++;
270340 			ret |= tx_hard_error;
....@@ -280,12 +350,10 @@
280350 		x->normal_irq_n++;
281351 
282352 		if (likely(intr_status & XGMAC_RI)) {
283
-			if (likely(intr_en & XGMAC_RIE)) {
284
-				x->rx_normal_irq_n++;
285
-				ret |= handle_rx;
286
-			}
353
+			x->rx_normal_irq_n++;
354
+			ret |= handle_rx;
287355 		}
288
-		if (likely(intr_status & XGMAC_TI)) {
356
+		if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) {
289357 			x->tx_normal_irq_n++;
290358 			ret |= handle_tx;
291359 		}
....@@ -297,25 +365,51 @@
297365 	return ret;
298366 }
299367 
300
-static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
301
-				    struct dma_features *dma_cap)
368
+static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,
369
+				   struct dma_features *dma_cap)
302370 {
303371 	u32 hw_cap;
304372 
305373 	/*  MAC HW feature 0 */
306374 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
375
+	dma_cap->vlins = (hw_cap & XGMAC_HWFEAT_SAVLANINS) >> 27;
307376 	dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
308377 	dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
378
+	dma_cap->eee = (hw_cap & XGMAC_HWFEAT_EEESEL) >> 13;
309379 	dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
310380 	dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
311
-	dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10;
381
+	dma_cap->av &= !((hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10);
382
+	dma_cap->arpoffsel = (hw_cap & XGMAC_HWFEAT_ARPOFFSEL) >> 9;
383
+	dma_cap->rmon = (hw_cap & XGMAC_HWFEAT_MMCSEL) >> 8;
312384 	dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
313385 	dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
386
+	dma_cap->vlhash = (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4;
314387 	dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;
315388 
316389 	/* MAC HW feature 1 */
317390 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
391
+	dma_cap->l3l4fnum = (hw_cap & XGMAC_HWFEAT_L3L4FNUM) >> 27;
392
+	dma_cap->hash_tb_sz = (hw_cap & XGMAC_HWFEAT_HASHTBLSZ) >> 24;
393
+	dma_cap->rssen = (hw_cap & XGMAC_HWFEAT_RSSEN) >> 20;
318394 	dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
395
+	dma_cap->sphen = (hw_cap & XGMAC_HWFEAT_SPHEN) >> 17;
396
+
397
+	dma_cap->addr64 = (hw_cap & XGMAC_HWFEAT_ADDR64) >> 14;
398
+	switch (dma_cap->addr64) {
399
+	case 0:
400
+		dma_cap->addr64 = 32;
401
+		break;
402
+	case 1:
403
+		dma_cap->addr64 = 40;
404
+		break;
405
+	case 2:
406
+		dma_cap->addr64 = 48;
407
+		break;
408
+	default:
409
+		dma_cap->addr64 = 32;
410
+		break;
411
+	}
412
+
319413 	dma_cap->tx_fifo_size =
320414 		128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
321415 	dma_cap->rx_fifo_size =
....@@ -332,6 +426,21 @@
332426 		((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
333427 	dma_cap->number_rx_queues =
334428 		((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
429
+
430
+	/* MAC HW feature 3 */
431
+	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);
432
+	dma_cap->tbssel = (hw_cap & XGMAC_HWFEAT_TBSSEL) >> 27;
433
+	dma_cap->fpesel = (hw_cap & XGMAC_HWFEAT_FPESEL) >> 26;
434
+	dma_cap->estwid = (hw_cap & XGMAC_HWFEAT_ESTWID) >> 23;
435
+	dma_cap->estdep = (hw_cap & XGMAC_HWFEAT_ESTDEP) >> 20;
436
+	dma_cap->estsel = (hw_cap & XGMAC_HWFEAT_ESTSEL) >> 19;
437
+	dma_cap->asp = (hw_cap & XGMAC_HWFEAT_ASP) >> 14;
438
+	dma_cap->dvlan = (hw_cap & XGMAC_HWFEAT_DVLAN) >> 13;
439
+	dma_cap->frpes = (hw_cap & XGMAC_HWFEAT_FRPES) >> 11;
440
+	dma_cap->frpbs = (hw_cap & XGMAC_HWFEAT_FRPPB) >> 9;
441
+	dma_cap->frpsel = (hw_cap & XGMAC_HWFEAT_FRPSEL) >> 3;
442
+
443
+	return 0;
335444 }
336445 
337446 static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
....@@ -374,6 +483,23 @@
374483 	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
375484 }
376485 
486
+static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
487
+{
488
+	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
489
+	u32 flow = readl(ioaddr + XGMAC_RX_FLOW_CTRL);
490
+
491
+	value &= ~XGMAC_TXQEN;
492
+	if (qmode != MTL_QUEUE_AVB) {
493
+		value |= 0x2 << XGMAC_TXQEN_SHIFT;
494
+		writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
495
+	} else {
496
+		value |= 0x1 << XGMAC_TXQEN_SHIFT;
497
+		writel(flow & (~XGMAC_RFE), ioaddr + XGMAC_RX_FLOW_CTRL);
498
+	}
499
+
500
+	writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
501
+}
502
+
377503 static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
378504 {
379505 	u32 value;
....@@ -384,6 +510,44 @@
384510 	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
385511 }
386512 
513
+static void dwxgmac2_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
514
+{
515
+	u32 value = readl(ioaddr + XGMAC_RX_CONFIG);
516
+
517
+	value &= ~XGMAC_CONFIG_HDSMS;
518
+	value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
519
+	writel(value, ioaddr + XGMAC_RX_CONFIG);
520
+
521
+	value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
522
+	if (en)
523
+		value |= XGMAC_SPH;
524
+	else
525
+		value &= ~XGMAC_SPH;
526
+	writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
527
+}
528
+
529
+static int dwxgmac2_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)
530
+{
531
+	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
532
+
533
+	if (en)
534
+		value |= XGMAC_EDSE;
535
+	else
536
+		value &= ~XGMAC_EDSE;
537
+
538
+	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
539
+
540
+	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE;
541
+	if (en && !value)
542
+		return -EIO;
543
+
544
+	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL0);
545
+	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL1);
546
+	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL2);
547
+	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL3);
548
+	return 0;
549
+}
550
+
387551 const struct stmmac_dma_ops dwxgmac210_dma_ops = {
388552 	.reset = dwxgmac2_dma_reset,
389553 	.init = dwxgmac2_dma_init,
....@@ -391,7 +555,7 @@
391555 	.init_rx_chan = dwxgmac2_dma_init_rx_chan,
392556 	.init_tx_chan = dwxgmac2_dma_init_tx_chan,
393557 	.axi = dwxgmac2_dma_axi,
394
-	.dump_regs = NULL,
558
+	.dump_regs = dwxgmac2_dma_dump_regs,
395559 	.dma_rx_mode = dwxgmac2_dma_rx_mode,
396560 	.dma_tx_mode = dwxgmac2_dma_tx_mode,
397561 	.enable_dma_irq = dwxgmac2_enable_dma_irq,
....@@ -408,5 +572,8 @@
408572 	.set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
409573 	.set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
410574 	.enable_tso = dwxgmac2_enable_tso,
575
+	.qmode = dwxgmac2_qmode,
411576 	.set_bfsize = dwxgmac2_set_bfsize,
577
+	.enable_sph = dwxgmac2_enable_sph,
578
+	.enable_tbs = dwxgmac2_enable_tbs,
412579 };