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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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| 1 | 2 | /******************************************************************************* |
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| 2 | 3 | DWMAC DMA Header file. |
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| 3 | 4 | |
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| 4 | 5 | Copyright (C) 2007-2009 STMicroelectronics Ltd |
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| 5 | 6 | |
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| 6 | | - This program is free software; you can redistribute it and/or modify it |
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| 7 | | - under the terms and conditions of the GNU General Public License, |
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| 8 | | - version 2, as published by the Free Software Foundation. |
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| 9 | | - |
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| 10 | | - This program is distributed in the hope it will be useful, but WITHOUT |
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| 11 | | - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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| 12 | | - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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| 13 | | - more details. |
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| 14 | | - |
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| 15 | | - The full GNU General Public License is included in this distribution in |
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| 16 | | - the file called "COPYING". |
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| 17 | 7 | |
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| 18 | 8 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
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| 19 | 9 | *******************************************************************************/ |
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| .. | .. |
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| 106 | 96 | |
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| 107 | 97 | /* DMA default interrupt mask */ |
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| 108 | 98 | #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL) |
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| 99 | +#define DMA_INTR_DEFAULT_RX (DMA_INTR_ENA_RIE) |
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| 100 | +#define DMA_INTR_DEFAULT_TX (DMA_INTR_ENA_TIE) |
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| 109 | 101 | |
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| 110 | 102 | /* DMA Status register defines */ |
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| 111 | 103 | #define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */ |
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| .. | .. |
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| 138 | 130 | |
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| 139 | 131 | #define NUM_DWMAC100_DMA_REGS 9 |
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| 140 | 132 | #define NUM_DWMAC1000_DMA_REGS 23 |
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| 133 | +#define NUM_DWMAC4_DMA_REGS 27 |
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| 141 | 134 | |
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| 142 | 135 | void dwmac_enable_dma_transmission(void __iomem *ioaddr); |
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| 143 | | -void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan); |
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| 144 | | -void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan); |
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| 136 | +void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx); |
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| 137 | +void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx); |
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| 145 | 138 | void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan); |
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| 146 | 139 | void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan); |
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| 147 | 140 | void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan); |
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