disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
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@@ -1,12 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * DWMAC4 DMA Header file.
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  *
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- *
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  * Copyright (C) 2007-2015  STMicroelectronics Ltd
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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  *
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  * Author: Alexandre Torgue <alexandre.torgue@st.com>
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  */
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@@ -26,6 +22,7 @@
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 #define DMA_DEBUG_STATUS_1		0x00001010
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 #define DMA_DEBUG_STATUS_2		0x00001014
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 #define DMA_AXI_BUS_MODE		0x00001028
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+#define DMA_TBS_CTRL			0x00001050
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 /* DMA Bus Mode bitmap */
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 #define DMA_BUS_MODE_SFT_RESET		BIT(0)
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@@ -69,6 +66,7 @@
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 #define DMA_SYS_BUS_MB			BIT(14)
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 #define DMA_AXI_1KBBE			BIT(13)
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 #define DMA_SYS_BUS_AAL			BIT(12)
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+#define DMA_SYS_BUS_EAME		BIT(11)
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 #define DMA_AXI_BLEN256			BIT(7)
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 #define DMA_AXI_BLEN128			BIT(6)
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 #define DMA_AXI_BLEN64			BIT(5)
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@@ -85,6 +83,11 @@
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 #define DMA_AXI_BURST_LEN_MASK		0x000000FE
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+/* DMA TBS Control */
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+#define DMA_TBS_FTOS			GENMASK(31, 8)
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+#define DMA_TBS_FTOV			BIT(0)
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+#define DMA_TBS_DEF_FTOS		(DMA_TBS_FTOS | DMA_TBS_FTOV)
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+
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 /* Following DMA defines are chanels oriented */
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 #define DMA_CHAN_BASE_ADDR		0x00001100
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 #define DMA_CHAN_BASE_OFFSET		0x80
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@@ -95,7 +98,9 @@
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 #define DMA_CHAN_CONTROL(x)		DMA_CHANX_BASE_ADDR(x)
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 #define DMA_CHAN_TX_CONTROL(x)		(DMA_CHANX_BASE_ADDR(x) + 0x4)
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 #define DMA_CHAN_RX_CONTROL(x)		(DMA_CHANX_BASE_ADDR(x) + 0x8)
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+#define DMA_CHAN_TX_BASE_ADDR_HI(x)	(DMA_CHANX_BASE_ADDR(x) + 0x10)
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 #define DMA_CHAN_TX_BASE_ADDR(x)	(DMA_CHANX_BASE_ADDR(x) + 0x14)
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+#define DMA_CHAN_RX_BASE_ADDR_HI(x)	(DMA_CHANX_BASE_ADDR(x) + 0x18)
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 #define DMA_CHAN_RX_BASE_ADDR(x)	(DMA_CHANX_BASE_ADDR(x) + 0x1c)
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 #define DMA_CHAN_TX_END_ADDR(x)		(DMA_CHANX_BASE_ADDR(x) + 0x20)
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 #define DMA_CHAN_RX_END_ADDR(x)		(DMA_CHANX_BASE_ADDR(x) + 0x28)
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@@ -111,9 +116,11 @@
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 #define DMA_CHAN_STATUS(x)		(DMA_CHANX_BASE_ADDR(x) + 0x60)
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 /* DMA Control X */
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+#define DMA_CONTROL_SPH			BIT(24)
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 #define DMA_CONTROL_MSS_MASK		GENMASK(13, 0)
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 /* DMA Tx Channel X Control register defines */
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+#define DMA_CONTROL_EDSE		BIT(28)
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 #define DMA_CONTROL_TSE			BIT(12)
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 #define DMA_CONTROL_OSP			BIT(4)
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 #define DMA_CONTROL_ST			BIT(0)
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@@ -168,6 +175,8 @@
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 /* DMA default interrupt mask for 4.00 */
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 #define DMA_CHAN_INTR_DEFAULT_MASK	(DMA_CHAN_INTR_NORMAL | \
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 					 DMA_CHAN_INTR_ABNORMAL)
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+#define DMA_CHAN_INTR_DEFAULT_RX	(DMA_CHAN_INTR_ENA_RIE)
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+#define DMA_CHAN_INTR_DEFAULT_TX	(DMA_CHAN_INTR_ENA_TIE)
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 #define DMA_CHAN_INTR_NORMAL_4_10	(DMA_CHAN_INTR_ENA_NIE_4_10 | \
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 					 DMA_CHAN_INTR_ENA_RIE | \
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@@ -178,6 +187,8 @@
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 /* DMA default interrupt mask for 4.10a */
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 #define DMA_CHAN_INTR_DEFAULT_MASK_4_10	(DMA_CHAN_INTR_NORMAL_4_10 | \
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 					 DMA_CHAN_INTR_ABNORMAL_4_10)
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+#define DMA_CHAN_INTR_DEFAULT_RX_4_10	(DMA_CHAN_INTR_ENA_RIE)
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+#define DMA_CHAN_INTR_DEFAULT_TX_4_10	(DMA_CHAN_INTR_ENA_TIE)
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 /* channel 0 specific fields */
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 #define DMA_CHAN0_DBG_STAT_TPS		GENMASK(15, 12)
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@@ -186,9 +197,10 @@
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 #define DMA_CHAN0_DBG_STAT_RPS_SHIFT	8
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 int dwmac4_dma_reset(void __iomem *ioaddr);
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-void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan);
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-void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan);
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-void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan);
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+void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
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+void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
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+void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
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+void dwmac410_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
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 void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan);
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 void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan);
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 void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan);