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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /******************************************************************************* |
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| 2 | 3 | This is the driver for the MAC 10/100 on-chip Ethernet controller |
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| 3 | 4 | currently tested on all the ST boards based on STb7109 and stx7200 SoCs. |
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| .. | .. |
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| 9 | 10 | |
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| 10 | 11 | Copyright (C) 2007-2009 STMicroelectronics Ltd |
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| 11 | 12 | |
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| 12 | | - This program is free software; you can redistribute it and/or modify it |
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| 13 | | - under the terms and conditions of the GNU General Public License, |
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| 14 | | - version 2, as published by the Free Software Foundation. |
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| 15 | | - |
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| 16 | | - This program is distributed in the hope it will be useful, but WITHOUT |
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| 17 | | - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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| 18 | | - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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| 19 | | - more details. |
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| 20 | | - |
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| 21 | | - The full GNU General Public License is included in this distribution in |
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| 22 | | - the file called "COPYING". |
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| 23 | 13 | |
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| 24 | 14 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
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| 25 | 15 | *******************************************************************************/ |
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| .. | .. |
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| 41 | 31 | |
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| 42 | 32 | static void dwmac100_dma_init_rx(void __iomem *ioaddr, |
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| 43 | 33 | struct stmmac_dma_cfg *dma_cfg, |
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| 44 | | - u32 dma_rx_phy, u32 chan) |
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| 34 | + dma_addr_t dma_rx_phy, u32 chan) |
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| 45 | 35 | { |
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| 46 | 36 | /* RX descriptor base addr lists must be written into DMA CSR3 */ |
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| 47 | | - writel(dma_rx_phy, ioaddr + DMA_RCV_BASE_ADDR); |
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| 37 | + writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR); |
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| 48 | 38 | } |
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| 49 | 39 | |
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| 50 | 40 | static void dwmac100_dma_init_tx(void __iomem *ioaddr, |
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| 51 | 41 | struct stmmac_dma_cfg *dma_cfg, |
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| 52 | | - u32 dma_tx_phy, u32 chan) |
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| 42 | + dma_addr_t dma_tx_phy, u32 chan) |
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| 53 | 43 | { |
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| 54 | 44 | /* TX descriptor base addr lists must be written into DMA CSR4 */ |
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| 55 | | - writel(dma_tx_phy, ioaddr + DMA_TX_BASE_ADDR); |
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| 45 | + writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR); |
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| 56 | 46 | } |
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| 57 | 47 | |
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| 58 | 48 | /* Store and Forward capability is not used at all. |
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