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2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
..
..
@@ -1,10 +1,9 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
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  *
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  * Copyright (C) STMicroelectronics SA 2017
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  * Author:  Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
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- * License terms:  GNU General Public License (GPL), version 2
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- *
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  */
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8
 
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 #include <linux/clk.h>
..
..
@@ -25,9 +24,29 @@
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24
 
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 #define SYSCFG_MCU_ETH_MASK		BIT(23)
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 #define SYSCFG_MP1_ETH_MASK		GENMASK(23, 16)
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+#define SYSCFG_PMCCLRR_OFFSET		0x40
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28
 
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 #define SYSCFG_PMCR_ETH_CLK_SEL		BIT(16)
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 #define SYSCFG_PMCR_ETH_REF_CLK_SEL	BIT(17)
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+
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+/* CLOCK feed to PHY*/
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+#define ETH_CK_F_25M	25000000
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+#define ETH_CK_F_50M	50000000
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+#define ETH_CK_F_125M	125000000
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+
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+/*  Ethernet PHY interface selection in register SYSCFG Configuration
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+ *------------------------------------------
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+ * src	 |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
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+ *------------------------------------------
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+ * MII   |   0	 |   0	  |   0    |   1   |
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+ *------------------------------------------
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+ * GMII  |   0	 |   0	  |   0    |   0   |
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+ *------------------------------------------
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+ * RGMII |   0	 |   0	  |   1	   |  n/a  |
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+ *------------------------------------------
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+ * RMII  |   1	 |   0	  |   0	   |  n/a  |
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+ *------------------------------------------
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+ */
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 #define SYSCFG_PMCR_ETH_SEL_MII		BIT(20)
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 #define SYSCFG_PMCR_ETH_SEL_RGMII	BIT(21)
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 #define SYSCFG_PMCR_ETH_SEL_RMII	BIT(23)
..
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@@ -35,14 +54,43 @@
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 #define SYSCFG_MCU_ETH_SEL_MII		0
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 #define SYSCFG_MCU_ETH_SEL_RMII		1
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56
 
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+/* STM32MP1 register definitions
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+ *
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+ * Below table summarizes the clock requirement and clock sources for
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+ * supported phy interface modes.
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+ * __________________________________________________________________________
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+ *|PHY_MODE | Normal | PHY wo crystal|   PHY wo crystal   |No 125Mhz from PHY|
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+ *|         |        |      25MHz    |        50MHz       |                  |
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+ * ---------------------------------------------------------------------------
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+ *|  MII    |	 -   |     eth-ck    |	      n/a	  |	  n/a        |
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+ *|         |        | st,ext-phyclk |                    |		     |
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+ * ---------------------------------------------------------------------------
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+ *|  GMII   |	 -   |     eth-ck    |	      n/a	  |	  n/a        |
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+ *|         |        | st,ext-phyclk |                    |		     |
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+ * ---------------------------------------------------------------------------
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+ *| RGMII   |	 -   |     eth-ck    |	      n/a	  |      eth-ck      |
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+ *|         |        | st,ext-phyclk |                    | st,eth-clk-sel or|
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+ *|         |        |               |                    | st,ext-phyclk    |
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+ * ---------------------------------------------------------------------------
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+ *| RMII    |	 -   |     eth-ck    |	    eth-ck        |	  n/a        |
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+ *|         |        | st,ext-phyclk | st,eth-ref-clk-sel |		     |
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+ *|         |        |               | or st,ext-phyclk   |		     |
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+ * ---------------------------------------------------------------------------
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+ *
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+ */
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+
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 struct stm32_dwmac {
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 	struct clk *clk_tx;
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 	struct clk *clk_rx;
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 	struct clk *clk_eth_ck;
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 	struct clk *clk_ethstp;
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 	struct clk *syscfg_clk;
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-	bool int_phyclk;	/* Clock from RCC to drive PHY */
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-	u32 mode_reg;		/* MAC glue-logic mode register */
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+	int ext_phyclk;
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+	int enable_eth_ck;
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+	int eth_clk_sel_reg;
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+	int eth_ref_clk_sel_reg;
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+	int irq_pwr_wakeup;
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+	u32 mode_reg;		 /* MAC glue-logic mode register */
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 	struct regmap *regmap;
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 	u32 speed;
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96
 	const struct stm32_ops *ops;
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@@ -57,6 +105,7 @@
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105
 	int (*parse_data)(struct stm32_dwmac *dwmac,
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106
 			  struct device *dev);
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107
 	u32 syscfg_eth_mask;
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+	bool clk_rx_enable_in_suspend;
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109
 };
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110
 
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111
 static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
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@@ -74,7 +123,8 @@
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123
 	if (ret)
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124
 		return ret;
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125
 
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-	if (!dwmac->dev->power.is_suspended) {
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+	if (!dwmac->ops->clk_rx_enable_in_suspend ||
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+	    !dwmac->dev->power.is_suspended) {
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128
 		ret = clk_prepare_enable(dwmac->clk_rx);
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129
 		if (ret) {
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130
 			clk_disable_unprepare(dwmac->clk_tx);
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@@ -101,8 +151,7 @@
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 		ret = clk_prepare_enable(dwmac->syscfg_clk);
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 		if (ret)
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 			return ret;
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-
105
-		if (dwmac->int_phyclk) {
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+		if (dwmac->enable_eth_ck) {
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 			ret = clk_prepare_enable(dwmac->clk_eth_ck);
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156
 			if (ret) {
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 				clk_disable_unprepare(dwmac->syscfg_clk);
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@@ -111,7 +160,7 @@
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160
 		}
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 	} else {
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 		clk_disable_unprepare(dwmac->syscfg_clk);
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-		if (dwmac->int_phyclk)
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+		if (dwmac->enable_eth_ck)
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 			clk_disable_unprepare(dwmac->clk_eth_ck);
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165
 	}
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 	return ret;
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@@ -120,30 +169,46 @@
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169
 static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
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170
 {
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 	struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
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-	u32 reg = dwmac->mode_reg;
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+	u32 reg = dwmac->mode_reg, clk_rate;
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173
 	int val;
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174
 
175
+	clk_rate = clk_get_rate(dwmac->clk_eth_ck);
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+	dwmac->enable_eth_ck = false;
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177
 	switch (plat_dat->interface) {
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178
 	case PHY_INTERFACE_MODE_MII:
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+		if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk)
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+			dwmac->enable_eth_ck = true;
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 		val = SYSCFG_PMCR_ETH_SEL_MII;
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182
 		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
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183
 		break;
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184
 	case PHY_INTERFACE_MODE_GMII:
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 		val = SYSCFG_PMCR_ETH_SEL_GMII;
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-		if (dwmac->int_phyclk)
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+		if (clk_rate == ETH_CK_F_25M &&
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+		    (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
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+			dwmac->enable_eth_ck = true;
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 			val |= SYSCFG_PMCR_ETH_CLK_SEL;
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+		}
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 		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
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 		break;
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 	case PHY_INTERFACE_MODE_RMII:
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 		val = SYSCFG_PMCR_ETH_SEL_RMII;
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-		if (dwmac->int_phyclk)
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+		if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) &&
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+		    (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) {
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+			dwmac->enable_eth_ck = true;
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 			val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
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+		}
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 		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
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 		break;
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 	case PHY_INTERFACE_MODE_RGMII:
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+	case PHY_INTERFACE_MODE_RGMII_ID:
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+	case PHY_INTERFACE_MODE_RGMII_RXID:
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+	case PHY_INTERFACE_MODE_RGMII_TXID:
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 		val = SYSCFG_PMCR_ETH_SEL_RGMII;
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-		if (dwmac->int_phyclk)
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+		if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) &&
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+		    (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
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+			dwmac->enable_eth_ck = true;
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 			val |= SYSCFG_PMCR_ETH_CLK_SEL;
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+		}
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 		pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
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 		break;
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 	default:
..
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@@ -153,6 +218,11 @@
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 		return -EINVAL;
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 	}
155
220
 
221
+	/* Need to update PMCCLRR (clear register) */
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+	regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
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+		     dwmac->ops->syscfg_eth_mask);
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+
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+	/* Update PMCSETR (set register) */
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 	return regmap_update_bits(dwmac->regmap, reg,
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227
 				 dwmac->ops->syscfg_eth_mask, val);
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228
 }
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@@ -180,7 +250,7 @@
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 	}
181
251
 
182
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 	return regmap_update_bits(dwmac->regmap, reg,
183
-				 dwmac->ops->syscfg_eth_mask, val);
253
+				 dwmac->ops->syscfg_eth_mask, val << 23);
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254
 }
185
255
 
186
256
 static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)
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@@ -232,35 +302,63 @@
232
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 static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
233
303
 			       struct device *dev)
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304
 {
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+	struct platform_device *pdev = to_platform_device(dev);
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 	struct device_node *np = dev->of_node;
307
+	int err = 0;
236
308
 
237
-	dwmac->int_phyclk = of_property_read_bool(np, "st,int-phyclk");
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+	/* Ethernet PHY have no crystal */
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+	dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
238
311
 
239
-	/* Check if internal clk from RCC selected */
240
-	if (dwmac->int_phyclk) {
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-		/*  Get ETH_CLK clocks */
242
-		dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck");
243
-		if (IS_ERR(dwmac->clk_eth_ck)) {
244
-			dev_err(dev, "No ETH CK clock provided...\n");
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-			return PTR_ERR(dwmac->clk_eth_ck);
246
-		}
312
+	/* Gigabit Ethernet 125MHz clock selection. */
313
+	dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel");
314
+
315
+	/* Ethernet 50Mhz RMII clock selection */
316
+	dwmac->eth_ref_clk_sel_reg =
317
+		of_property_read_bool(np, "st,eth-ref-clk-sel");
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+
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+	/*  Get ETH_CLK clocks */
320
+	dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck");
321
+	if (IS_ERR(dwmac->clk_eth_ck)) {
322
+		dev_info(dev, "No phy clock provided...\n");
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+		dwmac->clk_eth_ck = NULL;
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324
 	}
248
325
 
249
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 	/*  Clock used for low power mode */
250
327
 	dwmac->clk_ethstp = devm_clk_get(dev, "ethstp");
251
328
 	if (IS_ERR(dwmac->clk_ethstp)) {
252
-		dev_err(dev, "No ETH peripheral clock provided for CStop mode ...\n");
329
+		dev_err(dev,
330
+			"No ETH peripheral clock provided for CStop mode ...\n");
253
331
 		return PTR_ERR(dwmac->clk_ethstp);
254
332
 	}
255
333
 
256
-	/*  Clock for sysconfig */
334
+	/*  Optional Clock for sysconfig */
257
335
 	dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
258
-	if (IS_ERR(dwmac->syscfg_clk)) {
259
-		dev_err(dev, "No syscfg clock provided...\n");
260
-		return PTR_ERR(dwmac->syscfg_clk);
261
-	}
336
+	if (IS_ERR(dwmac->syscfg_clk))
337
+		dwmac->syscfg_clk = NULL;
262
338
 
263
-	return 0;
339
+	/* Get IRQ information early to have an ability to ask for deferred
340
+	 * probe if needed before we went too far with resource allocation.
341
+	 */
342
+	dwmac->irq_pwr_wakeup = platform_get_irq_byname_optional(pdev,
343
+							"stm32_pwr_wakeup");
344
+	if (dwmac->irq_pwr_wakeup == -EPROBE_DEFER)
345
+		return -EPROBE_DEFER;
346
+
347
+	if (!dwmac->clk_eth_ck && dwmac->irq_pwr_wakeup >= 0) {
348
+		err = device_init_wakeup(&pdev->dev, true);
349
+		if (err) {
350
+			dev_err(&pdev->dev, "Failed to init wake up irq\n");
351
+			return err;
352
+		}
353
+		err = dev_pm_set_dedicated_wake_irq(&pdev->dev,
354
+						    dwmac->irq_pwr_wakeup);
355
+		if (err) {
356
+			dev_err(&pdev->dev, "Failed to set wake up irq\n");
357
+			device_init_wakeup(&pdev->dev, false);
358
+		}
359
+		device_set_wakeup_enable(&pdev->dev, false);
360
+	}
361
+	return err;
264
362
 }
265
363
 
266
364
 static int stm32_dwmac_probe(struct platform_device *pdev)
..
..
@@ -326,8 +424,14 @@
326
424
 	struct net_device *ndev = platform_get_drvdata(pdev);
327
425
 	struct stmmac_priv *priv = netdev_priv(ndev);
328
426
 	int ret = stmmac_dvr_remove(&pdev->dev);
427
+	struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
329
428
 
330
429
 	stm32_dwmac_clk_disable(priv->plat->bsp_priv);
430
+
431
+	if (dwmac->irq_pwr_wakeup >= 0) {
432
+		dev_pm_clear_wake_irq(&pdev->dev);
433
+		device_init_wakeup(&pdev->dev, false);
434
+	}
331
435
 
332
436
 	return ret;
333
437
 }
..
..
@@ -342,7 +446,7 @@
342
446
 
343
447
 	clk_disable_unprepare(dwmac->clk_tx);
344
448
 	clk_disable_unprepare(dwmac->syscfg_clk);
345
-	if (dwmac->int_phyclk)
449
+	if (dwmac->enable_eth_ck)
346
450
 		clk_disable_unprepare(dwmac->clk_eth_ck);
347
451
 
348
452
 	return ret;
..
..
@@ -413,7 +517,8 @@
413
517
 	.suspend = stm32mp1_suspend,
414
518
 	.resume = stm32mp1_resume,
415
519
 	.parse_data = stm32mp1_parse_data,
416
-	.syscfg_eth_mask = SYSCFG_MP1_ETH_MASK
520
+	.syscfg_eth_mask = SYSCFG_MP1_ETH_MASK,
521
+	.clk_rx_enable_in_suspend = true
417
522
 };
418
523
 
419
524
 static const struct of_device_id stm32_dwmac_match[] = {