forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk-tool.c
....@@ -9,6 +9,7 @@
99 #include <linux/if_ether.h>
1010 #include <linux/if.h>
1111 #include <linux/dma-mapping.h>
12
+#include <linux/of_device.h>
1213 #include <linux/slab.h>
1314 #include <linux/prefetch.h>
1415 #include <linux/regmap.h>
....@@ -85,6 +86,7 @@
8586 	int rx;
8687 	int final_tx;
8788 	int final_rx;
89
+	int max_delay;
8890 };
8991 
9092 #define DMA_CONTROL_OSP		BIT(4)
....@@ -99,6 +101,7 @@
99101 
100102 #define	STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
101103 #define MAX_DELAYLINE 0x7f
104
+#define RK3588_MAX_DELAYLINE 0xc7
102105 #define SCAN_STEP 0x5
103106 #define SCAN_VALID_RANGE 0xA
104107 
....@@ -119,7 +122,8 @@
119122 	.size = 1024,
120123 };
121124 
122
-static int dwmac_rk_enable_mac_loopback(struct stmmac_priv *priv, int speed)
125
+static int dwmac_rk_enable_mac_loopback(struct stmmac_priv *priv, int speed,
126
+					int addr, bool phy)
123127 {
124128 	u32 ctrl;
125129 	int phy_val;
....@@ -128,25 +132,30 @@
128132 	ctrl &= ~priv->hw->link.speed_mask;
129133 	ctrl |= GMAC_CONTROL_LM;
130134 
131
-	phy_val = mdiobus_read(priv->mii, priv->plat->phy_addr, MII_BMCR);
135
+	if (phy)
136
+		phy_val = mdiobus_read(priv->mii, addr, MII_BMCR);
132137 
133138 	switch (speed) {
134139 	case LOOPBACK_SPEED1000:
135140 		ctrl |= priv->hw->link.speed1000;
136
-		phy_val |= BMCR_ANENABLE;
137
-		phy_val |= BMCR_SPEED1000;
141
+		if (phy) {
142
+			phy_val &= ~BMCR_SPEED100;
143
+			phy_val |= BMCR_SPEED1000;
144
+		}
138145 		break;
139146 	case LOOPBACK_SPEED100:
140147 		ctrl |= priv->hw->link.speed100;
141
-		phy_val &= ~BMCR_ANENABLE;
142
-		phy_val &= ~BMCR_SPEED1000;
143
-		phy_val |= BMCR_SPEED100;
148
+		if (phy) {
149
+			phy_val &= ~BMCR_SPEED1000;
150
+			phy_val |= BMCR_SPEED100;
151
+		}
144152 		break;
145153 	case LOOPBACK_SPEED10:
146154 		ctrl |= priv->hw->link.speed10;
147
-		phy_val &= ~BMCR_ANENABLE;
148
-		phy_val &= ~BMCR_SPEED1000;
149
-		phy_val &= ~BMCR_SPEED100;
155
+		if (phy) {
156
+			phy_val &= ~BMCR_SPEED1000;
157
+			phy_val &= ~BMCR_SPEED100;
158
+		}
150159 		break;
151160 	default:
152161 		return -EPERM;
....@@ -155,9 +164,14 @@
155164 	ctrl |= priv->hw->link.duplex;
156165 	writel(ctrl, priv->ioaddr + GMAC_CONTROL);
157166 
158
-	phy_val |= BMCR_FULLDPLX;
159
-	mdiobus_write(priv->mii, priv->plat->phy_addr, MII_BMCR, phy_val);
160
-	phy_val = mdiobus_read(priv->mii, priv->plat->phy_addr, MII_BMCR);
167
+	if (phy) {
168
+		phy_val &= ~BMCR_PDOWN;
169
+		phy_val &= ~BMCR_ANENABLE;
170
+		phy_val &= ~BMCR_PDOWN;
171
+		phy_val |= BMCR_FULLDPLX;
172
+		mdiobus_write(priv->mii, addr, MII_BMCR, phy_val);
173
+		phy_val = mdiobus_read(priv->mii, addr, MII_BMCR);
174
+	}
161175 
162176 	if (likely(priv->plat->fix_mac_speed))
163177 		priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
....@@ -165,7 +179,7 @@
165179 	return 0;
166180 }
167181 
168
-static int dwmac_rk_disable_mac_loopback(struct stmmac_priv *priv)
182
+static int dwmac_rk_disable_mac_loopback(struct stmmac_priv *priv, int addr)
169183 {
170184 	u32 ctrl;
171185 	int phy_val;
....@@ -174,25 +188,27 @@
174188 	ctrl &= ~GMAC_CONTROL_LM;
175189 	writel(ctrl, priv->ioaddr + GMAC_CONTROL);
176190 
177
-	phy_val = mdiobus_read(priv->mii, priv->plat->phy_addr, MII_BMCR);
191
+	phy_val = mdiobus_read(priv->mii, addr, MII_BMCR);
178192 	phy_val |= BMCR_ANENABLE;
179193 
180
-	mdiobus_write(priv->mii, priv->plat->phy_addr, MII_BMCR, phy_val);
181
-	phy_val = mdiobus_read(priv->mii, priv->plat->phy_addr, MII_BMCR);
194
+	mdiobus_write(priv->mii, addr, MII_BMCR, phy_val);
195
+	phy_val = mdiobus_read(priv->mii, addr, MII_BMCR);
182196 
183197 	return 0;
184198 }
185199 
186200 static int dwmac_rk_set_mac_loopback(struct stmmac_priv *priv,
187
-				     int speed, bool enable)
201
+				     int speed, bool enable,
202
+				     int addr, bool phy)
188203 {
189204 	if (enable)
190
-		return dwmac_rk_enable_mac_loopback(priv, speed);
205
+		return dwmac_rk_enable_mac_loopback(priv, speed, addr, phy);
191206 	else
192
-		return dwmac_rk_disable_mac_loopback(priv);
207
+		return dwmac_rk_disable_mac_loopback(priv, addr);
193208 }
194209 
195
-static int dwmac_rk_enable_phy_loopback(struct stmmac_priv *priv, int speed)
210
+static int dwmac_rk_enable_phy_loopback(struct stmmac_priv *priv, int speed,
211
+					int addr, bool phy)
196212 {
197213 	u32 ctrl;
198214 	int val;
....@@ -200,25 +216,30 @@
200216 	ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
201217 	ctrl &= ~priv->hw->link.speed_mask;
202218 
203
-	val = mdiobus_read(priv->mii, 0, MII_BMCR);
204
-
205
-	val &= ~BMCR_ANENABLE;
206
-	val |= BMCR_LOOPBACK;
219
+	if (phy)
220
+		val = mdiobus_read(priv->mii, addr, MII_BMCR);
207221 
208222 	switch (speed) {
209223 	case LOOPBACK_SPEED1000:
210224 		ctrl |= priv->hw->link.speed1000;
211
-		val |= BMCR_SPEED1000;
225
+		if (phy) {
226
+			val &= ~BMCR_SPEED100;
227
+			val |= BMCR_SPEED1000;
228
+		}
212229 		break;
213230 	case LOOPBACK_SPEED100:
214231 		ctrl |= priv->hw->link.speed100;
215
-		val &= ~BMCR_SPEED1000;
216
-		val |= BMCR_SPEED100;
232
+		if (phy) {
233
+			val &= ~BMCR_SPEED1000;
234
+			val |= BMCR_SPEED100;
235
+		}
217236 		break;
218237 	case LOOPBACK_SPEED10:
219238 		ctrl |= priv->hw->link.speed10;
220
-		val &= ~BMCR_SPEED1000;
221
-		val &= ~BMCR_SPEED100;
239
+		if (phy) {
240
+			val &= ~BMCR_SPEED1000;
241
+			val &= ~BMCR_SPEED100;
242
+		}
222243 		break;
223244 	default:
224245 		return -EPERM;
....@@ -227,9 +248,14 @@
227248 	ctrl |= priv->hw->link.duplex;
228249 	writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
229250 
230
-	val |= BMCR_FULLDPLX;
231
-	mdiobus_write(priv->mii, 0, MII_BMCR, val);
232
-	val = mdiobus_read(priv->mii, 0, MII_BMCR);
251
+	if (phy) {
252
+		val |= BMCR_FULLDPLX;
253
+		val &= ~BMCR_PDOWN;
254
+		val &= ~BMCR_ANENABLE;
255
+		val |= BMCR_LOOPBACK;
256
+		mdiobus_write(priv->mii, addr, MII_BMCR, val);
257
+		val = mdiobus_read(priv->mii, addr, MII_BMCR);
258
+	}
233259 
234260 	if (likely(priv->plat->fix_mac_speed))
235261 		priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
....@@ -237,40 +263,43 @@
237263 	return 0;
238264 }
239265 
240
-static int dwmac_rk_disable_phy_loopback(struct stmmac_priv *priv)
266
+static int dwmac_rk_disable_phy_loopback(struct stmmac_priv *priv, int addr)
241267 {
242268 	int val;
243269 
244
-	val = mdiobus_read(priv->mii, 0, MII_BMCR);
270
+	val = mdiobus_read(priv->mii, addr, MII_BMCR);
245271 	val |= BMCR_ANENABLE;
246272 	val &= ~BMCR_LOOPBACK;
247273 
248
-	mdiobus_write(priv->mii, 0, MII_BMCR, val);
249
-	val = mdiobus_read(priv->mii, priv->plat->phy_addr, MII_BMCR);
274
+	mdiobus_write(priv->mii, addr, MII_BMCR, val);
275
+	val = mdiobus_read(priv->mii, addr, MII_BMCR);
250276 
251277 	return 0;
252278 }
253279 
254280 static int dwmac_rk_set_phy_loopback(struct stmmac_priv *priv,
255
-				     int speed, bool enable)
281
+				     int speed, bool enable,
282
+				     int addr, bool phy)
256283 {
257284 	if (enable)
258
-		return dwmac_rk_enable_phy_loopback(priv, speed);
285
+		return dwmac_rk_enable_phy_loopback(priv, speed,
286
+						     addr, phy);
259287 	else
260
-		return dwmac_rk_disable_phy_loopback(priv);
288
+		return dwmac_rk_disable_phy_loopback(priv, addr);
261289 }
262290 
263291 static int dwmac_rk_set_loopback(struct stmmac_priv *priv,
264
-				 int type, int speed, bool enable)
292
+				 int type, int speed, bool enable,
293
+				 int addr, bool phy)
265294 {
266295 	int ret;
267296 
268297 	switch (type) {
269298 	case LOOPBACK_TYPE_PHY:
270
-		ret = dwmac_rk_set_phy_loopback(priv, speed, enable);
299
+		ret = dwmac_rk_set_phy_loopback(priv, speed, enable, addr, phy);
271300 		break;
272301 	case LOOPBACK_TYPE_GMAC:
273
-		ret = dwmac_rk_set_mac_loopback(priv, speed, enable);
302
+		ret = dwmac_rk_set_mac_loopback(priv, speed, enable, addr, phy);
274303 		break;
275304 	default:
276305 		ret = -EOPNOTSUPP;
....@@ -776,9 +805,20 @@
776805 	return __dwmac_rk_loopback_run(priv, lb_priv);
777806 }
778807 
779
-static inline bool dwmac_rk_delayline_is_valid(int tx, int rx)
808
+static inline bool dwmac_rk_delayline_is_txvalid(struct dwmac_rk_lb_priv *lb_priv,
809
+						 int tx)
780810 {
781
-	if ((tx > 0 && tx < MAX_DELAYLINE) && (rx > 0 && rx < MAX_DELAYLINE))
811
+	if (tx > 0 && tx < lb_priv->max_delay)
812
+		return true;
813
+	else
814
+		return false;
815
+}
816
+
817
+static inline bool dwmac_rk_delayline_is_valid(struct dwmac_rk_lb_priv *lb_priv,
818
+					       int tx, int rx)
819
+{
820
+	if ((tx > 0 && tx < lb_priv->max_delay) &&
821
+	    (rx > 0 && rx < lb_priv->max_delay))
782822 		return true;
783823 	else
784824 		return false;
....@@ -789,7 +829,7 @@
789829 {
790830 	int tx_left, tx_right, rx_up, rx_down;
791831 	int i, j, tx_index, rx_index;
792
-	int tx_mid, rx_mid;
832
+	int tx_mid = 0, rx_mid = 0;
793833 
794834 	/* initiation */
795835 	tx_index = SCAN_STEP;
....@@ -797,12 +837,12 @@
797837 
798838 re_scan:
799839 	/* start from rx based on the experience */
800
-	for (i = rx_index; i <= (MAX_DELAYLINE - SCAN_STEP); i += SCAN_STEP) {
840
+	for (i = rx_index; i <= (lb_priv->max_delay - SCAN_STEP); i += SCAN_STEP) {
801841 		tx_left = 0;
802842 		tx_right = 0;
803843 		tx_mid = 0;
804844 
805
-		for (j = tx_index; j <= (MAX_DELAYLINE - SCAN_STEP);
845
+		for (j = tx_index; j <= (lb_priv->max_delay - SCAN_STEP);
806846 		     j += SCAN_STEP) {
807847 			if (!dwmac_rk_loopback_with_identify(priv,
808848 			    lb_priv, j, i)) {
....@@ -820,14 +860,14 @@
820860 	}
821861 
822862 	/* Worst case: reach the end */
823
-	if (i >= (MAX_DELAYLINE - SCAN_STEP))
863
+	if (i >= (lb_priv->max_delay - SCAN_STEP))
824864 		goto end;
825865 
826866 	rx_up = 0;
827867 	rx_down = 0;
828868 
829869 	/* look for rx_mid base on the tx_mid */
830
-	for (i = SCAN_STEP; i <= (MAX_DELAYLINE - SCAN_STEP);
870
+	for (i = SCAN_STEP; i <= (lb_priv->max_delay - SCAN_STEP);
831871 	     i += SCAN_STEP) {
832872 		if (!dwmac_rk_loopback_with_identify(priv, lb_priv,
833873 		    tx_mid, i)) {
....@@ -846,23 +886,24 @@
846886 		goto re_scan;
847887 	}
848888 
849
-	if (dwmac_rk_delayline_is_valid(tx_mid, rx_mid)) {
889
+	if (dwmac_rk_delayline_is_valid(lb_priv, tx_mid, rx_mid)) {
850890 		lb_priv->final_tx = tx_mid;
851891 		lb_priv->final_rx = rx_mid;
852892 
853
-		pr_info("Find suitable tx_delay = 0x%02x, rx_delay = 0x%02x\n",
893
+		pr_info("Find available tx_delay = 0x%02x, rx_delay = 0x%02x\n",
854894 			lb_priv->final_tx, lb_priv->final_rx);
855895 
856896 		return 0;
857897 	}
858898 end:
859
-	pr_err("Can't find suitable delayline\n");
899
+	pr_err("Can't find available delayline\n");
860900 	return -ENXIO;
861901 }
862902 
863903 static int dwmac_rk_delayline_scan(struct stmmac_priv *priv,
864904 				   struct dwmac_rk_lb_priv *lb_priv)
865905 {
906
+	int phy_iface = dwmac_rk_get_phy_interface(priv);
866907 	int tx, rx, tx_sum, rx_sum, count;
867908 	int tx_mid, rx_mid;
868909 	int ret = -ENXIO;
....@@ -871,9 +912,11 @@
871912 	rx_sum = 0;
872913 	count = 0;
873914 
874
-	for (rx = 0x0; rx <= MAX_DELAYLINE; rx++) {
875
-		printk(KERN_CONT "RX(0x%02x):", rx);
876
-		for (tx = 0x0; tx <= MAX_DELAYLINE; tx++) {
915
+	for (rx = 0x0; rx <= lb_priv->max_delay; rx++) {
916
+		if (phy_iface == PHY_INTERFACE_MODE_RGMII_RXID)
917
+			rx = -1;
918
+		printk(KERN_CONT "RX(%03d):", rx);
919
+		for (tx = 0x0; tx <= lb_priv->max_delay; tx++) {
877920 			if (!dwmac_rk_loopback_with_identify(priv,
878921 			    lb_priv, tx, rx)) {
879922 				tx_sum += tx;
....@@ -885,24 +928,40 @@
885928 			}
886929 		}
887930 		printk(KERN_CONT "\n");
931
+
932
+		if (phy_iface == PHY_INTERFACE_MODE_RGMII_RXID)
933
+			break;
888934 	}
889935 
890936 	if (tx_sum && rx_sum && count) {
891937 		tx_mid = tx_sum / count;
892938 		rx_mid = rx_sum / count;
893939 
894
-		if (dwmac_rk_delayline_is_valid(tx_mid, rx_mid)) {
895
-			lb_priv->final_tx = tx_mid;
896
-			lb_priv->final_rx = rx_mid;
897
-			ret = 0;
940
+		if (phy_iface == PHY_INTERFACE_MODE_RGMII_RXID) {
941
+			if (dwmac_rk_delayline_is_txvalid(lb_priv, tx_mid)) {
942
+				lb_priv->final_tx = tx_mid;
943
+				lb_priv->final_rx = -1;
944
+				ret = 0;
945
+			}
946
+		} else {
947
+			if (dwmac_rk_delayline_is_valid(lb_priv, tx_mid, rx_mid)) {
948
+				lb_priv->final_tx = tx_mid;
949
+				lb_priv->final_rx = rx_mid;
950
+				ret = 0;
951
+			}
898952 		}
899953 	}
900954 
901
-	if (ret)
955
+	if (ret) {
902956 		pr_err("\nCan't find suitable delayline\n");
903
-	else
904
-		pr_info("\nFind suitable tx_delay = 0x%02x, rx_delay = 0x%02x\n",
905
-			lb_priv->final_tx, lb_priv->final_rx);
957
+	} else {
958
+		if (phy_iface == PHY_INTERFACE_MODE_RGMII_RXID)
959
+			pr_info("Find available tx_delay = 0x%02x, rx_delay = disable\n",
960
+				lb_priv->final_tx);
961
+		else
962
+			pr_info("\nFind suitable tx_delay = 0x%02x, rx_delay = 0x%02x\n",
963
+				lb_priv->final_tx, lb_priv->final_rx);
964
+	}
906965 
907966 	return ret;
908967 }
....@@ -974,17 +1033,17 @@
9741033 	int ret = -ENOMEM;
9751034 
9761035 	/* desc dma map */
977
-	lb_priv->dma_rx = dma_zalloc_coherent(priv->device,
978
-					      sizeof(struct dma_desc),
979
-					      &lb_priv->dma_rx_phy,
980
-					      GFP_KERNEL);
1036
+	lb_priv->dma_rx = dma_alloc_coherent(priv->device,
1037
+					     sizeof(struct dma_desc),
1038
+					     &lb_priv->dma_rx_phy,
1039
+					     GFP_KERNEL);
9811040 	if (!lb_priv->dma_rx)
9821041 		return ret;
9831042 
984
-	lb_priv->dma_tx = dma_zalloc_coherent(priv->device,
985
-					      sizeof(struct dma_desc),
986
-					      &lb_priv->dma_tx_phy,
987
-					      GFP_KERNEL);
1043
+	lb_priv->dma_tx = dma_alloc_coherent(priv->device,
1044
+					     sizeof(struct dma_desc),
1045
+					     &lb_priv->dma_tx_phy,
1046
+					     GFP_KERNEL);
9881047 	if (!lb_priv->dma_tx) {
9891048 		dma_free_coherent(priv->device,
9901049 				  sizeof(struct dma_desc),
....@@ -1095,6 +1154,54 @@
10951154 	}
10961155 }
10971156 
1157
+static void dwmac_rk_rx_queue_dma_chan_map(struct stmmac_priv *priv)
1158
+{
1159
+	u32 rx_queues_count = min_t(u32, priv->plat->rx_queues_to_use, 1);
1160
+	u32 queue;
1161
+	u32 chan;
1162
+
1163
+	for (queue = 0; queue < rx_queues_count; queue++) {
1164
+		chan = priv->plat->rx_queues_cfg[queue].chan;
1165
+		stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
1166
+	}
1167
+}
1168
+
1169
+static void dwmac_rk_mac_enable_rx_queues(struct stmmac_priv *priv)
1170
+{
1171
+	u32 rx_queues_count = min_t(u32, priv->plat->rx_queues_to_use, 1);
1172
+	int queue;
1173
+	u8 mode;
1174
+
1175
+	for (queue = 0; queue < rx_queues_count; queue++) {
1176
+		mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1177
+		stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1178
+	}
1179
+}
1180
+
1181
+static void dwmac_rk_mtl_configuration(struct stmmac_priv *priv)
1182
+{
1183
+	/* Map RX MTL to DMA channels */
1184
+	dwmac_rk_rx_queue_dma_chan_map(priv);
1185
+
1186
+	/* Enable MAC RX Queues */
1187
+	dwmac_rk_mac_enable_rx_queues(priv);
1188
+}
1189
+
1190
+static void dwmac_rk_mmc_setup(struct stmmac_priv *priv)
1191
+{
1192
+	unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1193
+			    MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1194
+
1195
+	stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
1196
+
1197
+	if (priv->dma_cap.rmon) {
1198
+		stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
1199
+		memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1200
+	} else {
1201
+		netdev_info(priv->dev, "No MAC Management Counters available\n");
1202
+	}
1203
+}
1204
+
10981205 static int dwmac_rk_init(struct net_device *dev,
10991206 			 struct dwmac_rk_lb_priv *lb_priv)
11001207 {
....@@ -1134,6 +1241,10 @@
11341241 	/* Initialize the MAC Core */
11351242 	stmmac_core_init(priv, priv->hw, dev);
11361243 
1244
+	dwmac_rk_mtl_configuration(priv);
1245
+
1246
+	dwmac_rk_mmc_setup(priv);
1247
+
11371248 	ret = priv->hw->mac->rx_ipc(priv->hw);
11381249 	if (!ret) {
11391250 		pr_warn(" RX IPC Checksum Offload disabled\n");
....@@ -1155,7 +1266,7 @@
11551266 		writel((mode & ~DMA_CONTROL_OSF), priv->ioaddr + DMA_CONTROL);
11561267 	}
11571268 
1158
-	stmmac_enable_dma_irq(priv, priv->ioaddr, 0);
1269
+	stmmac_enable_dma_irq(priv, priv->ioaddr, 0, 1, 1);
11591270 
11601271 	if (priv->hw->pcs)
11611272 		stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
....@@ -1172,10 +1283,41 @@
11721283 {
11731284 	struct stmmac_priv *priv = netdev_priv(dev);
11741285 
1175
-	stmmac_disable_dma_irq(priv, priv->ioaddr, 0);
1286
+	stmmac_disable_dma_irq(priv, priv->ioaddr, 0, 0, 0);
11761287 
11771288 	/* Release and free the Rx/Tx resources */
11781289 	dwmac_rk_free_dma_desc_resources(priv, lb_priv);
1290
+}
1291
+
1292
+static int dwmac_rk_get_max_delayline(struct stmmac_priv *priv)
1293
+{
1294
+	if (of_device_is_compatible(priv->device->of_node,
1295
+				    "rockchip,rk3588-gmac"))
1296
+		return RK3588_MAX_DELAYLINE;
1297
+	else
1298
+		return MAX_DELAYLINE;
1299
+}
1300
+
1301
+static int dwmac_rk_phy_poll_reset(struct stmmac_priv *priv, int addr)
1302
+{
1303
+	/* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
1304
+	unsigned int val, retries = 12;
1305
+	int ret;
1306
+
1307
+	val = mdiobus_read(priv->mii, addr, MII_BMCR);
1308
+	mdiobus_write(priv->mii, addr, MII_BMCR, val | BMCR_RESET);
1309
+
1310
+	do {
1311
+		msleep(50);
1312
+		ret = mdiobus_read(priv->mii, addr, MII_BMCR);
1313
+		if (ret < 0)
1314
+			return ret;
1315
+	} while (ret & BMCR_RESET && --retries);
1316
+	if (ret & BMCR_RESET)
1317
+		return -ETIMEDOUT;
1318
+
1319
+	msleep(1);
1320
+	return 0;
11791321 }
11801322 
11811323 static int dwmac_rk_loopback_run(struct stmmac_priv *priv,
....@@ -1183,11 +1325,14 @@
11831325 {
11841326 	struct net_device *ndev = priv->dev;
11851327 	int phy_iface = dwmac_rk_get_phy_interface(priv);
1186
-	int ndev_up;
1328
+	int ndev_up, phy_addr;
11871329 	int ret = -EINVAL;
11881330 
11891331 	if (!ndev || !priv->mii)
11901332 		return -EINVAL;
1333
+
1334
+	phy_addr = priv->dev->phydev->mdio.addr;
1335
+	lb_priv->max_delay = dwmac_rk_get_max_delayline(priv);
11911336 
11921337 	rtnl_lock();
11931338 	/* check the netdevice up or not */
....@@ -1211,25 +1356,29 @@
12111356 
12121357 		if (priv->plat->stmmac_rst)
12131358 			reset_control_assert(priv->plat->stmmac_rst);
1214
-
1215
-		if (priv->mii)
1216
-			priv->mii->reset(priv->mii);
1217
-
1359
+		dwmac_rk_phy_poll_reset(priv, phy_addr);
12181360 		if (priv->plat->stmmac_rst)
12191361 			reset_control_deassert(priv->plat->stmmac_rst);
12201362 	}
12211363 	/* wait for phy and controller ready */
12221364 	usleep_range(100000, 200000);
12231365 
1366
+	dwmac_rk_set_loopback(priv, lb_priv->type, lb_priv->speed,
1367
+			      true, phy_addr, true);
1368
+
12241369 	ret = dwmac_rk_init(ndev, lb_priv);
12251370 	if (ret)
12261371 		goto exit_init;
1227
-	dwmac_rk_set_loopback(priv, lb_priv->type, lb_priv->speed, true);
1372
+
1373
+	dwmac_rk_set_loopback(priv, lb_priv->type, lb_priv->speed,
1374
+			      true, phy_addr, false);
12281375 
12291376 	if (lb_priv->scan) {
12301377 		/* scan only support for rgmii mode */
12311378 		if (phy_iface != PHY_INTERFACE_MODE_RGMII &&
1232
-		    phy_iface != PHY_INTERFACE_MODE_RGMII_ID) {
1379
+		    phy_iface != PHY_INTERFACE_MODE_RGMII_ID &&
1380
+		    phy_iface != PHY_INTERFACE_MODE_RGMII_RXID &&
1381
+		    phy_iface != PHY_INTERFACE_MODE_RGMII_TXID) {
12331382 			ret = -EINVAL;
12341383 			goto out;
12351384 		}
....@@ -1245,8 +1394,8 @@
12451394 
12461395 out:
12471396 	dwmac_rk_release(ndev, lb_priv);
1248
-	dwmac_rk_set_loopback(priv, lb_priv->type, lb_priv->speed, false);
1249
-
1397
+	dwmac_rk_set_loopback(priv, lb_priv->type, lb_priv->speed,
1398
+			      false, phy_addr, false);
12501399 exit_init:
12511400 	if (ndev_up)
12521401 		ndev->netdev_ops->ndo_open(ndev);
....@@ -1291,10 +1440,10 @@
12911440 	*data = 0;
12921441 	data++;
12931442 
1294
-	if (kstrtoint(tmp, 0, &tx) || tx > MAX_DELAYLINE)
1443
+	if (kstrtoint(tmp, 0, &tx) || tx > dwmac_rk_get_max_delayline(priv))
12951444 		goto out;
12961445 
1297
-	if (kstrtoint(data, 0, &rx) || rx > MAX_DELAYLINE)
1446
+	if (kstrtoint(data, 0, &rx) || rx > dwmac_rk_get_max_delayline(priv))
12981447 		goto out;
12991448 
13001449 	dwmac_rk_set_rgmii_delayline(priv, tx, rx);