forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk-tool.c
....@@ -9,6 +9,7 @@
99 #include <linux/if_ether.h>
1010 #include <linux/if.h>
1111 #include <linux/dma-mapping.h>
12
+#include <linux/of_device.h>
1213 #include <linux/slab.h>
1314 #include <linux/prefetch.h>
1415 #include <linux/regmap.h>
....@@ -100,6 +101,7 @@
100101 
101102 #define	STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
102103 #define MAX_DELAYLINE 0x7f
104
+#define RK3588_MAX_DELAYLINE 0xc7
103105 #define SCAN_STEP 0x5
104106 #define SCAN_VALID_RANGE 0xA
105107 
....@@ -120,7 +122,8 @@
120122 	.size = 1024,
121123 };
122124 
123
-static int dwmac_rk_enable_mac_loopback(struct stmmac_priv *priv, int speed)
125
+static int dwmac_rk_enable_mac_loopback(struct stmmac_priv *priv, int speed,
126
+					int addr, bool phy)
124127 {
125128 	u32 ctrl;
126129 	int phy_val;
....@@ -129,25 +132,30 @@
129132 	ctrl &= ~priv->hw->link.speed_mask;
130133 	ctrl |= GMAC_CONTROL_LM;
131134 
132
-	phy_val = mdiobus_read(priv->mii, priv->plat->phy_addr, MII_BMCR);
135
+	if (phy)
136
+		phy_val = mdiobus_read(priv->mii, addr, MII_BMCR);
133137 
134138 	switch (speed) {
135139 	case LOOPBACK_SPEED1000:
136140 		ctrl |= priv->hw->link.speed1000;
137
-		phy_val |= BMCR_ANENABLE;
138
-		phy_val |= BMCR_SPEED1000;
141
+		if (phy) {
142
+			phy_val &= ~BMCR_SPEED100;
143
+			phy_val |= BMCR_SPEED1000;
144
+		}
139145 		break;
140146 	case LOOPBACK_SPEED100:
141147 		ctrl |= priv->hw->link.speed100;
142
-		phy_val &= ~BMCR_ANENABLE;
143
-		phy_val &= ~BMCR_SPEED1000;
144
-		phy_val |= BMCR_SPEED100;
148
+		if (phy) {
149
+			phy_val &= ~BMCR_SPEED1000;
150
+			phy_val |= BMCR_SPEED100;
151
+		}
145152 		break;
146153 	case LOOPBACK_SPEED10:
147154 		ctrl |= priv->hw->link.speed10;
148
-		phy_val &= ~BMCR_ANENABLE;
149
-		phy_val &= ~BMCR_SPEED1000;
150
-		phy_val &= ~BMCR_SPEED100;
155
+		if (phy) {
156
+			phy_val &= ~BMCR_SPEED1000;
157
+			phy_val &= ~BMCR_SPEED100;
158
+		}
151159 		break;
152160 	default:
153161 		return -EPERM;
....@@ -156,9 +164,14 @@
156164 	ctrl |= priv->hw->link.duplex;
157165 	writel(ctrl, priv->ioaddr + GMAC_CONTROL);
158166 
159
-	phy_val |= BMCR_FULLDPLX;
160
-	mdiobus_write(priv->mii, priv->plat->phy_addr, MII_BMCR, phy_val);
161
-	phy_val = mdiobus_read(priv->mii, priv->plat->phy_addr, MII_BMCR);
167
+	if (phy) {
168
+		phy_val &= ~BMCR_PDOWN;
169
+		phy_val &= ~BMCR_ANENABLE;
170
+		phy_val &= ~BMCR_PDOWN;
171
+		phy_val |= BMCR_FULLDPLX;
172
+		mdiobus_write(priv->mii, addr, MII_BMCR, phy_val);
173
+		phy_val = mdiobus_read(priv->mii, addr, MII_BMCR);
174
+	}
162175 
163176 	if (likely(priv->plat->fix_mac_speed))
164177 		priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
....@@ -166,7 +179,7 @@
166179 	return 0;
167180 }
168181 
169
-static int dwmac_rk_disable_mac_loopback(struct stmmac_priv *priv)
182
+static int dwmac_rk_disable_mac_loopback(struct stmmac_priv *priv, int addr)
170183 {
171184 	u32 ctrl;
172185 	int phy_val;
....@@ -175,25 +188,27 @@
175188 	ctrl &= ~GMAC_CONTROL_LM;
176189 	writel(ctrl, priv->ioaddr + GMAC_CONTROL);
177190 
178
-	phy_val = mdiobus_read(priv->mii, priv->plat->phy_addr, MII_BMCR);
191
+	phy_val = mdiobus_read(priv->mii, addr, MII_BMCR);
179192 	phy_val |= BMCR_ANENABLE;
180193 
181
-	mdiobus_write(priv->mii, priv->plat->phy_addr, MII_BMCR, phy_val);
182
-	phy_val = mdiobus_read(priv->mii, priv->plat->phy_addr, MII_BMCR);
194
+	mdiobus_write(priv->mii, addr, MII_BMCR, phy_val);
195
+	phy_val = mdiobus_read(priv->mii, addr, MII_BMCR);
183196 
184197 	return 0;
185198 }
186199 
187200 static int dwmac_rk_set_mac_loopback(struct stmmac_priv *priv,
188
-				     int speed, bool enable)
201
+				     int speed, bool enable,
202
+				     int addr, bool phy)
189203 {
190204 	if (enable)
191
-		return dwmac_rk_enable_mac_loopback(priv, speed);
205
+		return dwmac_rk_enable_mac_loopback(priv, speed, addr, phy);
192206 	else
193
-		return dwmac_rk_disable_mac_loopback(priv);
207
+		return dwmac_rk_disable_mac_loopback(priv, addr);
194208 }
195209 
196
-static int dwmac_rk_enable_phy_loopback(struct stmmac_priv *priv, int speed)
210
+static int dwmac_rk_enable_phy_loopback(struct stmmac_priv *priv, int speed,
211
+					int addr, bool phy)
197212 {
198213 	u32 ctrl;
199214 	int val;
....@@ -201,25 +216,30 @@
201216 	ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
202217 	ctrl &= ~priv->hw->link.speed_mask;
203218 
204
-	val = mdiobus_read(priv->mii, 0, MII_BMCR);
205
-
206
-	val &= ~BMCR_ANENABLE;
207
-	val |= BMCR_LOOPBACK;
219
+	if (phy)
220
+		val = mdiobus_read(priv->mii, addr, MII_BMCR);
208221 
209222 	switch (speed) {
210223 	case LOOPBACK_SPEED1000:
211224 		ctrl |= priv->hw->link.speed1000;
212
-		val |= BMCR_SPEED1000;
225
+		if (phy) {
226
+			val &= ~BMCR_SPEED100;
227
+			val |= BMCR_SPEED1000;
228
+		}
213229 		break;
214230 	case LOOPBACK_SPEED100:
215231 		ctrl |= priv->hw->link.speed100;
216
-		val &= ~BMCR_SPEED1000;
217
-		val |= BMCR_SPEED100;
232
+		if (phy) {
233
+			val &= ~BMCR_SPEED1000;
234
+			val |= BMCR_SPEED100;
235
+		}
218236 		break;
219237 	case LOOPBACK_SPEED10:
220238 		ctrl |= priv->hw->link.speed10;
221
-		val &= ~BMCR_SPEED1000;
222
-		val &= ~BMCR_SPEED100;
239
+		if (phy) {
240
+			val &= ~BMCR_SPEED1000;
241
+			val &= ~BMCR_SPEED100;
242
+		}
223243 		break;
224244 	default:
225245 		return -EPERM;
....@@ -228,9 +248,14 @@
228248 	ctrl |= priv->hw->link.duplex;
229249 	writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
230250 
231
-	val |= BMCR_FULLDPLX;
232
-	mdiobus_write(priv->mii, 0, MII_BMCR, val);
233
-	val = mdiobus_read(priv->mii, 0, MII_BMCR);
251
+	if (phy) {
252
+		val |= BMCR_FULLDPLX;
253
+		val &= ~BMCR_PDOWN;
254
+		val &= ~BMCR_ANENABLE;
255
+		val |= BMCR_LOOPBACK;
256
+		mdiobus_write(priv->mii, addr, MII_BMCR, val);
257
+		val = mdiobus_read(priv->mii, addr, MII_BMCR);
258
+	}
234259 
235260 	if (likely(priv->plat->fix_mac_speed))
236261 		priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
....@@ -238,40 +263,43 @@
238263 	return 0;
239264 }
240265 
241
-static int dwmac_rk_disable_phy_loopback(struct stmmac_priv *priv)
266
+static int dwmac_rk_disable_phy_loopback(struct stmmac_priv *priv, int addr)
242267 {
243268 	int val;
244269 
245
-	val = mdiobus_read(priv->mii, 0, MII_BMCR);
270
+	val = mdiobus_read(priv->mii, addr, MII_BMCR);
246271 	val |= BMCR_ANENABLE;
247272 	val &= ~BMCR_LOOPBACK;
248273 
249
-	mdiobus_write(priv->mii, 0, MII_BMCR, val);
250
-	val = mdiobus_read(priv->mii, priv->plat->phy_addr, MII_BMCR);
274
+	mdiobus_write(priv->mii, addr, MII_BMCR, val);
275
+	val = mdiobus_read(priv->mii, addr, MII_BMCR);
251276 
252277 	return 0;
253278 }
254279 
255280 static int dwmac_rk_set_phy_loopback(struct stmmac_priv *priv,
256
-				     int speed, bool enable)
281
+				     int speed, bool enable,
282
+				     int addr, bool phy)
257283 {
258284 	if (enable)
259
-		return dwmac_rk_enable_phy_loopback(priv, speed);
285
+		return dwmac_rk_enable_phy_loopback(priv, speed,
286
+						     addr, phy);
260287 	else
261
-		return dwmac_rk_disable_phy_loopback(priv);
288
+		return dwmac_rk_disable_phy_loopback(priv, addr);
262289 }
263290 
264291 static int dwmac_rk_set_loopback(struct stmmac_priv *priv,
265
-				 int type, int speed, bool enable)
292
+				 int type, int speed, bool enable,
293
+				 int addr, bool phy)
266294 {
267295 	int ret;
268296 
269297 	switch (type) {
270298 	case LOOPBACK_TYPE_PHY:
271
-		ret = dwmac_rk_set_phy_loopback(priv, speed, enable);
299
+		ret = dwmac_rk_set_phy_loopback(priv, speed, enable, addr, phy);
272300 		break;
273301 	case LOOPBACK_TYPE_GMAC:
274
-		ret = dwmac_rk_set_mac_loopback(priv, speed, enable);
302
+		ret = dwmac_rk_set_mac_loopback(priv, speed, enable, addr, phy);
275303 		break;
276304 	default:
277305 		ret = -EOPNOTSUPP;
....@@ -1005,17 +1033,17 @@
10051033 	int ret = -ENOMEM;
10061034 
10071035 	/* desc dma map */
1008
-	lb_priv->dma_rx = dma_zalloc_coherent(priv->device,
1009
-					      sizeof(struct dma_desc),
1010
-					      &lb_priv->dma_rx_phy,
1011
-					      GFP_KERNEL);
1036
+	lb_priv->dma_rx = dma_alloc_coherent(priv->device,
1037
+					     sizeof(struct dma_desc),
1038
+					     &lb_priv->dma_rx_phy,
1039
+					     GFP_KERNEL);
10121040 	if (!lb_priv->dma_rx)
10131041 		return ret;
10141042 
1015
-	lb_priv->dma_tx = dma_zalloc_coherent(priv->device,
1016
-					      sizeof(struct dma_desc),
1017
-					      &lb_priv->dma_tx_phy,
1018
-					      GFP_KERNEL);
1043
+	lb_priv->dma_tx = dma_alloc_coherent(priv->device,
1044
+					     sizeof(struct dma_desc),
1045
+					     &lb_priv->dma_tx_phy,
1046
+					     GFP_KERNEL);
10191047 	if (!lb_priv->dma_tx) {
10201048 		dma_free_coherent(priv->device,
10211049 				  sizeof(struct dma_desc),
....@@ -1126,6 +1154,54 @@
11261154 	}
11271155 }
11281156 
1157
+static void dwmac_rk_rx_queue_dma_chan_map(struct stmmac_priv *priv)
1158
+{
1159
+	u32 rx_queues_count = min_t(u32, priv->plat->rx_queues_to_use, 1);
1160
+	u32 queue;
1161
+	u32 chan;
1162
+
1163
+	for (queue = 0; queue < rx_queues_count; queue++) {
1164
+		chan = priv->plat->rx_queues_cfg[queue].chan;
1165
+		stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
1166
+	}
1167
+}
1168
+
1169
+static void dwmac_rk_mac_enable_rx_queues(struct stmmac_priv *priv)
1170
+{
1171
+	u32 rx_queues_count = min_t(u32, priv->plat->rx_queues_to_use, 1);
1172
+	int queue;
1173
+	u8 mode;
1174
+
1175
+	for (queue = 0; queue < rx_queues_count; queue++) {
1176
+		mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1177
+		stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1178
+	}
1179
+}
1180
+
1181
+static void dwmac_rk_mtl_configuration(struct stmmac_priv *priv)
1182
+{
1183
+	/* Map RX MTL to DMA channels */
1184
+	dwmac_rk_rx_queue_dma_chan_map(priv);
1185
+
1186
+	/* Enable MAC RX Queues */
1187
+	dwmac_rk_mac_enable_rx_queues(priv);
1188
+}
1189
+
1190
+static void dwmac_rk_mmc_setup(struct stmmac_priv *priv)
1191
+{
1192
+	unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1193
+			    MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1194
+
1195
+	stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
1196
+
1197
+	if (priv->dma_cap.rmon) {
1198
+		stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
1199
+		memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1200
+	} else {
1201
+		netdev_info(priv->dev, "No MAC Management Counters available\n");
1202
+	}
1203
+}
1204
+
11291205 static int dwmac_rk_init(struct net_device *dev,
11301206 			 struct dwmac_rk_lb_priv *lb_priv)
11311207 {
....@@ -1165,6 +1241,10 @@
11651241 	/* Initialize the MAC Core */
11661242 	stmmac_core_init(priv, priv->hw, dev);
11671243 
1244
+	dwmac_rk_mtl_configuration(priv);
1245
+
1246
+	dwmac_rk_mmc_setup(priv);
1247
+
11681248 	ret = priv->hw->mac->rx_ipc(priv->hw);
11691249 	if (!ret) {
11701250 		pr_warn(" RX IPC Checksum Offload disabled\n");
....@@ -1186,7 +1266,7 @@
11861266 		writel((mode & ~DMA_CONTROL_OSF), priv->ioaddr + DMA_CONTROL);
11871267 	}
11881268 
1189
-	stmmac_enable_dma_irq(priv, priv->ioaddr, 0);
1269
+	stmmac_enable_dma_irq(priv, priv->ioaddr, 0, 1, 1);
11901270 
11911271 	if (priv->hw->pcs)
11921272 		stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
....@@ -1203,7 +1283,7 @@
12031283 {
12041284 	struct stmmac_priv *priv = netdev_priv(dev);
12051285 
1206
-	stmmac_disable_dma_irq(priv, priv->ioaddr, 0);
1286
+	stmmac_disable_dma_irq(priv, priv->ioaddr, 0, 0, 0);
12071287 
12081288 	/* Release and free the Rx/Tx resources */
12091289 	dwmac_rk_free_dma_desc_resources(priv, lb_priv);
....@@ -1211,7 +1291,33 @@
12111291 
12121292 static int dwmac_rk_get_max_delayline(struct stmmac_priv *priv)
12131293 {
1214
-	return MAX_DELAYLINE;
1294
+	if (of_device_is_compatible(priv->device->of_node,
1295
+				    "rockchip,rk3588-gmac"))
1296
+		return RK3588_MAX_DELAYLINE;
1297
+	else
1298
+		return MAX_DELAYLINE;
1299
+}
1300
+
1301
+static int dwmac_rk_phy_poll_reset(struct stmmac_priv *priv, int addr)
1302
+{
1303
+	/* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
1304
+	unsigned int val, retries = 12;
1305
+	int ret;
1306
+
1307
+	val = mdiobus_read(priv->mii, addr, MII_BMCR);
1308
+	mdiobus_write(priv->mii, addr, MII_BMCR, val | BMCR_RESET);
1309
+
1310
+	do {
1311
+		msleep(50);
1312
+		ret = mdiobus_read(priv->mii, addr, MII_BMCR);
1313
+		if (ret < 0)
1314
+			return ret;
1315
+	} while (ret & BMCR_RESET && --retries);
1316
+	if (ret & BMCR_RESET)
1317
+		return -ETIMEDOUT;
1318
+
1319
+	msleep(1);
1320
+	return 0;
12151321 }
12161322 
12171323 static int dwmac_rk_loopback_run(struct stmmac_priv *priv,
....@@ -1219,12 +1325,13 @@
12191325 {
12201326 	struct net_device *ndev = priv->dev;
12211327 	int phy_iface = dwmac_rk_get_phy_interface(priv);
1222
-	int ndev_up;
1328
+	int ndev_up, phy_addr;
12231329 	int ret = -EINVAL;
12241330 
12251331 	if (!ndev || !priv->mii)
12261332 		return -EINVAL;
12271333 
1334
+	phy_addr = priv->dev->phydev->mdio.addr;
12281335 	lb_priv->max_delay = dwmac_rk_get_max_delayline(priv);
12291336 
12301337 	rtnl_lock();
....@@ -1249,20 +1356,22 @@
12491356 
12501357 		if (priv->plat->stmmac_rst)
12511358 			reset_control_assert(priv->plat->stmmac_rst);
1252
-
1253
-		if (priv->mii)
1254
-			priv->mii->reset(priv->mii);
1255
-
1359
+		dwmac_rk_phy_poll_reset(priv, phy_addr);
12561360 		if (priv->plat->stmmac_rst)
12571361 			reset_control_deassert(priv->plat->stmmac_rst);
12581362 	}
12591363 	/* wait for phy and controller ready */
12601364 	usleep_range(100000, 200000);
12611365 
1366
+	dwmac_rk_set_loopback(priv, lb_priv->type, lb_priv->speed,
1367
+			      true, phy_addr, true);
1368
+
12621369 	ret = dwmac_rk_init(ndev, lb_priv);
12631370 	if (ret)
12641371 		goto exit_init;
1265
-	dwmac_rk_set_loopback(priv, lb_priv->type, lb_priv->speed, true);
1372
+
1373
+	dwmac_rk_set_loopback(priv, lb_priv->type, lb_priv->speed,
1374
+			      true, phy_addr, false);
12661375 
12671376 	if (lb_priv->scan) {
12681377 		/* scan only support for rgmii mode */
....@@ -1285,8 +1394,8 @@
12851394 
12861395 out:
12871396 	dwmac_rk_release(ndev, lb_priv);
1288
-	dwmac_rk_set_loopback(priv, lb_priv->type, lb_priv->speed, false);
1289
-
1397
+	dwmac_rk_set_loopback(priv, lb_priv->type, lb_priv->speed,
1398
+			      false, phy_addr, false);
12901399 exit_init:
12911400 	if (ndev_up)
12921401 		ndev->netdev_ops->ndo_open(ndev);