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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
....@@ -1,16 +1,11 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
34  *
45  * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
9
- *
10
- * You should have received a copy of the GNU General Public License
11
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
126  */
137 
8
+#include <linux/bitfield.h>
149 #include <linux/clk.h>
1510 #include <linux/clk-provider.h>
1611 #include <linux/device.h>
....@@ -37,7 +32,10 @@
3732 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
3833 #define PRG_ETH0_CLK_M250_SEL_MASK	GENMASK(4, 4)
3934 
40
-#define PRG_ETH0_TXDLY_SHIFT		5
35
+/* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
36
+ * cycle of the 125MHz RGMII TX clock):
37
+ * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
38
+ */
4139 #define PRG_ETH0_TXDLY_MASK		GENMASK(6, 5)
4240 
4341 /* divider for the result of m250_sel */
....@@ -49,7 +47,26 @@
4947 #define PRG_ETH0_INVERTED_RMII_CLK	BIT(11)
5048 #define PRG_ETH0_TX_AND_PHY_REF_CLK	BIT(12)
5149 
52
-#define MUX_CLK_NUM_PARENTS		2
50
+/* Bypass (= 0, the signal from the GPIO input directly connects to the
51
+ * internal sampling) or enable (= 1) the internal logic for RXEN and RXD[3:0]
52
+ * timing tuning.
53
+ */
54
+#define PRG_ETH0_ADJ_ENABLE		BIT(13)
55
+/* Controls whether the RXEN and RXD[3:0] signals should be aligned with the
56
+ * input RX rising/falling edge and sent to the Ethernet internals. This sets
57
+ * the automatically delay and skew automatically (internally).
58
+ */
59
+#define PRG_ETH0_ADJ_SETUP		BIT(14)
60
+/* An internal counter based on the "timing-adjustment" clock. The counter is
61
+ * cleared on both, the falling and rising edge of the RX_CLK. This selects the
62
+ * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
63
+ */
64
+#define PRG_ETH0_ADJ_DELAY		GENMASK(19, 15)
65
+/* Adjusts the skew between each bit of RXEN and RXD[3:0]. If a signal has a
66
+ * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67
+ * ...) can be configured to be 1 to compensate for a delay of about 1ns.
68
+ */
69
+#define PRG_ETH0_ADJ_SKEW		GENMASK(24, 20)
5370 
5471 struct meson8b_dwmac;
5572 
....@@ -65,6 +82,8 @@
6582 	phy_interface_t			phy_mode;
6683 	struct clk			*rgmii_tx_clk;
6784 	u32				tx_delay_ns;
85
+	u32				rx_delay_ns;
86
+	struct clk			*timing_adj_clk;
6887 };
6988 
7089 struct meson8b_dwmac_clk_configs {
....@@ -88,12 +107,12 @@
88107 
89108 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
90109 					      const char *name_suffix,
91
-					      const char **parent_names,
110
+					      const struct clk_parent_data *parents,
92111 					      int num_parents,
93112 					      const struct clk_ops *ops,
94113 					      struct clk_hw *hw)
95114 {
96
-	struct clk_init_data init;
115
+	struct clk_init_data init = { };
97116 	char clk_name[32];
98117 
99118 	snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev),
....@@ -102,7 +121,7 @@
102121 	init.name = clk_name;
103122 	init.ops = ops;
104123 	init.flags = CLK_SET_RATE_PARENT;
105
-	init.parent_names = parent_names;
124
+	init.parent_data = parents;
106125 	init.num_parents = num_parents;
107126 
108127 	hw->init = &init;
....@@ -112,11 +131,12 @@
112131 
113132 static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
114133 {
115
-	int i, ret;
116134 	struct clk *clk;
117135 	struct device *dev = dwmac->dev;
118
-	const char *parent_name, *mux_parent_names[MUX_CLK_NUM_PARENTS];
119
-	struct meson8b_dwmac_clk_configs *clk_configs;
136
+	static const struct clk_parent_data mux_parents[] = {
137
+		{ .fw_name = "clkin0", },
138
+		{ .index = -1, },
139
+	};
120140 	static const struct clk_div_table div_table[] = {
121141 		{ .div = 2, .val = 2, },
122142 		{ .div = 3, .val = 3, },
....@@ -126,63 +146,49 @@
126146 		{ .div = 7, .val = 7, },
127147 		{ /* end of array */ }
128148 	};
149
+	struct meson8b_dwmac_clk_configs *clk_configs;
150
+	struct clk_parent_data parent_data = { };
129151 
130152 	clk_configs = devm_kzalloc(dev, sizeof(*clk_configs), GFP_KERNEL);
131153 	if (!clk_configs)
132154 		return -ENOMEM;
133155 
134
-	/* get the mux parents from DT */
135
-	for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
136
-		char name[16];
137
-
138
-		snprintf(name, sizeof(name), "clkin%d", i);
139
-		clk = devm_clk_get(dev, name);
140
-		if (IS_ERR(clk)) {
141
-			ret = PTR_ERR(clk);
142
-			if (ret != -EPROBE_DEFER)
143
-				dev_err(dev, "Missing clock %s\n", name);
144
-			return ret;
145
-		}
146
-
147
-		mux_parent_names[i] = __clk_get_name(clk);
148
-	}
149
-
150156 	clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
151157 	clk_configs->m250_mux.shift = __ffs(PRG_ETH0_CLK_M250_SEL_MASK);
152158 	clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK >>
153159 				     clk_configs->m250_mux.shift;
154
-	clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parent_names,
155
-					 MUX_CLK_NUM_PARENTS, &clk_mux_ops,
160
+	clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parents,
161
+					 ARRAY_SIZE(mux_parents), &clk_mux_ops,
156162 					 &clk_configs->m250_mux.hw);
157163 	if (WARN_ON(IS_ERR(clk)))
158164 		return PTR_ERR(clk);
159165 
160
-	parent_name = __clk_get_name(clk);
166
+	parent_data.hw = &clk_configs->m250_mux.hw;
161167 	clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0;
162168 	clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT;
163169 	clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH;
164170 	clk_configs->m250_div.table = div_table;
165171 	clk_configs->m250_div.flags = CLK_DIVIDER_ALLOW_ZERO |
166172 				      CLK_DIVIDER_ROUND_CLOSEST;
167
-	clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_name, 1,
173
+	clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_data, 1,
168174 					 &clk_divider_ops,
169175 					 &clk_configs->m250_div.hw);
170176 	if (WARN_ON(IS_ERR(clk)))
171177 		return PTR_ERR(clk);
172178 
173
-	parent_name = __clk_get_name(clk);
179
+	parent_data.hw = &clk_configs->m250_div.hw;
174180 	clk_configs->fixed_div2.mult = 1;
175181 	clk_configs->fixed_div2.div = 2;
176
-	clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_name, 1,
182
+	clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_data, 1,
177183 					 &clk_fixed_factor_ops,
178184 					 &clk_configs->fixed_div2.hw);
179185 	if (WARN_ON(IS_ERR(clk)))
180186 		return PTR_ERR(clk);
181187 
182
-	parent_name = __clk_get_name(clk);
188
+	parent_data.hw = &clk_configs->fixed_div2.hw;
183189 	clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;
184190 	clk_configs->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN;
185
-	clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_name, 1,
191
+	clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_data, 1,
186192 					 &clk_gate_ops,
187193 					 &clk_configs->rgmii_tx_en.hw);
188194 	if (WARN_ON(IS_ERR(clk)))
....@@ -246,29 +252,79 @@
246252 	return 0;
247253 }
248254 
249
-static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
255
+static int meson8b_devm_clk_prepare_enable(struct meson8b_dwmac *dwmac,
256
+					   struct clk *clk)
250257 {
251258 	int ret;
252
-	u8 tx_dly_val = 0;
259
+
260
+	ret = clk_prepare_enable(clk);
261
+	if (ret)
262
+		return ret;
263
+
264
+	return devm_add_action_or_reset(dwmac->dev,
265
+					(void(*)(void *))clk_disable_unprepare,
266
+					clk);
267
+}
268
+
269
+static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
270
+{
271
+	u32 tx_dly_config, rx_dly_config, delay_config;
272
+	int ret;
273
+
274
+	tx_dly_config = FIELD_PREP(PRG_ETH0_TXDLY_MASK,
275
+				   dwmac->tx_delay_ns >> 1);
276
+
277
+	if (dwmac->rx_delay_ns == 2)
278
+		rx_dly_config = PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP;
279
+	else
280
+		rx_dly_config = 0;
253281 
254282 	switch (dwmac->phy_mode) {
255283 	case PHY_INTERFACE_MODE_RGMII:
284
+		delay_config = tx_dly_config | rx_dly_config;
285
+		break;
256286 	case PHY_INTERFACE_MODE_RGMII_RXID:
257
-		/* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where
258
-		 * 8ns are exactly one cycle of the 125MHz RGMII TX clock):
259
-		 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
260
-		 */
261
-		tx_dly_val = dwmac->tx_delay_ns >> 1;
262
-		/* fall through */
263
-
264
-	case PHY_INTERFACE_MODE_RGMII_ID:
287
+		delay_config = tx_dly_config;
288
+		break;
265289 	case PHY_INTERFACE_MODE_RGMII_TXID:
290
+		delay_config = rx_dly_config;
291
+		break;
292
+	case PHY_INTERFACE_MODE_RGMII_ID:
293
+	case PHY_INTERFACE_MODE_RMII:
294
+		delay_config = 0;
295
+		break;
296
+	default:
297
+		dev_err(dwmac->dev, "unsupported phy-mode %s\n",
298
+			phy_modes(dwmac->phy_mode));
299
+		return -EINVAL;
300
+	};
301
+
302
+	if (delay_config & PRG_ETH0_ADJ_ENABLE) {
303
+		if (!dwmac->timing_adj_clk) {
304
+			dev_err(dwmac->dev,
305
+				"The timing-adjustment clock is mandatory for the RX delay re-timing\n");
306
+			return -EINVAL;
307
+		}
308
+
309
+		/* The timing adjustment logic is driven by a separate clock */
310
+		ret = meson8b_devm_clk_prepare_enable(dwmac,
311
+						      dwmac->timing_adj_clk);
312
+		if (ret) {
313
+			dev_err(dwmac->dev,
314
+				"Failed to enable the timing-adjustment clock\n");
315
+			return ret;
316
+		}
317
+	}
318
+
319
+	meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK |
320
+				PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP |
321
+				PRG_ETH0_ADJ_DELAY | PRG_ETH0_ADJ_SKEW,
322
+				delay_config);
323
+
324
+	if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) {
266325 		/* only relevant for RMII mode -> disable in RGMII mode */
267326 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
268327 					PRG_ETH0_INVERTED_RMII_CLK, 0);
269
-
270
-		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
271
-					tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
272328 
273329 		/* Configure the 125MHz RGMII TX clock, the IP block changes
274330 		 * the output automatically (= without us having to configure
....@@ -282,34 +338,18 @@
282338 			return ret;
283339 		}
284340 
285
-		ret = clk_prepare_enable(dwmac->rgmii_tx_clk);
341
+		ret = meson8b_devm_clk_prepare_enable(dwmac,
342
+						      dwmac->rgmii_tx_clk);
286343 		if (ret) {
287344 			dev_err(dwmac->dev,
288345 				"failed to enable the RGMII TX clock\n");
289346 			return ret;
290347 		}
291
-
292
-		devm_add_action_or_reset(dwmac->dev,
293
-					(void(*)(void *))clk_disable_unprepare,
294
-					dwmac->rgmii_tx_clk);
295
-		break;
296
-
297
-	case PHY_INTERFACE_MODE_RMII:
348
+	} else {
298349 		/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
299350 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
300351 					PRG_ETH0_INVERTED_RMII_CLK,
301352 					PRG_ETH0_INVERTED_RMII_CLK);
302
-
303
-		/* TX clock delay cannot be configured in RMII mode */
304
-		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
305
-					0);
306
-
307
-		break;
308
-
309
-	default:
310
-		dev_err(dwmac->dev, "unsupported phy-mode %s\n",
311
-			phy_modes(dwmac->phy_mode));
312
-		return -EINVAL;
313353 	}
314354 
315355 	/* enable TX_CLK and PHY_REF_CLK generator */
....@@ -323,7 +363,6 @@
323363 {
324364 	struct plat_stmmacenet_data *plat_dat;
325365 	struct stmmac_resources stmmac_res;
326
-	struct resource *res;
327366 	struct meson8b_dwmac *dwmac;
328367 	int ret;
329368 
....@@ -347,18 +386,16 @@
347386 		ret = -EINVAL;
348387 		goto err_remove_config_dt;
349388 	}
350
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
351
-	dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
389
+	dwmac->regs = devm_platform_ioremap_resource(pdev, 1);
352390 	if (IS_ERR(dwmac->regs)) {
353391 		ret = PTR_ERR(dwmac->regs);
354392 		goto err_remove_config_dt;
355393 	}
356394 
357395 	dwmac->dev = &pdev->dev;
358
-	dwmac->phy_mode = of_get_phy_mode(pdev->dev.of_node);
359
-	if ((int)dwmac->phy_mode < 0) {
396
+	ret = of_get_phy_mode(pdev->dev.of_node, &dwmac->phy_mode);
397
+	if (ret) {
360398 		dev_err(&pdev->dev, "missing phy-mode property\n");
361
-		ret = -EINVAL;
362399 		goto err_remove_config_dt;
363400 	}
364401 
....@@ -366,6 +403,25 @@
366403 	if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns",
367404 				 &dwmac->tx_delay_ns))
368405 		dwmac->tx_delay_ns = 2;
406
+
407
+	/* use 0ns as fallback since this is what most boards actually use */
408
+	if (of_property_read_u32(pdev->dev.of_node, "amlogic,rx-delay-ns",
409
+				 &dwmac->rx_delay_ns))
410
+		dwmac->rx_delay_ns = 0;
411
+
412
+	if (dwmac->rx_delay_ns != 0 && dwmac->rx_delay_ns != 2) {
413
+		dev_err(&pdev->dev,
414
+			"The only allowed RX delays values are: 0ns, 2ns");
415
+		ret = -EINVAL;
416
+		goto err_remove_config_dt;
417
+	}
418
+
419
+	dwmac->timing_adj_clk = devm_clk_get_optional(dwmac->dev,
420
+						      "timing-adjustment");
421
+	if (IS_ERR(dwmac->timing_adj_clk)) {
422
+		ret = PTR_ERR(dwmac->timing_adj_clk);
423
+		goto err_remove_config_dt;
424
+	}
369425 
370426 	ret = meson8b_init_rgmii_tx_clk(dwmac);
371427 	if (ret)
....@@ -418,6 +474,10 @@
418474 		.compatible = "amlogic,meson-axg-dwmac",
419475 		.data = &meson_axg_dwmac_data,
420476 	},
477
+	{
478
+		.compatible = "amlogic,meson-g12a-dwmac",
479
+		.data = &meson_axg_dwmac_data,
480
+	},
421481 	{ }
422482 };
423483 MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);