| .. | .. |
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| 39 | 39 | #include <linux/if_link.h> |
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| 40 | 40 | #include <linux/firmware.h> |
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| 41 | 41 | #include <linux/mlx5/cq.h> |
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| 42 | +#include <linux/mlx5/fs.h> |
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| 43 | +#include <linux/mlx5/driver.h> |
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| 42 | 44 | |
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| 43 | 45 | #define DRIVER_NAME "mlx5_core" |
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| 44 | 46 | #define DRIVER_VERSION "5.0-0" |
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| .. | .. |
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| 46 | 48 | extern uint mlx5_core_debug_mask; |
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| 47 | 49 | |
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| 48 | 50 | #define mlx5_core_dbg(__dev, format, ...) \ |
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| 49 | | - dev_dbg(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \ |
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| 51 | + dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \ |
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| 50 | 52 | __func__, __LINE__, current->pid, \ |
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| 51 | 53 | ##__VA_ARGS__) |
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| 52 | 54 | |
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| 53 | | -#define mlx5_core_dbg_once(__dev, format, ...) \ |
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| 54 | | - dev_dbg_once(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \ |
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| 55 | | - __func__, __LINE__, current->pid, \ |
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| 55 | +#define mlx5_core_dbg_once(__dev, format, ...) \ |
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| 56 | + dev_dbg_once((__dev)->device, \ |
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| 57 | + "%s:%d:(pid %d): " format, \ |
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| 58 | + __func__, __LINE__, current->pid, \ |
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| 56 | 59 | ##__VA_ARGS__) |
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| 57 | 60 | |
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| 58 | | -#define mlx5_core_dbg_mask(__dev, mask, format, ...) \ |
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| 59 | | -do { \ |
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| 60 | | - if ((mask) & mlx5_core_debug_mask) \ |
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| 61 | | - mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \ |
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| 61 | +#define mlx5_core_dbg_mask(__dev, mask, format, ...) \ |
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| 62 | +do { \ |
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| 63 | + if ((mask) & mlx5_core_debug_mask) \ |
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| 64 | + mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \ |
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| 62 | 65 | } while (0) |
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| 63 | 66 | |
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| 64 | | -#define mlx5_core_err(__dev, format, ...) \ |
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| 65 | | - dev_err(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \ |
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| 66 | | - __func__, __LINE__, current->pid, \ |
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| 67 | +#define mlx5_core_err(__dev, format, ...) \ |
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| 68 | + dev_err((__dev)->device, "%s:%d:(pid %d): " format, \ |
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| 69 | + __func__, __LINE__, current->pid, \ |
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| 67 | 70 | ##__VA_ARGS__) |
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| 68 | 71 | |
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| 69 | | -#define mlx5_core_err_rl(__dev, format, ...) \ |
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| 70 | | - dev_err_ratelimited(&(__dev)->pdev->dev, \ |
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| 71 | | - "%s:%d:(pid %d): " format, \ |
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| 72 | | - __func__, __LINE__, current->pid, \ |
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| 73 | | - ##__VA_ARGS__) |
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| 72 | +#define mlx5_core_err_rl(__dev, format, ...) \ |
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| 73 | + dev_err_ratelimited((__dev)->device, \ |
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| 74 | + "%s:%d:(pid %d): " format, \ |
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| 75 | + __func__, __LINE__, current->pid, \ |
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| 76 | + ##__VA_ARGS__) |
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| 74 | 77 | |
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| 75 | | -#define mlx5_core_warn(__dev, format, ...) \ |
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| 76 | | - dev_warn(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \ |
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| 77 | | - __func__, __LINE__, current->pid, \ |
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| 78 | | - ##__VA_ARGS__) |
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| 78 | +#define mlx5_core_warn(__dev, format, ...) \ |
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| 79 | + dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \ |
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| 80 | + __func__, __LINE__, current->pid, \ |
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| 81 | + ##__VA_ARGS__) |
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| 79 | 82 | |
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| 80 | | -#define mlx5_core_info(__dev, format, ...) \ |
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| 81 | | - dev_info(&(__dev)->pdev->dev, format, ##__VA_ARGS__) |
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| 83 | +#define mlx5_core_warn_once(__dev, format, ...) \ |
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| 84 | + dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \ |
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| 85 | + __func__, __LINE__, current->pid, \ |
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| 86 | + ##__VA_ARGS__) |
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| 87 | + |
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| 88 | +#define mlx5_core_warn_rl(__dev, format, ...) \ |
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| 89 | + dev_warn_ratelimited((__dev)->device, \ |
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| 90 | + "%s:%d:(pid %d): " format, \ |
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| 91 | + __func__, __LINE__, current->pid, \ |
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| 92 | + ##__VA_ARGS__) |
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| 93 | + |
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| 94 | +#define mlx5_core_info(__dev, format, ...) \ |
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| 95 | + dev_info((__dev)->device, format, ##__VA_ARGS__) |
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| 96 | + |
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| 97 | +#define mlx5_core_info_rl(__dev, format, ...) \ |
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| 98 | + dev_info_ratelimited((__dev)->device, \ |
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| 99 | + "%s:%d:(pid %d): " format, \ |
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| 100 | + __func__, __LINE__, current->pid, \ |
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| 101 | + ##__VA_ARGS__) |
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| 102 | + |
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| 103 | +static inline struct device *mlx5_core_dma_dev(struct mlx5_core_dev *dev) |
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| 104 | +{ |
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| 105 | + return &dev->pdev->dev; |
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| 106 | +} |
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| 82 | 107 | |
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| 83 | 108 | enum { |
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| 84 | 109 | MLX5_CMD_DATA, /* print command payload only */ |
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| .. | .. |
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| 90 | 115 | MLX5_DRIVER_SYND = 0xbadd00de, |
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| 91 | 116 | }; |
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| 92 | 117 | |
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| 118 | +enum mlx5_semaphore_space_address { |
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| 119 | + MLX5_SEMAPHORE_SPACE_DOMAIN = 0xA, |
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| 120 | + MLX5_SEMAPHORE_SW_RESET = 0x20, |
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| 121 | +}; |
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| 122 | + |
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| 93 | 123 | int mlx5_query_hca_caps(struct mlx5_core_dev *dev); |
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| 94 | 124 | int mlx5_query_board_id(struct mlx5_core_dev *dev); |
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| 95 | 125 | int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id); |
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| 96 | 126 | int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev); |
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| 97 | 127 | int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev); |
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| 98 | | -void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, |
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| 99 | | - unsigned long param); |
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| 100 | | -void mlx5_core_page_fault(struct mlx5_core_dev *dev, |
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| 101 | | - struct mlx5_pagefault *pfault); |
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| 102 | | -void mlx5_port_module_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe); |
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| 128 | +int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev); |
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| 103 | 129 | void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force); |
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| 130 | +void mlx5_error_sw_reset(struct mlx5_core_dev *dev); |
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| 131 | +u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev); |
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| 132 | +int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev); |
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| 104 | 133 | void mlx5_disable_device(struct mlx5_core_dev *dev); |
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| 105 | 134 | void mlx5_recover_device(struct mlx5_core_dev *dev); |
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| 106 | 135 | int mlx5_sriov_init(struct mlx5_core_dev *dev); |
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| .. | .. |
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| 108 | 137 | int mlx5_sriov_attach(struct mlx5_core_dev *dev); |
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| 109 | 138 | void mlx5_sriov_detach(struct mlx5_core_dev *dev); |
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| 110 | 139 | int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs); |
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| 111 | | -bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev); |
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| 112 | 140 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id); |
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| 113 | 141 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id); |
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| 114 | 142 | int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, |
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| .. | .. |
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| 118 | 146 | u32 modify_bitmask); |
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| 119 | 147 | int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, |
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| 120 | 148 | u32 element_id); |
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| 121 | | -int mlx5_wait_for_vf_pages(struct mlx5_core_dev *dev); |
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| 122 | | -u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev); |
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| 149 | +int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages); |
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| 123 | 150 | |
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| 124 | | -int mlx5_eq_init(struct mlx5_core_dev *dev); |
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| 125 | | -void mlx5_eq_cleanup(struct mlx5_core_dev *dev); |
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| 126 | | -int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, |
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| 127 | | - int nent, u64 mask, const char *name, |
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| 128 | | - enum mlx5_eq_type type); |
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| 129 | | -int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
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| 130 | | -int mlx5_eq_add_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq); |
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| 131 | | -int mlx5_eq_del_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq); |
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| 132 | | -int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, |
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| 133 | | - u32 *out, int outlen); |
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| 134 | | -int mlx5_start_eqs(struct mlx5_core_dev *dev); |
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| 135 | | -void mlx5_stop_eqs(struct mlx5_core_dev *dev); |
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| 136 | | -/* This function should only be called after mlx5_cmd_force_teardown_hca */ |
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| 137 | | -void mlx5_core_eq_free_irqs(struct mlx5_core_dev *dev); |
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| 138 | | -struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn); |
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| 139 | | -u32 mlx5_eq_poll_irq_disabled(struct mlx5_eq *eq); |
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| 140 | | -void mlx5_cq_tasklet_cb(unsigned long data); |
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| 141 | | -void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced); |
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| 142 | | -int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
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| 143 | | -void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
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| 144 | | -int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); |
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| 145 | | -void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); |
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| 146 | | -int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); |
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| 151 | +void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev); |
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| 152 | +void mlx5_cmd_flush(struct mlx5_core_dev *dev); |
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| 153 | +void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); |
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| 147 | 154 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); |
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| 148 | 155 | |
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| 149 | 156 | int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group, |
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| .. | .. |
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| 156 | 163 | void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev); |
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| 157 | 164 | void mlx5_lag_remove(struct mlx5_core_dev *dev); |
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| 158 | 165 | |
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| 166 | +int mlx5_irq_table_init(struct mlx5_core_dev *dev); |
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| 167 | +void mlx5_irq_table_cleanup(struct mlx5_core_dev *dev); |
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| 168 | +int mlx5_irq_table_create(struct mlx5_core_dev *dev); |
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| 169 | +void mlx5_irq_table_destroy(struct mlx5_core_dev *dev); |
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| 170 | +int mlx5_irq_attach_nb(struct mlx5_irq_table *irq_table, int vecidx, |
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| 171 | + struct notifier_block *nb); |
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| 172 | +int mlx5_irq_detach_nb(struct mlx5_irq_table *irq_table, int vecidx, |
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| 173 | + struct notifier_block *nb); |
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| 174 | +struct cpumask * |
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| 175 | +mlx5_irq_get_affinity_mask(struct mlx5_irq_table *irq_table, int vecidx); |
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| 176 | +struct cpu_rmap *mlx5_irq_get_rmap(struct mlx5_irq_table *table); |
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| 177 | +int mlx5_irq_get_num_comp(struct mlx5_irq_table *table); |
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| 178 | + |
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| 179 | +int mlx5_events_init(struct mlx5_core_dev *dev); |
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| 180 | +void mlx5_events_cleanup(struct mlx5_core_dev *dev); |
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| 181 | +void mlx5_events_start(struct mlx5_core_dev *dev); |
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| 182 | +void mlx5_events_stop(struct mlx5_core_dev *dev); |
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| 183 | + |
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| 159 | 184 | void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv); |
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| 160 | 185 | void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv); |
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| 161 | 186 | void mlx5_attach_device(struct mlx5_core_dev *dev); |
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| 162 | 187 | void mlx5_detach_device(struct mlx5_core_dev *dev); |
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| 163 | 188 | bool mlx5_device_registered(struct mlx5_core_dev *dev); |
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| 164 | | -int mlx5_register_device(struct mlx5_core_dev *dev); |
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| 189 | +void mlx5_register_device(struct mlx5_core_dev *dev); |
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| 165 | 190 | void mlx5_unregister_device(struct mlx5_core_dev *dev); |
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| 166 | 191 | void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol); |
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| 167 | 192 | void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol); |
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| .. | .. |
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| 169 | 194 | void mlx5_dev_list_lock(void); |
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| 170 | 195 | void mlx5_dev_list_unlock(void); |
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| 171 | 196 | int mlx5_dev_list_trylock(void); |
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| 172 | | -int mlx5_encap_alloc(struct mlx5_core_dev *dev, |
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| 173 | | - int header_type, |
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| 174 | | - size_t size, |
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| 175 | | - void *encap_header, |
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| 176 | | - u32 *encap_id); |
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| 177 | | -void mlx5_encap_dealloc(struct mlx5_core_dev *dev, u32 encap_id); |
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| 178 | | - |
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| 179 | | -int mlx5_modify_header_alloc(struct mlx5_core_dev *dev, |
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| 180 | | - u8 namespace, u8 num_actions, |
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| 181 | | - void *modify_actions, u32 *modify_header_id); |
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| 182 | | -void mlx5_modify_header_dealloc(struct mlx5_core_dev *dev, u32 modify_header_id); |
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| 183 | 197 | |
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| 184 | 198 | bool mlx5_lag_intf_add(struct mlx5_interface *intf, struct mlx5_priv *priv); |
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| 185 | 199 | |
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| .. | .. |
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| 188 | 202 | int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode); |
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| 189 | 203 | int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode); |
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| 190 | 204 | |
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| 205 | +struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev); |
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| 206 | +void mlx5_dm_cleanup(struct mlx5_core_dev *dev); |
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| 207 | + |
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| 191 | 208 | #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \ |
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| 192 | 209 | MLX5_CAP_GEN((mdev), pps_modify) && \ |
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| 193 | 210 | MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \ |
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| 194 | 211 | MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj)) |
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| 195 | 212 | |
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| 196 | | -int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw); |
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| 213 | +int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw, |
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| 214 | + struct netlink_ext_ack *extack); |
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| 215 | +int mlx5_fw_version_query(struct mlx5_core_dev *dev, |
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| 216 | + u32 *running_ver, u32 *stored_ver); |
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| 197 | 217 | |
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| 198 | 218 | void mlx5e_init(void); |
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| 199 | 219 | void mlx5e_cleanup(void); |
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| 220 | + |
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| 221 | +static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev) |
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| 222 | +{ |
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| 223 | + return pci_num_vf(dev->pdev) ? true : false; |
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| 224 | +} |
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| 200 | 225 | |
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| 201 | 226 | static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev) |
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| 202 | 227 | { |
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| .. | .. |
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| 210 | 235 | MLX5_CAP_GEN(dev, lag_master); |
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| 211 | 236 | } |
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| 212 | 237 | |
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| 213 | | -int mlx5_lag_allow(struct mlx5_core_dev *dev); |
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| 214 | | -int mlx5_lag_forbid(struct mlx5_core_dev *dev); |
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| 215 | | - |
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| 216 | 238 | void mlx5_reload_interface(struct mlx5_core_dev *mdev, int protocol); |
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| 239 | +void mlx5_lag_update(struct mlx5_core_dev *dev); |
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| 240 | + |
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| 241 | +enum { |
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| 242 | + MLX5_NIC_IFC_FULL = 0, |
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| 243 | + MLX5_NIC_IFC_DISABLED = 1, |
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| 244 | + MLX5_NIC_IFC_NO_DRAM_NIC = 2, |
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| 245 | + MLX5_NIC_IFC_SW_RESET = 7 |
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| 246 | +}; |
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| 247 | + |
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| 248 | +u8 mlx5_get_nic_state(struct mlx5_core_dev *dev); |
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| 249 | +void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state); |
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| 250 | + |
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| 251 | +void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup); |
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| 252 | +int mlx5_load_one(struct mlx5_core_dev *dev, bool boot); |
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| 217 | 253 | #endif /* __MLX5_CORE_H__ */ |
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