disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/net/ethernet/mellanox/mlx5/core/fw.c
..
..
@@ -31,32 +31,56 @@
31
31
  */
32
32
 
33
33
 #include <linux/mlx5/driver.h>
34
-#include <linux/mlx5/cmd.h>
35
34
 #include <linux/mlx5/eswitch.h>
36
35
 #include <linux/module.h>
37
36
 #include "mlx5_core.h"
38
37
 #include "../../mlxfw/mlxfw.h"
38
+#include "accel/tls.h"
39
39
 
40
-static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out,
41
-				  int outlen)
42
-{
43
-	u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {0};
40
+enum {
41
+	MCQS_IDENTIFIER_BOOT_IMG	= 0x1,
42
+	MCQS_IDENTIFIER_OEM_NVCONFIG	= 0x4,
43
+	MCQS_IDENTIFIER_MLNX_NVCONFIG	= 0x5,
44
+	MCQS_IDENTIFIER_CS_TOKEN	= 0x6,
45
+	MCQS_IDENTIFIER_DBG_TOKEN	= 0x7,
46
+	MCQS_IDENTIFIER_GEARBOX		= 0xA,
47
+};
44
48
 
45
-	MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
46
-	return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
47
-}
49
+enum {
50
+	MCQS_UPDATE_STATE_IDLE,
51
+	MCQS_UPDATE_STATE_IN_PROGRESS,
52
+	MCQS_UPDATE_STATE_APPLIED,
53
+	MCQS_UPDATE_STATE_ACTIVE,
54
+	MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET,
55
+	MCQS_UPDATE_STATE_FAILED,
56
+	MCQS_UPDATE_STATE_CANCELED,
57
+	MCQS_UPDATE_STATE_BUSY,
58
+};
59
+
60
+enum {
61
+	MCQI_INFO_TYPE_CAPABILITIES	  = 0x0,
62
+	MCQI_INFO_TYPE_VERSION		  = 0x1,
63
+	MCQI_INFO_TYPE_ACTIVATION_METHOD  = 0x5,
64
+};
65
+
66
+enum {
67
+	MCQI_FW_RUNNING_VERSION = 0,
68
+	MCQI_FW_STORED_VERSION  = 1,
69
+};
48
70
 
49
71
 int mlx5_query_board_id(struct mlx5_core_dev *dev)
50
72
 {
51
73
 	u32 *out;
52
74
 	int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
75
+	u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
53
76
 	int err;
54
77
 
55
78
 	out = kzalloc(outlen, GFP_KERNEL);
56
79
 	if (!out)
57
80
 		return -ENOMEM;
58
81
 
59
-	err = mlx5_cmd_query_adapter(dev, out, outlen);
82
+	MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
83
+	err = mlx5_cmd_exec_inout(dev, query_adapter, in, out);
60
84
 	if (err)
61
85
 		goto out;
62
86
 
..
..
@@ -75,13 +99,15 @@
75
99
 {
76
100
 	u32 *out;
77
101
 	int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
102
+	u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
78
103
 	int err;
79
104
 
80
105
 	out = kzalloc(outlen, GFP_KERNEL);
81
106
 	if (!out)
82
107
 		return -ENOMEM;
83
108
 
84
-	err = mlx5_cmd_query_adapter(mdev, out, outlen);
109
+	MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
110
+	err = mlx5_cmd_exec_inout(mdev, query_adapter, in, out);
85
111
 	if (err)
86
112
 		goto out;
87
113
 
..
..
@@ -100,11 +126,11 @@
100
126
 				   MLX5_PCAM_REGS_5000_TO_507F);
101
127
 }
102
128
 
103
-static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
129
+static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev,
130
+					  enum mlx5_mcam_reg_groups group)
104
131
 {
105
-	return mlx5_query_mcam_reg(dev, dev->caps.mcam,
106
-				   MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
107
-				   MLX5_MCAM_REGS_FIRST_128);
132
+	return mlx5_query_mcam_reg(dev, dev->caps.mcam[group],
133
+				   MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group);
108
134
 }
109
135
 
110
136
 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
..
..
@@ -190,8 +216,11 @@
190
216
 	if (MLX5_CAP_GEN(dev, pcam_reg))
191
217
 		mlx5_get_pcam_reg(dev);
192
218
 
193
-	if (MLX5_CAP_GEN(dev, mcam_reg))
194
-		mlx5_get_mcam_reg(dev);
219
+	if (MLX5_CAP_GEN(dev, mcam_reg)) {
220
+		mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128);
221
+		mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9080_0x90FF);
222
+		mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F);
223
+	}
195
224
 
196
225
 	if (MLX5_CAP_GEN(dev, qcam_reg))
197
226
 		mlx5_get_qcam_reg(dev);
..
..
@@ -202,13 +231,37 @@
202
231
 			return err;
203
232
 	}
204
233
 
234
+	if (MLX5_CAP_GEN(dev, event_cap)) {
235
+		err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_EVENT);
236
+		if (err)
237
+			return err;
238
+	}
239
+
240
+	if (mlx5_accel_is_ktls_tx(dev) || mlx5_accel_is_ktls_rx(dev)) {
241
+		err = mlx5_core_get_caps(dev, MLX5_CAP_TLS);
242
+		if (err)
243
+			return err;
244
+	}
245
+
246
+	if (MLX5_CAP_GEN_64(dev, general_obj_types) &
247
+		MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
248
+		err = mlx5_core_get_caps(dev, MLX5_CAP_VDPA_EMULATION);
249
+		if (err)
250
+			return err;
251
+	}
252
+
253
+	if (MLX5_CAP_GEN(dev, ipsec_offload)) {
254
+		err = mlx5_core_get_caps(dev, MLX5_CAP_IPSEC);
255
+		if (err)
256
+			return err;
257
+	}
258
+
205
259
 	return 0;
206
260
 }
207
261
 
208
262
 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id)
209
263
 {
210
-	u32 out[MLX5_ST_SZ_DW(init_hca_out)] = {0};
211
-	u32 in[MLX5_ST_SZ_DW(init_hca_in)]   = {0};
264
+	u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {};
212
265
 	int i;
213
266
 
214
267
 	MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
..
..
@@ -219,16 +272,15 @@
219
272
 				       sw_owner_id[i]);
220
273
 	}
221
274
 
222
-	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
275
+	return mlx5_cmd_exec_in(dev, init_hca, in);
223
276
 }
224
277
 
225
278
 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
226
279
 {
227
-	u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
228
-	u32 in[MLX5_ST_SZ_DW(teardown_hca_in)]   = {0};
280
+	u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
229
281
 
230
282
 	MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
231
-	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
283
+	return mlx5_cmd_exec_in(dev, teardown_hca, in);
232
284
 }
233
285
 
234
286
 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
..
..
@@ -250,9 +302,57 @@
250
302
 	if (ret)
251
303
 		return ret;
252
304
 
253
-	force_state = MLX5_GET(teardown_hca_out, out, force_state);
305
+	force_state = MLX5_GET(teardown_hca_out, out, state);
254
306
 	if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
255
307
 		mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n");
308
+		return -EIO;
309
+	}
310
+
311
+	return 0;
312
+}
313
+
314
+#define MLX5_FAST_TEARDOWN_WAIT_MS   3000
315
+int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
316
+{
317
+	unsigned long end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS;
318
+	u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
319
+	u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
320
+	int state;
321
+	int ret;
322
+
323
+	if (!MLX5_CAP_GEN(dev, fast_teardown)) {
324
+		mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
325
+		return -EOPNOTSUPP;
326
+	}
327
+
328
+	MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
329
+	MLX5_SET(teardown_hca_in, in, profile,
330
+		 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
331
+
332
+	ret = mlx5_cmd_exec_inout(dev, teardown_hca, in, out);
333
+	if (ret)
334
+		return ret;
335
+
336
+	state = MLX5_GET(teardown_hca_out, out, state);
337
+	if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
338
+		mlx5_core_warn(dev, "teardown with fast mode failed\n");
339
+		return -EIO;
340
+	}
341
+
342
+	mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED);
343
+
344
+	/* Loop until device state turns to disable */
345
+	end = jiffies + msecs_to_jiffies(delay_ms);
346
+	do {
347
+		if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
348
+			break;
349
+
350
+		cond_resched();
351
+	} while (!time_after(jiffies, end));
352
+
353
+	if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
354
+		dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n",
355
+			mlx5_get_nic_state(dev), delay_ms);
256
356
 		return -EIO;
257
357
 	}
258
358
 
..
..
@@ -344,33 +444,49 @@
344
444
 }
345
445
 
346
446
 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
347
-			       u16 component_index,
348
-			       u32 *max_component_size,
349
-			       u8 *log_mcda_word_size,
350
-			       u16 *mcda_max_write_size)
447
+			       u16 component_index, bool read_pending,
448
+			       u8 info_type, u16 data_size, void *mcqi_data)
351
449
 {
352
-	u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)];
353
-	int offset = MLX5_ST_SZ_DW(mcqi_reg);
354
-	u32 in[MLX5_ST_SZ_DW(mcqi_reg)];
450
+	u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_UN_SZ_DW(mcqi_reg_data)] = {};
451
+	u32 in[MLX5_ST_SZ_DW(mcqi_reg)] = {};
452
+	void *data;
355
453
 	int err;
356
454
 
357
-	memset(in, 0, sizeof(in));
358
-	memset(out, 0, sizeof(out));
359
-
360
455
 	MLX5_SET(mcqi_reg, in, component_index, component_index);
361
-	MLX5_SET(mcqi_reg, in, data_size, MLX5_ST_SZ_BYTES(mcqi_cap));
456
+	MLX5_SET(mcqi_reg, in, read_pending_component, read_pending);
457
+	MLX5_SET(mcqi_reg, in, info_type, info_type);
458
+	MLX5_SET(mcqi_reg, in, data_size, data_size);
362
459
 
363
460
 	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
364
-				   sizeof(out), MLX5_REG_MCQI, 0, 0);
461
+				   MLX5_ST_SZ_BYTES(mcqi_reg) + data_size,
462
+				   MLX5_REG_MCQI, 0, 0);
365
463
 	if (err)
366
-		goto out;
464
+		return err;
367
465
 
368
-	*max_component_size = MLX5_GET(mcqi_cap, out + offset, max_component_size);
369
-	*log_mcda_word_size = MLX5_GET(mcqi_cap, out + offset, log_mcda_word_size);
370
-	*mcda_max_write_size = MLX5_GET(mcqi_cap, out + offset, mcda_max_write_size);
466
+	data = MLX5_ADDR_OF(mcqi_reg, out, data);
467
+	memcpy(mcqi_data, data, data_size);
371
468
 
372
-out:
373
-	return err;
469
+	return 0;
470
+}
471
+
472
+static int mlx5_reg_mcqi_caps_query(struct mlx5_core_dev *dev, u16 component_index,
473
+				    u32 *max_component_size, u8 *log_mcda_word_size,
474
+				    u16 *mcda_max_write_size)
475
+{
476
+	u32 mcqi_reg[MLX5_ST_SZ_DW(mcqi_cap)] = {};
477
+	int err;
478
+
479
+	err = mlx5_reg_mcqi_query(dev, component_index, 0,
480
+				  MCQI_INFO_TYPE_CAPABILITIES,
481
+				  MLX5_ST_SZ_BYTES(mcqi_cap), mcqi_reg);
482
+	if (err)
483
+		return err;
484
+
485
+	*max_component_size = MLX5_GET(mcqi_cap, mcqi_reg, max_component_size);
486
+	*log_mcda_word_size = MLX5_GET(mcqi_cap, mcqi_reg, log_mcda_word_size);
487
+	*mcda_max_write_size = MLX5_GET(mcqi_cap, mcqi_reg, mcda_max_write_size);
488
+
489
+	return 0;
374
490
 }
375
491
 
376
492
 struct mlx5_mlxfw_dev {
..
..
@@ -386,8 +502,13 @@
386
502
 		container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
387
503
 	struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
388
504
 
389
-	return mlx5_reg_mcqi_query(dev, component_index, p_max_size,
390
-				   p_align_bits, p_max_write_size);
505
+	if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi)) {
506
+		mlx5_core_warn(dev, "caps query isn't supported by running FW\n");
507
+		return -EOPNOTSUPP;
508
+	}
509
+
510
+	return mlx5_reg_mcqi_caps_query(dev, component_index, p_max_size,
511
+					p_align_bits, p_max_write_size);
391
512
 }
392
513
 
393
514
 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
..
..
@@ -491,6 +612,44 @@
491
612
 			 fwhandle, 0);
492
613
 }
493
614
 
615
+#define MLX5_FSM_REACTIVATE_TOUT 5000 /* msecs */
616
+static int mlx5_fsm_reactivate(struct mlxfw_dev *mlxfw_dev, u8 *status)
617
+{
618
+	unsigned long exp_time = jiffies + msecs_to_jiffies(MLX5_FSM_REACTIVATE_TOUT);
619
+	struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
620
+		container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
621
+	struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
622
+	u32 out[MLX5_ST_SZ_DW(mirc_reg)];
623
+	u32 in[MLX5_ST_SZ_DW(mirc_reg)];
624
+	int err;
625
+
626
+	if (!MLX5_CAP_MCAM_REG2(dev, mirc))
627
+		return -EOPNOTSUPP;
628
+
629
+	memset(in, 0, sizeof(in));
630
+
631
+	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
632
+				   sizeof(out), MLX5_REG_MIRC, 0, 1);
633
+	if (err)
634
+		return err;
635
+
636
+	do {
637
+		memset(out, 0, sizeof(out));
638
+		err = mlx5_core_access_reg(dev, in, sizeof(in), out,
639
+					   sizeof(out), MLX5_REG_MIRC, 0, 0);
640
+		if (err)
641
+			return err;
642
+
643
+		*status = MLX5_GET(mirc_reg, out, status_code);
644
+		if (*status != MLXFW_FSM_REACTIVATE_STATUS_BUSY)
645
+			return 0;
646
+
647
+		msleep(20);
648
+	} while (time_before(jiffies, exp_time));
649
+
650
+	return 0;
651
+}
652
+
494
653
 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
495
654
 	.component_query	= mlx5_component_query,
496
655
 	.fsm_lock		= mlx5_fsm_lock,
..
..
@@ -498,19 +657,22 @@
498
657
 	.fsm_block_download	= mlx5_fsm_block_download,
499
658
 	.fsm_component_verify	= mlx5_fsm_component_verify,
500
659
 	.fsm_activate		= mlx5_fsm_activate,
660
+	.fsm_reactivate		= mlx5_fsm_reactivate,
501
661
 	.fsm_query_state	= mlx5_fsm_query_state,
502
662
 	.fsm_cancel		= mlx5_fsm_cancel,
503
663
 	.fsm_release		= mlx5_fsm_release
504
664
 };
505
665
 
506
666
 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
507
-			const struct firmware *firmware)
667
+			const struct firmware *firmware,
668
+			struct netlink_ext_ack *extack)
508
669
 {
509
670
 	struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
510
671
 		.mlxfw_dev = {
511
672
 			.ops = &mlx5_mlxfw_dev_ops,
512
673
 			.psid = dev->board_id,
513
674
 			.psid_size = strlen(dev->board_id),
675
+			.devlink = priv_to_devlink(dev),
514
676
 		},
515
677
 		.mlx5_core_dev = dev
516
678
 	};
..
..
@@ -523,5 +685,133 @@
523
685
 		return -EOPNOTSUPP;
524
686
 	}
525
687
 
526
-	return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, firmware);
688
+	return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev,
689
+				    firmware, extack);
690
+}
691
+
692
+static int mlx5_reg_mcqi_version_query(struct mlx5_core_dev *dev,
693
+				       u16 component_index, bool read_pending,
694
+				       u32 *mcqi_version_out)
695
+{
696
+	return mlx5_reg_mcqi_query(dev, component_index, read_pending,
697
+				   MCQI_INFO_TYPE_VERSION,
698
+				   MLX5_ST_SZ_BYTES(mcqi_version),
699
+				   mcqi_version_out);
700
+}
701
+
702
+static int mlx5_reg_mcqs_query(struct mlx5_core_dev *dev, u32 *out,
703
+			       u16 component_index)
704
+{
705
+	u8 out_sz = MLX5_ST_SZ_BYTES(mcqs_reg);
706
+	u32 in[MLX5_ST_SZ_DW(mcqs_reg)] = {};
707
+	int err;
708
+
709
+	memset(out, 0, out_sz);
710
+
711
+	MLX5_SET(mcqs_reg, in, component_index, component_index);
712
+
713
+	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
714
+				   out_sz, MLX5_REG_MCQS, 0, 0);
715
+	return err;
716
+}
717
+
718
+/* scans component index sequentially, to find the boot img index */
719
+static int mlx5_get_boot_img_component_index(struct mlx5_core_dev *dev)
720
+{
721
+	u32 out[MLX5_ST_SZ_DW(mcqs_reg)] = {};
722
+	u16 identifier, component_idx = 0;
723
+	bool quit;
724
+	int err;
725
+
726
+	do {
727
+		err = mlx5_reg_mcqs_query(dev, out, component_idx);
728
+		if (err)
729
+			return err;
730
+
731
+		identifier = MLX5_GET(mcqs_reg, out, identifier);
732
+		quit = !!MLX5_GET(mcqs_reg, out, last_index_flag);
733
+		quit |= identifier == MCQS_IDENTIFIER_BOOT_IMG;
734
+	} while (!quit && ++component_idx);
735
+
736
+	if (identifier != MCQS_IDENTIFIER_BOOT_IMG) {
737
+		mlx5_core_warn(dev, "mcqs: can't find boot_img component ix, last scanned idx %d\n",
738
+			       component_idx);
739
+		return -EOPNOTSUPP;
740
+	}
741
+
742
+	return component_idx;
743
+}
744
+
745
+static int
746
+mlx5_fw_image_pending(struct mlx5_core_dev *dev,
747
+		      int component_index,
748
+		      bool *pending_version_exists)
749
+{
750
+	u32 out[MLX5_ST_SZ_DW(mcqs_reg)];
751
+	u8 component_update_state;
752
+	int err;
753
+
754
+	err = mlx5_reg_mcqs_query(dev, out, component_index);
755
+	if (err)
756
+		return err;
757
+
758
+	component_update_state = MLX5_GET(mcqs_reg, out, component_update_state);
759
+
760
+	if (component_update_state == MCQS_UPDATE_STATE_IDLE) {
761
+		*pending_version_exists = false;
762
+	} else if (component_update_state == MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET) {
763
+		*pending_version_exists = true;
764
+	} else {
765
+		mlx5_core_warn(dev,
766
+			       "mcqs: can't read pending fw version while fw state is %d\n",
767
+			       component_update_state);
768
+		return -ENODATA;
769
+	}
770
+	return 0;
771
+}
772
+
773
+int mlx5_fw_version_query(struct mlx5_core_dev *dev,
774
+			  u32 *running_ver, u32 *pending_ver)
775
+{
776
+	u32 reg_mcqi_version[MLX5_ST_SZ_DW(mcqi_version)] = {};
777
+	bool pending_version_exists;
778
+	int component_index;
779
+	int err;
780
+
781
+	if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi) ||
782
+	    !MLX5_CAP_MCAM_REG(dev, mcqs)) {
783
+		mlx5_core_warn(dev, "fw query isn't supported by the FW\n");
784
+		return -EOPNOTSUPP;
785
+	}
786
+
787
+	component_index = mlx5_get_boot_img_component_index(dev);
788
+	if (component_index < 0)
789
+		return component_index;
790
+
791
+	err = mlx5_reg_mcqi_version_query(dev, component_index,
792
+					  MCQI_FW_RUNNING_VERSION,
793
+					  reg_mcqi_version);
794
+	if (err)
795
+		return err;
796
+
797
+	*running_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
798
+
799
+	err = mlx5_fw_image_pending(dev, component_index, &pending_version_exists);
800
+	if (err)
801
+		return err;
802
+
803
+	if (!pending_version_exists) {
804
+		*pending_ver = 0;
805
+		return 0;
806
+	}
807
+
808
+	err = mlx5_reg_mcqi_version_query(dev, component_index,
809
+					  MCQI_FW_STORED_VERSION,
810
+					  reg_mcqi_version);
811
+	if (err)
812
+		return err;
813
+
814
+	*pending_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
815
+
816
+	return 0;
527
817
 }