disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_stats.c
..
..
@@ -38,6 +38,7 @@
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 #include "accel/ipsec.h"
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 #include "fpga/sdk.h"
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 #include "en_accel/ipsec.h"
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+#include "fpga/ipsec.h"
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42
 
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 static const struct counter_desc mlx5e_ipsec_hw_stats_desc[] = {
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 	{ MLX5E_DECLARE_STAT(struct mlx5e_ipsec_stats, ipsec_dec_in_packets) },
..
..
@@ -73,61 +74,74 @@
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 #define NUM_IPSEC_HW_COUNTERS ARRAY_SIZE(mlx5e_ipsec_hw_stats_desc)
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 #define NUM_IPSEC_SW_COUNTERS ARRAY_SIZE(mlx5e_ipsec_sw_stats_desc)
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-#define NUM_IPSEC_COUNTERS (NUM_IPSEC_HW_COUNTERS + NUM_IPSEC_SW_COUNTERS)
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-
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-int mlx5e_ipsec_get_count(struct mlx5e_priv *priv)
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+static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(ipsec_sw)
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 {
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-	if (!priv->ipsec)
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-		return 0;
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-
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-	return NUM_IPSEC_COUNTERS;
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+	return priv->ipsec ? NUM_IPSEC_SW_COUNTERS : 0;
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 }
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-int mlx5e_ipsec_get_strings(struct mlx5e_priv *priv, uint8_t *data)
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+static inline MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(ipsec_sw) {}
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+
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+static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(ipsec_sw)
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 {
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-	unsigned int i, idx = 0;
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+	unsigned int i;
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-	if (!priv->ipsec)
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-		return 0;
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-
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-	for (i = 0; i < NUM_IPSEC_HW_COUNTERS; i++)
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-		strcpy(data + (idx++) * ETH_GSTRING_LEN,
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-		       mlx5e_ipsec_hw_stats_desc[i].format);
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-
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-	for (i = 0; i < NUM_IPSEC_SW_COUNTERS; i++)
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-		strcpy(data + (idx++) * ETH_GSTRING_LEN,
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-		       mlx5e_ipsec_sw_stats_desc[i].format);
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-
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-	return NUM_IPSEC_COUNTERS;
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+	if (priv->ipsec)
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+		for (i = 0; i < NUM_IPSEC_SW_COUNTERS; i++)
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+			strcpy(data + (idx++) * ETH_GSTRING_LEN,
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+			       mlx5e_ipsec_sw_stats_desc[i].format);
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+	return idx;
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 }
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-void mlx5e_ipsec_update_stats(struct mlx5e_priv *priv)
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+static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(ipsec_sw)
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 {
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-	int ret;
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+	int i;
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-	if (!priv->ipsec)
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-		return;
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+	if (priv->ipsec)
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+		for (i = 0; i < NUM_IPSEC_SW_COUNTERS; i++)
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+			data[idx++] = MLX5E_READ_CTR_ATOMIC64(&priv->ipsec->sw_stats,
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+							      mlx5e_ipsec_sw_stats_desc, i);
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+	return idx;
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+}
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-	ret = mlx5_accel_ipsec_counters_read(priv->mdev, (u64 *)&priv->ipsec->stats,
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-					     NUM_IPSEC_HW_COUNTERS);
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+static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(ipsec_hw)
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+{
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+	return (priv->ipsec && mlx5_fpga_ipsec_device_caps(priv->mdev)) ? NUM_IPSEC_HW_COUNTERS : 0;
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+}
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+
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+static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(ipsec_hw)
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+{
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+	int ret = 0;
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+
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+	if (priv->ipsec)
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+		ret = mlx5_accel_ipsec_counters_read(priv->mdev, (u64 *)&priv->ipsec->stats,
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+						     NUM_IPSEC_HW_COUNTERS);
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 	if (ret)
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 		memset(&priv->ipsec->stats, 0, sizeof(priv->ipsec->stats));
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 }
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121
 
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-int mlx5e_ipsec_get_stats(struct mlx5e_priv *priv, u64 *data)
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+static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(ipsec_hw)
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 {
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-	int i, idx = 0;
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+	unsigned int i;
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-	if (!priv->ipsec)
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-		return 0;
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+	if (priv->ipsec && mlx5_fpga_ipsec_device_caps(priv->mdev))
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+		for (i = 0; i < NUM_IPSEC_HW_COUNTERS; i++)
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+			strcpy(data + (idx++) * ETH_GSTRING_LEN,
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+			       mlx5e_ipsec_hw_stats_desc[i].format);
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-	for (i = 0; i < NUM_IPSEC_HW_COUNTERS; i++)
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-		data[idx++] = MLX5E_READ_CTR64_CPU(&priv->ipsec->stats,
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-						   mlx5e_ipsec_hw_stats_desc, i);
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-
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-	for (i = 0; i < NUM_IPSEC_SW_COUNTERS; i++)
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-		data[idx++] = MLX5E_READ_CTR_ATOMIC64(&priv->ipsec->sw_stats,
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-						      mlx5e_ipsec_sw_stats_desc, i);
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-
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-	return NUM_IPSEC_COUNTERS;
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+	return idx;
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 }
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+
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+static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(ipsec_hw)
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+{
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+	int i;
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+
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+	if (priv->ipsec && mlx5_fpga_ipsec_device_caps(priv->mdev))
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+		for (i = 0; i < NUM_IPSEC_HW_COUNTERS; i++)
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+			data[idx++] = MLX5E_READ_CTR64_CPU(&priv->ipsec->stats,
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+							   mlx5e_ipsec_hw_stats_desc,
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+							   i);
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+	return idx;
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+}
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+
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+MLX5E_DEFINE_STATS_GRP(ipsec_sw, 0);
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+MLX5E_DEFINE_STATS_GRP(ipsec_hw, 0);