~hc/RK356X_SDK_RELEASE.git

..	..	@@ -12,8 +12,23 @@
12	12	#include <linux/interrupt.h>
13	13	#include <linux/kernel.h>
14	14	#include <linux/netdevice.h>
	15	+#include <linux/net_tstamp.h>
15	16	#include <linux/phy.h>
16	17	#include <linux/phylink.h>
	18	+#include <net/flow_offload.h>
	19	+#include <net/page_pool.h>
	20	+#include <linux/bpf.h>
	21	+#include <net/xdp.h>
	22	+
	23	+/* The PacketOffset field is measured in units of 32 bytes and is 3 bits wide,
	24	+ * so the maximum offset is 7 * 32 = 224
	25	+ */
	26	+#define MVPP2_SKB_HEADROOM min(max(XDP_PACKET_HEADROOM, NET_SKB_PAD), 224)
	27	+
	28	+#define MVPP2_XDP_PASS 0
	29	+#define MVPP2_XDP_DROPPED BIT(0)
	30	+#define MVPP2_XDP_TX BIT(1)
	31	+#define MVPP2_XDP_REDIR BIT(2)
17	32
18	33	/* Fifo Registers */
19	34	#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
..	..	@@ -101,6 +116,7 @@
101	116	#define MVPP2_CLS_FLOW_TBL1_REG 0x1828
102	117	#define MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK 0x7
103	118	#define MVPP2_CLS_FLOW_TBL1_N_FIELDS(x) (x)
	119	+#define MVPP2_CLS_FLOW_TBL1_LU_TYPE(lu) (((lu) & 0x3f) << 3)
104	120	#define MVPP2_CLS_FLOW_TBL1_PRIO_MASK 0x3f
105	121	#define MVPP2_CLS_FLOW_TBL1_PRIO(x) ((x) << 9)
106	122	#define MVPP2_CLS_FLOW_TBL1_SEQ_MASK 0x7
..	..	@@ -123,13 +139,18 @@
123	139	#define MVPP22_CLS_C2_TCAM_DATA2 0x1b18
124	140	#define MVPP22_CLS_C2_TCAM_DATA3 0x1b1c
125	141	#define MVPP22_CLS_C2_TCAM_DATA4 0x1b20
	142	+#define MVPP22_CLS_C2_LU_TYPE(lu) ((lu) & 0x3f)
126	143	#define MVPP22_CLS_C2_PORT_ID(port) ((port) << 8)
	144	+#define MVPP22_CLS_C2_PORT_MASK (0xff << 8)
	145	+#define MVPP22_CLS_C2_TCAM_INV 0x1b24
	146	+#define MVPP22_CLS_C2_TCAM_INV_BIT BIT(31)
127	147	#define MVPP22_CLS_C2_HIT_CTR 0x1b50
128	148	#define MVPP22_CLS_C2_ACT 0x1b60
129	149	#define MVPP22_CLS_C2_ACT_RSS_EN(act) (((act) & 0x3) << 19)
130	150	#define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13)
131	151	#define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11)
132	152	#define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9)
	153	+#define MVPP22_CLS_C2_ACT_COLOR(act) ((act) & 0x7)
133	154	#define MVPP22_CLS_C2_ATTR0 0x1b64
134	155	#define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24)
135	156	#define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f
..	..	@@ -141,6 +162,8 @@
141	162	#define MVPP22_CLS_C2_ATTR2 0x1b6c
142	163	#define MVPP22_CLS_C2_ATTR2_RSS_EN BIT(30)
143	164	#define MVPP22_CLS_C2_ATTR3 0x1b70
	165	+#define MVPP22_CLS_C2_TCAM_CTRL 0x1b90
	166	+#define MVPP22_CLS_C2_TCAM_BYPASS_FIFO BIT(0)
144	167
145	168	/* Descriptor Manager Top Registers */
146	169	#define MVPP2_RXQ_NUM_REG 0x2040
..	..	@@ -320,8 +343,26 @@
320	343	#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
321	344	#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
322	345
	346	+/* Packet Processor per-port counters */
	347	+#define MVPP2_OVERRUN_ETH_DROP 0x7000
	348	+#define MVPP2_CLS_ETH_DROP 0x7020
	349	+
323	350	/* Hit counters registers */
324	351	#define MVPP2_CTRS_IDX 0x7040
	352	+#define MVPP22_CTRS_TX_CTR(port, txq) ((txq) \| ((port) << 3) \| BIT(7))
	353	+#define MVPP2_TX_DESC_ENQ_CTR 0x7100
	354	+#define MVPP2_TX_DESC_ENQ_TO_DDR_CTR 0x7104
	355	+#define MVPP2_TX_BUFF_ENQ_TO_DDR_CTR 0x7108
	356	+#define MVPP2_TX_DESC_ENQ_HW_FWD_CTR 0x710c
	357	+#define MVPP2_RX_DESC_ENQ_CTR 0x7120
	358	+#define MVPP2_TX_PKTS_DEQ_CTR 0x7130
	359	+#define MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR 0x7200
	360	+#define MVPP2_TX_PKTS_EARLY_DROP_CTR 0x7204
	361	+#define MVPP2_TX_PKTS_BM_DROP_CTR 0x7208
	362	+#define MVPP2_TX_PKTS_BM_MC_DROP_CTR 0x720c
	363	+#define MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR 0x7220
	364	+#define MVPP2_RX_PKTS_EARLY_DROP_CTR 0x7224
	365	+#define MVPP2_RX_PKTS_BM_DROP_CTR 0x7228
325	366	#define MVPP2_CLS_DEC_TBL_HIT_CTR 0x7700
326	367	#define MVPP2_CLS_FLOW_TBL_HIT_CTR 0x7704
327	368
..	..	@@ -331,6 +372,7 @@
331	372	#define MVPP2_TXP_SCHED_ENQ_MASK 0xff
332	373	#define MVPP2_TXP_SCHED_DISQ_OFFSET 8
333	374	#define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
	375	+#define MVPP2_TXP_SCHED_FIXED_PRIO_REG 0x8014
334	376	#define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
335	377	#define MVPP2_TXP_SCHED_MTU_REG 0x801c
336	378	#define MVPP2_TXP_MTU_MAX 0x7FFFF
..	..	@@ -388,7 +430,7 @@
388	430	#define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2)
389	431	#define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3)
390	432	#define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4)
391		-#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
	433	+#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
392	434	#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
393	435	#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
394	436	#define MVPP2_GMAC_FC_ADV_EN BIT(9)
..	..	@@ -401,8 +443,8 @@
401	443	#define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1)
402	444	#define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2)
403	445	#define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3)
404		-#define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(6)
405		-#define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(7)
	446	+#define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(4)
	447	+#define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(5)
406	448	#define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11)
407	449	#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
408	450	#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
..	..	@@ -420,8 +462,12 @@
420	462	#define MVPP22_CTRL4_DP_CLK_SEL BIT(5)
421	463	#define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6)
422	464	#define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7)
	465	+#define MVPP22_GMAC_INT_SUM_STAT 0xa0
	466	+#define MVPP22_GMAC_INT_SUM_STAT_INTERNAL BIT(1)
	467	+#define MVPP22_GMAC_INT_SUM_STAT_PTP BIT(2)
423	468	#define MVPP22_GMAC_INT_SUM_MASK 0xa4
424	469	#define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
	470	+#define MVPP22_GMAC_INT_SUM_MASK_PTP BIT(2)
425	471
426	472	/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
427	473	* relative to port->base.
..	..	@@ -429,6 +475,8 @@
429	475	#define MVPP22_XLG_CTRL0_REG 0x100
430	476	#define MVPP22_XLG_CTRL0_PORT_EN BIT(0)
431	477	#define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1)
	478	+#define MVPP22_XLG_CTRL0_FORCE_LINK_DOWN BIT(2)
	479	+#define MVPP22_XLG_CTRL0_FORCE_LINK_PASS BIT(3)
432	480	#define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7)
433	481	#define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8)
434	482	#define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14)
..	..	@@ -445,9 +493,13 @@
445	493	#define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
446	494	#define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
447	495	#define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13)
	496	+#define MVPP22_XLG_EXT_INT_STAT 0x158
	497	+#define MVPP22_XLG_EXT_INT_STAT_XLG BIT(1)
	498	+#define MVPP22_XLG_EXT_INT_STAT_PTP BIT(7)
448	499	#define MVPP22_XLG_EXT_INT_MASK 0x15c
449	500	#define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1)
450	501	#define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2)
	502	+#define MVPP22_XLG_EXT_INT_MASK_PTP BIT(7)
451	503	#define MVPP22_XLG_CTRL4_REG 0x184
452	504	#define MVPP22_XLG_CTRL4_FWD_FC BIT(5)
453	505	#define MVPP22_XLG_CTRL4_FWD_PFC BIT(6)
..	..	@@ -457,6 +509,70 @@
457	509	/* SMI registers. PPv2.2 only, relative to priv->iface_base. */
458	510	#define MVPP22_SMI_MISC_CFG_REG 0x1204
459	511	#define MVPP22_SMI_POLLING_EN BIT(10)
	512	+
	513	+/* TAI registers, PPv2.2 only, relative to priv->iface_base */
	514	+#define MVPP22_TAI_INT_CAUSE 0x1400
	515	+#define MVPP22_TAI_INT_MASK 0x1404
	516	+#define MVPP22_TAI_CR0 0x1408
	517	+#define MVPP22_TAI_CR1 0x140c
	518	+#define MVPP22_TAI_TCFCR0 0x1410
	519	+#define MVPP22_TAI_TCFCR1 0x1414
	520	+#define MVPP22_TAI_TCFCR2 0x1418
	521	+#define MVPP22_TAI_FATWR 0x141c
	522	+#define MVPP22_TAI_TOD_STEP_NANO_CR 0x1420
	523	+#define MVPP22_TAI_TOD_STEP_FRAC_HIGH 0x1424
	524	+#define MVPP22_TAI_TOD_STEP_FRAC_LOW 0x1428
	525	+#define MVPP22_TAI_TAPDC_HIGH 0x142c
	526	+#define MVPP22_TAI_TAPDC_LOW 0x1430
	527	+#define MVPP22_TAI_TGTOD_SEC_HIGH 0x1434
	528	+#define MVPP22_TAI_TGTOD_SEC_MED 0x1438
	529	+#define MVPP22_TAI_TGTOD_SEC_LOW 0x143c
	530	+#define MVPP22_TAI_TGTOD_NANO_HIGH 0x1440
	531	+#define MVPP22_TAI_TGTOD_NANO_LOW 0x1444
	532	+#define MVPP22_TAI_TGTOD_FRAC_HIGH 0x1448
	533	+#define MVPP22_TAI_TGTOD_FRAC_LOW 0x144c
	534	+#define MVPP22_TAI_TLV_SEC_HIGH 0x1450
	535	+#define MVPP22_TAI_TLV_SEC_MED 0x1454
	536	+#define MVPP22_TAI_TLV_SEC_LOW 0x1458
	537	+#define MVPP22_TAI_TLV_NANO_HIGH 0x145c
	538	+#define MVPP22_TAI_TLV_NANO_LOW 0x1460
	539	+#define MVPP22_TAI_TLV_FRAC_HIGH 0x1464
	540	+#define MVPP22_TAI_TLV_FRAC_LOW 0x1468
	541	+#define MVPP22_TAI_TCV0_SEC_HIGH 0x146c
	542	+#define MVPP22_TAI_TCV0_SEC_MED 0x1470
	543	+#define MVPP22_TAI_TCV0_SEC_LOW 0x1474
	544	+#define MVPP22_TAI_TCV0_NANO_HIGH 0x1478
	545	+#define MVPP22_TAI_TCV0_NANO_LOW 0x147c
	546	+#define MVPP22_TAI_TCV0_FRAC_HIGH 0x1480
	547	+#define MVPP22_TAI_TCV0_FRAC_LOW 0x1484
	548	+#define MVPP22_TAI_TCV1_SEC_HIGH 0x1488
	549	+#define MVPP22_TAI_TCV1_SEC_MED 0x148c
	550	+#define MVPP22_TAI_TCV1_SEC_LOW 0x1490
	551	+#define MVPP22_TAI_TCV1_NANO_HIGH 0x1494
	552	+#define MVPP22_TAI_TCV1_NANO_LOW 0x1498
	553	+#define MVPP22_TAI_TCV1_FRAC_HIGH 0x149c
	554	+#define MVPP22_TAI_TCV1_FRAC_LOW 0x14a0
	555	+#define MVPP22_TAI_TCSR 0x14a4
	556	+#define MVPP22_TAI_TUC_LSB 0x14a8
	557	+#define MVPP22_TAI_GFM_SEC_HIGH 0x14ac
	558	+#define MVPP22_TAI_GFM_SEC_MED 0x14b0
	559	+#define MVPP22_TAI_GFM_SEC_LOW 0x14b4
	560	+#define MVPP22_TAI_GFM_NANO_HIGH 0x14b8
	561	+#define MVPP22_TAI_GFM_NANO_LOW 0x14bc
	562	+#define MVPP22_TAI_GFM_FRAC_HIGH 0x14c0
	563	+#define MVPP22_TAI_GFM_FRAC_LOW 0x14c4
	564	+#define MVPP22_TAI_PCLK_DA_HIGH 0x14c8
	565	+#define MVPP22_TAI_PCLK_DA_LOW 0x14cc
	566	+#define MVPP22_TAI_CTCR 0x14d0
	567	+#define MVPP22_TAI_PCLK_CCC_HIGH 0x14d4
	568	+#define MVPP22_TAI_PCLK_CCC_LOW 0x14d8
	569	+#define MVPP22_TAI_DTC_HIGH 0x14dc
	570	+#define MVPP22_TAI_DTC_LOW 0x14e0
	571	+#define MVPP22_TAI_CCC_HIGH 0x14e4
	572	+#define MVPP22_TAI_CCC_LOW 0x14e8
	573	+#define MVPP22_TAI_ICICE 0x14f4
	574	+#define MVPP22_TAI_ICICC_LOW 0x14f8
	575	+#define MVPP22_TAI_TUC_MSB 0x14fc
460	576
461	577	#define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00)
462	578
..	..	@@ -480,8 +596,49 @@
480	596	/* XPCS registers. PPv2.2 only */
481	597	#define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
482	598	#define MVPP22_XPCS_CFG0 0x0
	599	+#define MVPP22_XPCS_CFG0_RESET_DIS BIT(0)
483	600	#define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3)
484	601	#define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5)
	602	+
	603	+/* PTP registers. PPv2.2 only */
	604	+#define MVPP22_PTP_BASE(port) (0x7800 + (port * 0x1000))
	605	+#define MVPP22_PTP_INT_CAUSE 0x00
	606	+#define MVPP22_PTP_INT_CAUSE_QUEUE1 BIT(6)
	607	+#define MVPP22_PTP_INT_CAUSE_QUEUE0 BIT(5)
	608	+#define MVPP22_PTP_INT_MASK 0x04
	609	+#define MVPP22_PTP_INT_MASK_QUEUE1 BIT(6)
	610	+#define MVPP22_PTP_INT_MASK_QUEUE0 BIT(5)
	611	+#define MVPP22_PTP_GCR 0x08
	612	+#define MVPP22_PTP_GCR_RX_RESET BIT(13)
	613	+#define MVPP22_PTP_GCR_TX_RESET BIT(1)
	614	+#define MVPP22_PTP_GCR_TSU_ENABLE BIT(0)
	615	+#define MVPP22_PTP_TX_Q0_R0 0x0c
	616	+#define MVPP22_PTP_TX_Q0_R1 0x10
	617	+#define MVPP22_PTP_TX_Q0_R2 0x14
	618	+#define MVPP22_PTP_TX_Q1_R0 0x18
	619	+#define MVPP22_PTP_TX_Q1_R1 0x1c
	620	+#define MVPP22_PTP_TX_Q1_R2 0x20
	621	+#define MVPP22_PTP_TPCR 0x24
	622	+#define MVPP22_PTP_V1PCR 0x28
	623	+#define MVPP22_PTP_V2PCR 0x2c
	624	+#define MVPP22_PTP_Y1731PCR 0x30
	625	+#define MVPP22_PTP_NTPTSPCR 0x34
	626	+#define MVPP22_PTP_NTPRXPCR 0x38
	627	+#define MVPP22_PTP_NTPTXPCR 0x3c
	628	+#define MVPP22_PTP_WAMPPCR 0x40
	629	+#define MVPP22_PTP_NAPCR 0x44
	630	+#define MVPP22_PTP_FAPCR 0x48
	631	+#define MVPP22_PTP_CAPCR 0x50
	632	+#define MVPP22_PTP_ATAPCR 0x54
	633	+#define MVPP22_PTP_ACTAPCR 0x58
	634	+#define MVPP22_PTP_CATAPCR 0x5c
	635	+#define MVPP22_PTP_CACTAPCR 0x60
	636	+#define MVPP22_PTP_AITAPCR 0x64
	637	+#define MVPP22_PTP_CAITAPCR 0x68
	638	+#define MVPP22_PTP_CITAPCR 0x6c
	639	+#define MVPP22_PTP_NTP_OFF_HIGH 0x70
	640	+#define MVPP22_PTP_NTP_OFF_LOW 0x74
	641	+#define MVPP22_PTP_TX_PIPE_STATUS_DELAY 0x78
485	642
486	643	/* System controller registers. Accessed through a regmap. */
487	644	#define GENCONF_SOFT_RESET1 0x1108
..	..	@@ -548,8 +705,8 @@
548	705	#define MVPP2_MAX_TSO_SEGS 300
549	706	#define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
550	707
551		-/* Dfault number of RXQs in use */
552		-#define MVPP2_DEFAULT_RXQ 1
	708	+/* Max number of RXQs per port */
	709	+#define MVPP2_PORT_MAX_RXQ 32
553	710
554	711	/* Max number of Rx descriptors */
555	712	#define MVPP2_MAX_RXD_MAX 1024
..	..	@@ -597,16 +754,25 @@
597	754	ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
598	755	ETH_HLEN + ETH_FCS_LEN, cache_line_size())
599	756
600		-#define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
	757	+#define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + MVPP2_SKB_HEADROOM)
601	758	#define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
602	759	#define MVPP2_RX_MAX_PKT_SIZE(total_size) \
603		- ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
	760	+ ((total_size) - MVPP2_SKB_HEADROOM - MVPP2_SKB_SHINFO_SIZE)
	761	+
	762	+#define MVPP2_MAX_RX_BUF_SIZE (PAGE_SIZE - MVPP2_SKB_SHINFO_SIZE - MVPP2_SKB_HEADROOM)
604	763
605	764	#define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
606	765	#define MVPP2_BIT_TO_WORD(bit) ((bit) / 32)
607	766	#define MVPP2_BIT_IN_WORD(bit) ((bit) % 32)
608	767
	768	+#define MVPP2_N_PRS_FLOWS 52
	769	+#define MVPP2_N_RFS_ENTRIES_PER_FLOW 4
	770	+
	771	+/* There are 7 supported high-level flows */
	772	+#define MVPP2_N_RFS_RULES (MVPP2_N_RFS_ENTRIES_PER_FLOW * 7)
	773	+
609	774	/* RSS constants */
	775	+#define MVPP22_N_RSS_TABLES 8
610	776	#define MVPP22_RSS_TABLE_ENTRIES 32
611	777
612	778	/* IPv6 max L3 address size */
..	..	@@ -614,6 +780,7 @@
614	780
615	781	/* Port flags */
616	782	#define MVPP2_F_LOOPBACK BIT(0)
	783	+#define MVPP2_F_DT_COMPAT BIT(1)
617	784
618	785	/* Marvell tag types */
619	786	enum mvpp2_tag_type {
..	..	@@ -638,20 +805,58 @@
638	805	MVPP2_PRS_L3_BROAD_CAST
639	806	};
640	807
	808	+/* PTP descriptor constants. The low bits of the descriptor are stored
	809	+ * separately from the high bits.
	810	+ */
	811	+#define MVPP22_PTP_DESC_MASK_LOW 0xfff
	812	+
	813	+/* PTPAction */
	814	+enum mvpp22_ptp_action {
	815	+ MVPP22_PTP_ACTION_NONE = 0,
	816	+ MVPP22_PTP_ACTION_FORWARD = 1,
	817	+ MVPP22_PTP_ACTION_CAPTURE = 3,
	818	+ /* The following have not been verified */
	819	+ MVPP22_PTP_ACTION_ADDTIME = 4,
	820	+ MVPP22_PTP_ACTION_ADDCORRECTEDTIME = 5,
	821	+ MVPP22_PTP_ACTION_CAPTUREADDTIME = 6,
	822	+ MVPP22_PTP_ACTION_CAPTUREADDCORRECTEDTIME = 7,
	823	+ MVPP22_PTP_ACTION_ADDINGRESSTIME = 8,
	824	+ MVPP22_PTP_ACTION_CAPTUREADDINGRESSTIME = 9,
	825	+ MVPP22_PTP_ACTION_CAPTUREINGRESSTIME = 10,
	826	+};
	827	+
	828	+/* PTPPacketFormat */
	829	+enum mvpp22_ptp_packet_format {
	830	+ MVPP22_PTP_PKT_FMT_PTPV2 = 0,
	831	+ MVPP22_PTP_PKT_FMT_PTPV1 = 1,
	832	+ MVPP22_PTP_PKT_FMT_Y1731 = 2,
	833	+ MVPP22_PTP_PKT_FMT_NTPTS = 3,
	834	+ MVPP22_PTP_PKT_FMT_NTPRX = 4,
	835	+ MVPP22_PTP_PKT_FMT_NTPTX = 5,
	836	+ MVPP22_PTP_PKT_FMT_TWAMP = 6,
	837	+};
	838	+
	839	+#define MVPP22_PTP_ACTION(x) (((x) & 15) << 0)
	840	+#define MVPP22_PTP_PACKETFORMAT(x) (((x) & 7) << 4)
	841	+#define MVPP22_PTP_MACTIMESTAMPINGEN BIT(11)
	842	+#define MVPP22_PTP_TIMESTAMPENTRYID(x) (((x) & 31) << 12)
	843	+#define MVPP22_PTP_TIMESTAMPQUEUESELECT BIT(18)
	844	+
641	845	/* BM constants */
642	846	#define MVPP2_BM_JUMBO_BUF_NUM 512
643	847	#define MVPP2_BM_LONG_BUF_NUM 1024
644	848	#define MVPP2_BM_SHORT_BUF_NUM 2048
645	849	#define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
646	850	#define MVPP2_BM_POOL_PTR_ALIGN 128
	851	+#define MVPP2_BM_MAX_POOLS 8
647	852
648	853	/* BM cookie (32 bits) definition */
649	854	#define MVPP2_BM_COOKIE_POOL_OFFS 8
650	855	#define MVPP2_BM_COOKIE_CPU_OFFS 24
651	856
652		-#define MVPP2_BM_SHORT_FRAME_SIZE 512
653		-#define MVPP2_BM_LONG_FRAME_SIZE 2048
654		-#define MVPP2_BM_JUMBO_FRAME_SIZE 10240
	857	+#define MVPP2_BM_SHORT_FRAME_SIZE 736 /* frame size 128 */
	858	+#define MVPP2_BM_LONG_FRAME_SIZE 2240 /* frame size 1664 */
	859	+#define MVPP2_BM_JUMBO_FRAME_SIZE 10432 /* frame size 9856 */
655	860	/* BM short pool packet size
656	861	* These value assure that for SWF the total number
657	862	* of bytes allocated for each buffer will be 512
..	..	@@ -663,7 +868,7 @@
663	868	#define MVPP21_ADDR_SPACE_SZ 0
664	869	#define MVPP22_ADDR_SPACE_SZ SZ_64K
665	870
666		-#define MVPP2_MAX_THREADS 8
	871	+#define MVPP2_MAX_THREADS 9
667	872	#define MVPP2_MAX_QVECS MVPP2_MAX_THREADS
668	873
669	874	/* GMAC MIB Counters register definitions */
..	..	@@ -704,7 +909,36 @@
704	909
705	910	#define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40)
706	911
	912	+/* Buffer header info bits */
	913	+#define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff
	914	+#define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
	915	+#define MVPP2_B_HDR_INFO_LAST_OFFS 12
	916	+#define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)
	917	+#define MVPP2_B_HDR_INFO_IS_LAST(info) \
	918	+ (((info) & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
	919	+
	920	+struct mvpp2_tai;
	921	+
707	922	/* Definitions */
	923	+struct mvpp2_dbgfs_entries;
	924	+
	925	+struct mvpp2_rss_table {
	926	+ u32 indir[MVPP22_RSS_TABLE_ENTRIES];
	927	+};
	928	+
	929	+struct mvpp2_buff_hdr {
	930	+ __le32 next_phys_addr;
	931	+ __le32 next_dma_addr;
	932	+ __le16 byte_count;
	933	+ __le16 info;
	934	+ __le16 reserved1; /* bm_qset (for future use, BM) */
	935	+ u8 next_phys_addr_high;
	936	+ u8 next_dma_addr_high;
	937	+ __le16 reserved2;
	938	+ __le16 reserved3;
	939	+ __le16 reserved4;
	940	+ __le16 reserved5;
	941	+};
708	942
709	943	/* Shared Packet Processor resources */
710	944	struct mvpp2 {
..	..	@@ -734,9 +968,18 @@
734	968	/* List of pointers to port structures */
735	969	int port_count;
736	970	struct mvpp2_port *port_list[MVPP2_MAX_PORTS];
	971	+ struct mvpp2_tai *tai;
	972	+
	973	+ /* Number of Tx threads used */
	974	+ unsigned int nthreads;
	975	+ /* Map of threads needing locking */
	976	+ unsigned long lock_map;
737	977
738	978	/* Aggregated TXQs */
739	979	struct mvpp2_tx_queue *aggr_txqs;
	980	+
	981	+ /* Are we using page_pool with per-cpu pools? */
	982	+ int percpu_pools;
740	983
741	984	/* BM pools */
742	985	struct mvpp2_bm_pool *bm_pools;
..	..	@@ -761,6 +1004,15 @@
761	1004
762	1005	/* Debugfs root entry */
763	1006	struct dentry *dbgfs_dir;
	1007	+
	1008	+ /* Debugfs entries private data */
	1009	+ struct mvpp2_dbgfs_entries *dbgfs_entries;
	1010	+
	1011	+ /* RSS Indirection tables */
	1012	+ struct mvpp2_rss_table *rss_tables[MVPP22_N_RSS_TABLES];
	1013	+
	1014	+ /* page_pool allocator */
	1015	+ struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ];
764	1016	};
765	1017
766	1018	struct mvpp2_pcpu_stats {
..	..	@@ -769,14 +1021,21 @@
769	1021	u64 rx_bytes;
770	1022	u64 tx_packets;
771	1023	u64 tx_bytes;
	1024	+ /* XDP */
	1025	+ u64 xdp_redirect;
	1026	+ u64 xdp_pass;
	1027	+ u64 xdp_drop;
	1028	+ u64 xdp_xmit;
	1029	+ u64 xdp_xmit_err;
	1030	+ u64 xdp_tx;
	1031	+ u64 xdp_tx_err;
772	1032	};
773	1033
774	1034	/* Per-CPU port control */
775	1035	struct mvpp2_port_pcpu {
776	1036	struct hrtimer tx_done_timer;
	1037	+ struct net_device *dev;
777	1038	bool timer_scheduled;
778		- /* Tasklet for egress finalization */
779		- struct tasklet_struct tx_done_tasklet;
780	1039	};
781	1040
782	1041	struct mvpp2_queue_vector {
..	..	@@ -789,17 +1048,54 @@
789	1048	int nrxqs;
790	1049	u32 pending_cause_rx;
791	1050	struct mvpp2_port *port;
	1051	+ struct cpumask *mask;
	1052	+};
	1053	+
	1054	+/* Internal represention of a Flow Steering rule */
	1055	+struct mvpp2_rfs_rule {
	1056	+ /* Rule location inside the flow*/
	1057	+ int loc;
	1058	+
	1059	+ /* Flow type, such as TCP_V4_FLOW, IP6_FLOW, etc. */
	1060	+ int flow_type;
	1061	+
	1062	+ /* Index of the C2 TCAM entry handling this rule */
	1063	+ int c2_index;
	1064	+
	1065	+ /* Header fields that needs to be extracted to match this flow */
	1066	+ u16 hek_fields;
	1067	+
	1068	+ /* CLS engine : only c2 is supported for now. */
	1069	+ u8 engine;
	1070	+
	1071	+ /* TCAM key and mask for C2-based steering. These fields should be
	1072	+ * encapsulated in a union should we add more engines.
	1073	+ */
	1074	+ u64 c2_tcam;
	1075	+ u64 c2_tcam_mask;
	1076	+
	1077	+ struct flow_rule *flow;
	1078	+};
	1079	+
	1080	+struct mvpp2_ethtool_fs {
	1081	+ struct mvpp2_rfs_rule rule;
	1082	+ struct ethtool_rxnfc rxnfc;
	1083	+};
	1084	+
	1085	+struct mvpp2_hwtstamp_queue {
	1086	+ struct sk_buff *skb[32];
	1087	+ u8 next;
792	1088	};
793	1089
794	1090	struct mvpp2_port {
795	1091	u8 id;
796	1092
797	1093	/* Index of the port from the "group of ports" complex point
798		- * of view
	1094	+ * of view. This is specific to PPv2.2.
799	1095	*/
800	1096	int gop_id;
801	1097
802		- int link_irq;
	1098	+ int port_irq;
803	1099
804	1100	struct mvpp2 *priv;
805	1101
..	..	@@ -819,10 +1115,18 @@
819	1115	unsigned int ntxqs;
820	1116	struct net_device *dev;
821	1117
	1118	+ struct bpf_prog *xdp_prog;
	1119	+
822	1120	int pkt_size;
823	1121
824	1122	/* Per-CPU port control */
825	1123	struct mvpp2_port_pcpu __percpu *pcpu;
	1124	+
	1125	+ /* Protect the BM refills and the Tx paths when a thread is used on more
	1126	+ * than a single CPU.
	1127	+ */
	1128	+ spinlock_t bm_lock[MVPP2_MAX_THREADS];
	1129	+ spinlock_t tx_lock[MVPP2_MAX_THREADS];
826	1130
827	1131	/* Flags */
828	1132	unsigned long flags;
..	..	@@ -832,6 +1136,8 @@
832	1136	struct mvpp2_pcpu_stats __percpu *stats;
833	1137	u64 *ethtool_stats;
834	1138
	1139	+ unsigned long state;
	1140	+
835	1141	/* Per-port work and its lock to gather hardware statistics */
836	1142	struct mutex gather_stats_lock;
837	1143	struct delayed_work stats_work;
..	..	@@ -840,6 +1146,8 @@
840	1146
841	1147	phy_interface_t phy_interface;
842	1148	struct phylink *phylink;
	1149	+ struct phylink_config phylink_config;
	1150	+ struct phylink_pcs phylink_pcs;
843	1151	struct phy *comphy;
844	1152
845	1153	struct mvpp2_bm_pool *pool_long;
..	..	@@ -854,8 +1162,19 @@
854	1162
855	1163	u32 tx_time_coal;
856	1164
857		- /* RSS indirection table */
858		- u32 indir[MVPP22_RSS_TABLE_ENTRIES];
	1165	+ /* List of steering rules active on that port */
	1166	+ struct mvpp2_ethtool_fs *rfs_rules[MVPP2_N_RFS_ENTRIES_PER_FLOW];
	1167	+ int n_rfs_rules;
	1168	+
	1169	+ /* Each port has its own view of the rss contexts, so that it can number
	1170	+ * them from 0
	1171	+ */
	1172	+ int rss_ctx[MVPP22_N_RSS_TABLES];
	1173	+
	1174	+ bool hwtstamp;
	1175	+ bool rx_hwtstamp;
	1176	+ enum hwtstamp_tx_types tx_hwtstamp_type;
	1177	+ struct mvpp2_hwtstamp_queue tx_hwtstamp_queue[2];
859	1178	};
860	1179
861	1180	/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
..	..	@@ -924,7 +1243,8 @@
924	1243	u8 packet_offset;
925	1244	u8 phys_txq;
926	1245	__le16 data_size;
927		- __le64 reserved1;
	1246	+ __le32 ptp_descriptor;
	1247	+ __le32 reserved2;
928	1248	__le64 buf_dma_addr_ptp;
929	1249	__le64 buf_cookie_misc;
930	1250	};
..	..	@@ -935,7 +1255,7 @@
935	1255	__le16 reserved1;
936	1256	__le16 data_size;
937	1257	__le32 reserved2;
938		- __le32 reserved3;
	1258	+ __le32 timestamp;
939	1259	__le64 buf_dma_addr_key_hash;
940	1260	__le64 buf_cookie_misc;
941	1261	};
..	..	@@ -957,9 +1277,20 @@
957	1277	};
958	1278	};
959	1279
	1280	+enum mvpp2_tx_buf_type {
	1281	+ MVPP2_TYPE_SKB,
	1282	+ MVPP2_TYPE_XDP_TX,
	1283	+ MVPP2_TYPE_XDP_NDO,
	1284	+};
	1285	+
960	1286	struct mvpp2_txq_pcpu_buf {
	1287	+ enum mvpp2_tx_buf_type type;
	1288	+
961	1289	/* Transmitted SKB */
962		- struct sk_buff *skb;
	1290	+ union {
	1291	+ struct xdp_frame *xdpf;
	1292	+ struct sk_buff *skb;
	1293	+ };
963	1294
964	1295	/* Physical address of transmitted buffer */
965	1296	dma_addr_t dma;
..	..	@@ -970,7 +1301,7 @@
970	1301
971	1302	/* Per-CPU Tx queue control */
972	1303	struct mvpp2_txq_pcpu {
973		- int cpu;
	1304	+ unsigned int thread;
974	1305
975	1306	/* Number of Tx DMA descriptors in the descriptor ring */
976	1307	int size;
..	..	@@ -1058,6 +1389,10 @@
1058	1389
1059	1390	/* Port's logic RXQ number to which physical RXQ is mapped */
1060	1391	int logic_rxq;
	1392	+
	1393	+ /* XDP memory accounting */
	1394	+ struct xdp_rxq_info xdp_rxq_short;
	1395	+ struct xdp_rxq_info xdp_rxq_long;
1061	1396	};
1062	1397
1063	1398	struct mvpp2_bm_pool {
..	..	@@ -1096,16 +1431,41 @@
1096	1431	void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data);
1097	1432	u32 mvpp2_read(struct mvpp2 *priv, u32 offset);
1098	1433
1099		-u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset);
1100		-
1101		-void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, u32 offset, u32 data);
1102		-u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, u32 offset);
1103		-
1104		-void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, int cpu, u32 offset,
1105		- u32 data);
1106		-
1107	1434	void mvpp2_dbgfs_init(struct mvpp2 priv, const char name);
1108	1435
1109	1436	void mvpp2_dbgfs_cleanup(struct mvpp2 *priv);
	1437	+void mvpp2_dbgfs_exit(void);
1110	1438
	1439	+#ifdef CONFIG_MVPP2_PTP
	1440	+int mvpp22_tai_probe(struct device dev, struct mvpp2 priv);
	1441	+void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp,
	1442	+ struct skb_shared_hwtstamps *hwtstamp);
	1443	+void mvpp22_tai_start(struct mvpp2_tai *tai);
	1444	+void mvpp22_tai_stop(struct mvpp2_tai *tai);
	1445	+int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai);
	1446	+#else
	1447	+static inline int mvpp22_tai_probe(struct device dev, struct mvpp2 priv)
	1448	+{
	1449	+ return 0;
	1450	+}
	1451	+static inline void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp,
	1452	+ struct skb_shared_hwtstamps *hwtstamp)
	1453	+{
	1454	+}
	1455	+static inline void mvpp22_tai_start(struct mvpp2_tai *tai)
	1456	+{
	1457	+}
	1458	+static inline void mvpp22_tai_stop(struct mvpp2_tai *tai)
	1459	+{
	1460	+}
	1461	+static inline int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai)
	1462	+{
	1463	+ return -1;
	1464	+}
	1465	+#endif
	1466	+
	1467	+static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port)
	1468	+{
	1469	+ return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;
	1470	+}
1111	1471	#endif