| .. | .. |
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| 12 | 12 | #include "igb.h" |
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| 13 | 13 | |
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| 14 | 14 | static s32 igb_set_default_fc(struct e1000_hw *hw); |
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| 15 | | -static s32 igb_set_fc_watermarks(struct e1000_hw *hw); |
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| 15 | +static void igb_set_fc_watermarks(struct e1000_hw *hw); |
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| 16 | 16 | |
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| 17 | 17 | /** |
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| 18 | 18 | * igb_get_bus_info_pcie - Get PCIe bus information |
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| .. | .. |
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| 166 | 166 | * @vlan: VLAN id to add or remove |
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| 167 | 167 | * @vind: VMDq output index that maps queue to VLAN id |
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| 168 | 168 | * @vlan_on: if true add filter, if false remove |
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| 169 | + * @vlvf_bypass: skip VLVF if no match is found |
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| 169 | 170 | * |
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| 170 | 171 | * Sets or clears a bit in the VLAN filter table array based on VLAN id |
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| 171 | 172 | * and if we are adding or removing the filter |
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| .. | .. |
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| 425 | 426 | static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
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| 426 | 427 | { |
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| 427 | 428 | u32 hash_value, hash_mask; |
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| 428 | | - u8 bit_shift = 0; |
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| 429 | + u8 bit_shift = 1; |
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| 429 | 430 | |
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| 430 | 431 | /* Register count multiplied by bits per register */ |
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| 431 | 432 | hash_mask = (hw->mac.mta_reg_count * 32) - 1; |
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| .. | .. |
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| 433 | 434 | /* For a mc_filter_type of 0, bit_shift is the number of left-shifts |
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| 434 | 435 | * where 0xFF would still fall within the hash mask. |
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| 435 | 436 | */ |
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| 436 | | - while (hash_mask >> bit_shift != 0xFF) |
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| 437 | + while (hash_mask >> bit_shift != 0xFF && bit_shift < 4) |
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| 437 | 438 | bit_shift++; |
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| 438 | 439 | |
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| 439 | 440 | /* The portion of the address that is used for the hash table |
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| .. | .. |
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| 687 | 688 | |
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| 688 | 689 | wr32(E1000_FCTTV, hw->fc.pause_time); |
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| 689 | 690 | |
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| 690 | | - ret_val = igb_set_fc_watermarks(hw); |
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| 691 | + igb_set_fc_watermarks(hw); |
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| 691 | 692 | |
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| 692 | 693 | out: |
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| 693 | 694 | |
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| .. | .. |
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| 723 | 724 | * flow control XON frame transmission is enabled, then set XON frame |
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| 724 | 725 | * tansmission as well. |
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| 725 | 726 | **/ |
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| 726 | | -static s32 igb_set_fc_watermarks(struct e1000_hw *hw) |
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| 727 | +static void igb_set_fc_watermarks(struct e1000_hw *hw) |
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| 727 | 728 | { |
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| 728 | | - s32 ret_val = 0; |
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| 729 | 729 | u32 fcrtl = 0, fcrth = 0; |
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| 730 | 730 | |
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| 731 | 731 | /* Set the flow control receive threshold registers. Normally, |
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| .. | .. |
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| 747 | 747 | } |
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| 748 | 748 | wr32(E1000_FCRTL, fcrtl); |
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| 749 | 749 | wr32(E1000_FCRTH, fcrth); |
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| 750 | | - |
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| 751 | | - return ret_val; |
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| 752 | 750 | } |
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| 753 | 751 | |
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| 754 | 752 | /** |
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