~hc/RK356X_SDK_RELEASE.git

..	..	@@ -8,6 +8,7 @@
8	8
9	9	/* Maximum buffer lengths for all control queue types */
10	10	#define ICE_AQ_MAX_BUF_LEN 4096
	11	+#define ICE_MBXQ_MAX_BUF_LEN 4096
11	12
12	13	#define ICE_CTL_Q_DESC(R, i) \
13	14	(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
..	..	@@ -18,24 +19,26 @@
18	19
19	20	/* Defines that help manage the driver vs FW API checks.
20	21	* Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
21		- *
22	22	*/
23	23	#define EXP_FW_API_VER_BRANCH 0x00
24		-#define EXP_FW_API_VER_MAJOR 0x00
25		-#define EXP_FW_API_VER_MINOR 0x01
	24	+#define EXP_FW_API_VER_MAJOR 0x01
	25	+#define EXP_FW_API_VER_MINOR 0x05
26	26
27	27	/* Different control queue types: These are mainly for SW consumption. */
28	28	enum ice_ctl_q {
29	29	ICE_CTL_Q_UNKNOWN = 0,
30	30	ICE_CTL_Q_ADMIN,
	31	+ ICE_CTL_Q_MAILBOX,
31	32	};
32	33
33	34	/* Control Queue timeout settings - max delay 1s */
34	35	#define ICE_CTL_Q_SQ_CMD_TIMEOUT 10000 /* Count 10000 times */
35	36	#define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */
	37	+#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */
	38	+#define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */
36	39
37	40	struct ice_ctl_q_ring {
38		- void dma_head; / Virtual address to dma head */
	41	+ void dma_head; / Virtual address to DMA head */
39	42	struct ice_dma_mem desc_buf; /* descriptor ring memory */
40	43	void cmd_buf; / command buffer memory */
41	44
..	..	@@ -58,6 +61,7 @@
58	61	u32 bal;
59	62	u32 len_mask;
60	63	u32 len_ena_mask;
	64	+ u32 len_crit_mask;
61	65	u32 head_mask;
62	66	};
63	67
..	..	@@ -79,6 +83,7 @@
79	83	/* Control Queue information */
80	84	struct ice_ctl_q_info {
81	85	enum ice_ctl_q qtype;
	86	+ enum ice_aq_err rq_last_status; /* last status on receive queue */
82	87	struct ice_ctl_q_ring rq; /* receive queue */
83	88	struct ice_ctl_q_ring sq; /* send queue */
84	89	u32 sq_cmd_timeout; /* send queue cmd write back timeout */
..	..	@@ -86,10 +91,9 @@
86	91	u16 num_sq_entries; /* send queue depth */
87	92	u16 rq_buf_size; /* receive queue buffer size */
88	93	u16 sq_buf_size; /* send queue buffer size */
	94	+ enum ice_aq_err sq_last_status; /* last status on send queue */
89	95	struct mutex sq_lock; /* Send queue lock */
90	96	struct mutex rq_lock; /* Receive queue lock */
91		- enum ice_aq_err sq_last_status; /* last status on send queue */
92		- enum ice_aq_err rq_last_status; /* last status on receive queue */
93	97	};
94	98
95	99	#endif /* _ICE_CONTROLQ_H_ */