| .. | .. |
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| 6 | 6 | |
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| 7 | 7 | #include "i40e_type.h" |
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| 8 | 8 | |
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| 9 | | -#define I40E_DCBX_STATUS_NOT_STARTED 0 |
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| 10 | 9 | #define I40E_DCBX_STATUS_IN_PROGRESS 1 |
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| 11 | 10 | #define I40E_DCBX_STATUS_DONE 2 |
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| 12 | | -#define I40E_DCBX_STATUS_MULTIPLE_PEERS 3 |
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| 13 | 11 | #define I40E_DCBX_STATUS_DISABLED 7 |
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| 14 | 12 | |
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| 15 | 13 | #define I40E_TLV_TYPE_END 0 |
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| .. | .. |
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| 24 | 22 | #define I40E_CEE_DCBX_OUI 0x001b21 |
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| 25 | 23 | #define I40E_CEE_DCBX_TYPE 2 |
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| 26 | 24 | |
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| 27 | | -#define I40E_CEE_SUBTYPE_CTRL 1 |
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| 28 | 25 | #define I40E_CEE_SUBTYPE_PG_CFG 2 |
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| 29 | 26 | #define I40E_CEE_SUBTYPE_PFC_CFG 3 |
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| 30 | 27 | #define I40E_CEE_SUBTYPE_APP_PRI 4 |
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| 31 | 28 | |
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| 32 | 29 | #define I40E_CEE_MAX_FEAT_TYPE 3 |
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| 30 | +#define I40E_LLDP_CURRENT_STATUS_XL710_OFFSET 0x2B |
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| 31 | +#define I40E_LLDP_CURRENT_STATUS_X722_OFFSET 0x31 |
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| 32 | +#define I40E_LLDP_CURRENT_STATUS_OFFSET 1 |
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| 33 | +#define I40E_LLDP_CURRENT_STATUS_SIZE 1 |
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| 34 | + |
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| 33 | 35 | /* Defines for LLDP TLV header */ |
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| 34 | 36 | #define I40E_LLDP_TLV_LEN_SHIFT 0 |
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| 35 | 37 | #define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT) |
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| .. | .. |
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| 100 | 102 | struct i40e_cee_feat_tlv { |
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| 101 | 103 | struct i40e_cee_tlv_hdr hdr; |
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| 102 | 104 | u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */ |
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| 103 | | -#define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80 |
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| 104 | 105 | #define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40 |
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| 105 | | -#define I40E_CEE_FEAT_TLV_ERR_MASK 0x20 |
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| 106 | 106 | u8 subtype; |
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| 107 | 107 | u8 tlvinfo[1]; |
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| 108 | 108 | }; |
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| .. | .. |
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| 124 | 124 | u8 bridgetype, |
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| 125 | 125 | struct i40e_dcbx_config *dcbcfg); |
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| 126 | 126 | i40e_status i40e_get_dcb_config(struct i40e_hw *hw); |
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| 127 | | -i40e_status i40e_init_dcb(struct i40e_hw *hw); |
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| 127 | +i40e_status i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change); |
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| 128 | 128 | #endif /* _I40E_DCB_H_ */ |
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