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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
....@@ -1,18 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
3
- *
4
- *  This program is free software; you can redistribute it and/or modify it
5
- *  under the terms and conditions of the GNU General Public License,
6
- *  version 2, as published by the Free Software Foundation.
7
- *
8
- *  This program is distributed in the hope it will be useful, but WITHOUT
9
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11
- *  more details.
12
- *
13
- *  The full GNU General Public License is included in this distribution in
14
- *  the file called "COPYING".
15
- *
164  */
175 
186 #include "t4_regs.h"
....@@ -30,6 +18,7 @@
3018 
3119 static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
3220 	{ CUDBG_MBOX_LOG, cudbg_collect_mbox_log },
21
+	{ CUDBG_QDESC, cudbg_collect_qdesc },
3322 	{ CUDBG_DEV_LOG, cudbg_collect_fw_devlog },
3423 	{ CUDBG_REG_DUMP, cudbg_collect_reg_dump },
3524 	{ CUDBG_CIM_LA, cudbg_collect_cim_la },
....@@ -77,246 +66,9 @@
7766 	{ CUDBG_HMA_INDIRECT, cudbg_collect_hma_indirect },
7867 };
7968 
80
-static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
81
-{
82
-	struct cudbg_tcam tcam_region = { 0 };
83
-	u32 value, n = 0, len = 0;
84
-
85
-	switch (entity) {
86
-	case CUDBG_REG_DUMP:
87
-		switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
88
-		case CHELSIO_T4:
89
-			len = T4_REGMAP_SIZE;
90
-			break;
91
-		case CHELSIO_T5:
92
-		case CHELSIO_T6:
93
-			len = T5_REGMAP_SIZE;
94
-			break;
95
-		default:
96
-			break;
97
-		}
98
-		break;
99
-	case CUDBG_DEV_LOG:
100
-		len = adap->params.devlog.size;
101
-		break;
102
-	case CUDBG_CIM_LA:
103
-		if (is_t6(adap->params.chip)) {
104
-			len = adap->params.cim_la_size / 10 + 1;
105
-			len *= 10 * sizeof(u32);
106
-		} else {
107
-			len = adap->params.cim_la_size / 8;
108
-			len *= 8 * sizeof(u32);
109
-		}
110
-		len += sizeof(u32); /* for reading CIM LA configuration */
111
-		break;
112
-	case CUDBG_CIM_MA_LA:
113
-		len = 2 * CIM_MALA_SIZE * 5 * sizeof(u32);
114
-		break;
115
-	case CUDBG_CIM_QCFG:
116
-		len = sizeof(struct cudbg_cim_qcfg);
117
-		break;
118
-	case CUDBG_CIM_IBQ_TP0:
119
-	case CUDBG_CIM_IBQ_TP1:
120
-	case CUDBG_CIM_IBQ_ULP:
121
-	case CUDBG_CIM_IBQ_SGE0:
122
-	case CUDBG_CIM_IBQ_SGE1:
123
-	case CUDBG_CIM_IBQ_NCSI:
124
-		len = CIM_IBQ_SIZE * 4 * sizeof(u32);
125
-		break;
126
-	case CUDBG_CIM_OBQ_ULP0:
127
-		len = cudbg_cim_obq_size(adap, 0);
128
-		break;
129
-	case CUDBG_CIM_OBQ_ULP1:
130
-		len = cudbg_cim_obq_size(adap, 1);
131
-		break;
132
-	case CUDBG_CIM_OBQ_ULP2:
133
-		len = cudbg_cim_obq_size(adap, 2);
134
-		break;
135
-	case CUDBG_CIM_OBQ_ULP3:
136
-		len = cudbg_cim_obq_size(adap, 3);
137
-		break;
138
-	case CUDBG_CIM_OBQ_SGE:
139
-		len = cudbg_cim_obq_size(adap, 4);
140
-		break;
141
-	case CUDBG_CIM_OBQ_NCSI:
142
-		len = cudbg_cim_obq_size(adap, 5);
143
-		break;
144
-	case CUDBG_CIM_OBQ_RXQ0:
145
-		len = cudbg_cim_obq_size(adap, 6);
146
-		break;
147
-	case CUDBG_CIM_OBQ_RXQ1:
148
-		len = cudbg_cim_obq_size(adap, 7);
149
-		break;
150
-	case CUDBG_EDC0:
151
-		value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
152
-		if (value & EDRAM0_ENABLE_F) {
153
-			value = t4_read_reg(adap, MA_EDRAM0_BAR_A);
154
-			len = EDRAM0_SIZE_G(value);
155
-		}
156
-		len = cudbg_mbytes_to_bytes(len);
157
-		break;
158
-	case CUDBG_EDC1:
159
-		value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
160
-		if (value & EDRAM1_ENABLE_F) {
161
-			value = t4_read_reg(adap, MA_EDRAM1_BAR_A);
162
-			len = EDRAM1_SIZE_G(value);
163
-		}
164
-		len = cudbg_mbytes_to_bytes(len);
165
-		break;
166
-	case CUDBG_MC0:
167
-		value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
168
-		if (value & EXT_MEM0_ENABLE_F) {
169
-			value = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
170
-			len = EXT_MEM0_SIZE_G(value);
171
-		}
172
-		len = cudbg_mbytes_to_bytes(len);
173
-		break;
174
-	case CUDBG_MC1:
175
-		value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
176
-		if (value & EXT_MEM1_ENABLE_F) {
177
-			value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
178
-			len = EXT_MEM1_SIZE_G(value);
179
-		}
180
-		len = cudbg_mbytes_to_bytes(len);
181
-		break;
182
-	case CUDBG_RSS:
183
-		len = t4_chip_rss_size(adap) * sizeof(u16);
184
-		break;
185
-	case CUDBG_RSS_VF_CONF:
186
-		len = adap->params.arch.vfcount *
187
-		      sizeof(struct cudbg_rss_vf_conf);
188
-		break;
189
-	case CUDBG_PATH_MTU:
190
-		len = NMTUS * sizeof(u16);
191
-		break;
192
-	case CUDBG_PM_STATS:
193
-		len = sizeof(struct cudbg_pm_stats);
194
-		break;
195
-	case CUDBG_HW_SCHED:
196
-		len = sizeof(struct cudbg_hw_sched);
197
-		break;
198
-	case CUDBG_TP_INDIRECT:
199
-		switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
200
-		case CHELSIO_T5:
201
-			n = sizeof(t5_tp_pio_array) +
202
-			    sizeof(t5_tp_tm_pio_array) +
203
-			    sizeof(t5_tp_mib_index_array);
204
-			break;
205
-		case CHELSIO_T6:
206
-			n = sizeof(t6_tp_pio_array) +
207
-			    sizeof(t6_tp_tm_pio_array) +
208
-			    sizeof(t6_tp_mib_index_array);
209
-			break;
210
-		default:
211
-			break;
212
-		}
213
-		n = n / (IREG_NUM_ELEM * sizeof(u32));
214
-		len = sizeof(struct ireg_buf) * n;
215
-		break;
216
-	case CUDBG_SGE_INDIRECT:
217
-		len = sizeof(struct ireg_buf) * 2 +
218
-		      sizeof(struct sge_qbase_reg_field);
219
-		break;
220
-	case CUDBG_ULPRX_LA:
221
-		len = sizeof(struct cudbg_ulprx_la);
222
-		break;
223
-	case CUDBG_TP_LA:
224
-		len = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64);
225
-		break;
226
-	case CUDBG_MEMINFO:
227
-		len = sizeof(struct cudbg_ver_hdr) +
228
-		      sizeof(struct cudbg_meminfo);
229
-		break;
230
-	case CUDBG_CIM_PIF_LA:
231
-		len = sizeof(struct cudbg_cim_pif_la);
232
-		len += 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32);
233
-		break;
234
-	case CUDBG_CLK:
235
-		len = sizeof(struct cudbg_clk_info);
236
-		break;
237
-	case CUDBG_PCIE_INDIRECT:
238
-		n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
239
-		len = sizeof(struct ireg_buf) * n * 2;
240
-		break;
241
-	case CUDBG_PM_INDIRECT:
242
-		n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32));
243
-		len = sizeof(struct ireg_buf) * n * 2;
244
-		break;
245
-	case CUDBG_TID_INFO:
246
-		len = sizeof(struct cudbg_tid_info_region_rev1);
247
-		break;
248
-	case CUDBG_PCIE_CONFIG:
249
-		len = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS;
250
-		break;
251
-	case CUDBG_DUMP_CONTEXT:
252
-		len = cudbg_dump_context_size(adap);
253
-		break;
254
-	case CUDBG_MPS_TCAM:
255
-		len = sizeof(struct cudbg_mps_tcam) *
256
-		      adap->params.arch.mps_tcam_size;
257
-		break;
258
-	case CUDBG_VPD_DATA:
259
-		len = sizeof(struct cudbg_vpd_data);
260
-		break;
261
-	case CUDBG_LE_TCAM:
262
-		cudbg_fill_le_tcam_info(adap, &tcam_region);
263
-		len = sizeof(struct cudbg_tcam) +
264
-		      sizeof(struct cudbg_tid_data) * tcam_region.max_tid;
265
-		break;
266
-	case CUDBG_CCTRL:
267
-		len = sizeof(u16) * NMTUS * NCCTRL_WIN;
268
-		break;
269
-	case CUDBG_MA_INDIRECT:
270
-		if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
271
-			n = sizeof(t6_ma_ireg_array) /
272
-			    (IREG_NUM_ELEM * sizeof(u32));
273
-			len = sizeof(struct ireg_buf) * n * 2;
274
-		}
275
-		break;
276
-	case CUDBG_ULPTX_LA:
277
-		len = sizeof(struct cudbg_ver_hdr) +
278
-		      sizeof(struct cudbg_ulptx_la);
279
-		break;
280
-	case CUDBG_UP_CIM_INDIRECT:
281
-		n = 0;
282
-		if (is_t5(adap->params.chip))
283
-			n = sizeof(t5_up_cim_reg_array) /
284
-			    ((IREG_NUM_ELEM + 1) * sizeof(u32));
285
-		else if (is_t6(adap->params.chip))
286
-			n = sizeof(t6_up_cim_reg_array) /
287
-			    ((IREG_NUM_ELEM + 1) * sizeof(u32));
288
-		len = sizeof(struct ireg_buf) * n;
289
-		break;
290
-	case CUDBG_PBT_TABLE:
291
-		len = sizeof(struct cudbg_pbt_tables);
292
-		break;
293
-	case CUDBG_MBOX_LOG:
294
-		len = sizeof(struct cudbg_mbox_log) * adap->mbox_log->size;
295
-		break;
296
-	case CUDBG_HMA_INDIRECT:
297
-		if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
298
-			n = sizeof(t6_hma_ireg_array) /
299
-			    (IREG_NUM_ELEM * sizeof(u32));
300
-			len = sizeof(struct ireg_buf) * n;
301
-		}
302
-		break;
303
-	case CUDBG_HMA:
304
-		value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
305
-		if (value & HMA_MUX_F) {
306
-			/* In T6, there's no MC1.  So, HMA shares MC1
307
-			 * address space.
308
-			 */
309
-			value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
310
-			len = EXT_MEM1_SIZE_G(value);
311
-		}
312
-		len = cudbg_mbytes_to_bytes(len);
313
-		break;
314
-	default:
315
-		break;
316
-	}
317
-
318
-	return len;
319
-}
69
+static const struct cxgb4_collect_entity cxgb4_collect_flash_dump[] = {
70
+	{ CUDBG_FLASH, cudbg_collect_flash },
71
+};
32072 
32173 u32 cxgb4_get_dump_length(struct adapter *adap, u32 flag)
32274 {
....@@ -327,16 +79,19 @@
32779 	if (flag & CXGB4_ETH_DUMP_HW) {
32880 		for (i = 0; i < ARRAY_SIZE(cxgb4_collect_hw_dump); i++) {
32981 			entity = cxgb4_collect_hw_dump[i].entity;
330
-			len += cxgb4_get_entity_length(adap, entity);
82
+			len += cudbg_get_entity_length(adap, entity);
33183 		}
33284 	}
33385 
33486 	if (flag & CXGB4_ETH_DUMP_MEM) {
33587 		for (i = 0; i < ARRAY_SIZE(cxgb4_collect_mem_dump); i++) {
33688 			entity = cxgb4_collect_mem_dump[i].entity;
337
-			len += cxgb4_get_entity_length(adap, entity);
89
+			len += cudbg_get_entity_length(adap, entity);
33890 		}
33991 	}
92
+
93
+	if (flag & CXGB4_ETH_DUMP_FLASH)
94
+		len += adap->params.sf_size;
34095 
34196 	/* If compression is enabled, a smaller destination buffer is enough */
34297 	wsize = cudbg_get_workspace_size();
....@@ -476,6 +231,13 @@
476231 					   buf,
477232 					   &total_size);
478233 
234
+	if (flag & CXGB4_ETH_DUMP_FLASH)
235
+		cxgb4_cudbg_collect_entity(&cudbg_init, &dbg_buff,
236
+					   cxgb4_collect_flash_dump,
237
+					   ARRAY_SIZE(cxgb4_collect_flash_dump),
238
+					   buf,
239
+					   &total_size);
240
+
479241 	cudbg_free_compress_buff(&cudbg_init);
480242 	cudbg_hdr->data_len = total_size;
481243 	if (cudbg_init.compress_type != CUDBG_COMPRESSION_NONE)