| .. | .. |
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| 38 | 38 | lio_pci_readq(oct, CN6XXX_CIU_SOFT_RST); |
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| 39 | 39 | lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_RST); |
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| 40 | 40 | |
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| 41 | | - /* make sure that the reset is written before starting timer */ |
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| 42 | | - mmiowb(); |
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| 43 | | - |
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| 44 | 41 | /* Wait for 10ms as Octeon resets. */ |
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| 45 | 42 | mdelay(100); |
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| 46 | 43 | |
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| .. | .. |
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| 487 | 484 | |
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| 488 | 485 | /* Disable Interrupts */ |
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| 489 | 486 | writeq(0, cn6xxx->intr_enb_reg64); |
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| 490 | | - |
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| 491 | | - /* make sure interrupts are really disabled */ |
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| 492 | | - mmiowb(); |
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| 493 | 487 | } |
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| 494 | 488 | |
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| 495 | 489 | static void lio_cn6xxx_get_pcie_qlmport(struct octeon_device *oct) |
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| .. | .. |
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| 554 | 548 | value = octeon_read_csr(oct, reg); |
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| 555 | 549 | value &= ~(1 << oq_no); |
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| 556 | 550 | octeon_write_csr(oct, reg, value); |
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| 557 | | - |
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| 558 | | - /* Ensure that the enable register is written. |
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| 559 | | - */ |
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| 560 | | - mmiowb(); |
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| 561 | 551 | |
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| 562 | 552 | spin_unlock(&cn6xxx->lock_for_droq_int_enb_reg); |
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| 563 | 553 | } |
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