| .. | .. |
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| 13 | 13 | #define DRV_NAME "cavium_ptp" |
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| 14 | 14 | |
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| 15 | 15 | #define PCI_DEVICE_ID_CAVIUM_PTP 0xA00C |
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| 16 | +#define PCI_SUBSYS_DEVID_88XX_PTP 0xA10C |
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| 17 | +#define PCI_SUBSYS_DEVID_81XX_PTP 0XA20C |
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| 18 | +#define PCI_SUBSYS_DEVID_83XX_PTP 0xA30C |
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| 16 | 19 | #define PCI_DEVICE_ID_CAVIUM_RST 0xA00E |
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| 17 | 20 | |
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| 18 | 21 | #define PCI_PTP_BAR_NO 0 |
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| .. | .. |
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| 83 | 86 | |
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| 84 | 87 | /** |
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| 85 | 88 | * cavium_ptp_adjfine() - Adjust ptp frequency |
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| 86 | | - * @ptp: PTP clock info |
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| 89 | + * @ptp_info: PTP clock info |
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| 87 | 90 | * @scaled_ppm: how much to adjust by, in parts per million, but with a |
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| 88 | 91 | * 16 bit binary fractional field |
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| 89 | 92 | */ |
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| .. | .. |
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| 131 | 134 | |
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| 132 | 135 | /** |
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| 133 | 136 | * cavium_ptp_adjtime() - Adjust ptp time |
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| 134 | | - * @ptp: PTP clock info |
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| 137 | + * @ptp_info: PTP clock info |
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| 135 | 138 | * @delta: how much to adjust by, in nanosecs |
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| 136 | 139 | */ |
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| 137 | 140 | static int cavium_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta) |
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| .. | .. |
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| 152 | 155 | |
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| 153 | 156 | /** |
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| 154 | 157 | * cavium_ptp_gettime() - Get hardware clock time with adjustment |
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| 155 | | - * @ptp: PTP clock info |
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| 158 | + * @ptp_info: PTP clock info |
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| 156 | 159 | * @ts: timespec |
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| 157 | 160 | */ |
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| 158 | 161 | static int cavium_ptp_gettime(struct ptp_clock_info *ptp_info, |
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| .. | .. |
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| 174 | 177 | |
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| 175 | 178 | /** |
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| 176 | 179 | * cavium_ptp_settime() - Set hardware clock time. Reset adjustment |
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| 177 | | - * @ptp: PTP clock info |
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| 180 | + * @ptp_info: PTP clock info |
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| 178 | 181 | * @ts: timespec |
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| 179 | 182 | */ |
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| 180 | 183 | static int cavium_ptp_settime(struct ptp_clock_info *ptp_info, |
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| .. | .. |
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| 196 | 199 | |
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| 197 | 200 | /** |
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| 198 | 201 | * cavium_ptp_enable() - Request to enable or disable an ancillary feature. |
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| 199 | | - * @ptp: PTP clock info |
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| 202 | + * @ptp_info: PTP clock info |
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| 200 | 203 | * @rq: request |
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| 201 | 204 | * @on: is it on |
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| 202 | 205 | */ |
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| .. | .. |
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| 277 | 280 | writeq(clock_comp, clock->reg_base + PTP_CLOCK_COMP); |
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| 278 | 281 | |
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| 279 | 282 | clock->ptp_clock = ptp_clock_register(&clock->ptp_info, dev); |
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| 280 | | - if (!clock->ptp_clock) { |
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| 281 | | - err = -ENODEV; |
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| 282 | | - goto error_stop; |
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| 283 | | - } |
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| 284 | 283 | if (IS_ERR(clock->ptp_clock)) { |
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| 285 | 284 | err = PTR_ERR(clock->ptp_clock); |
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| 286 | 285 | goto error_stop; |
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| .. | .. |
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| 325 | 324 | } |
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| 326 | 325 | |
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| 327 | 326 | static const struct pci_device_id cavium_ptp_id_table[] = { |
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| 328 | | - { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP) }, |
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| 327 | + { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP, |
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| 328 | + PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_88XX_PTP) }, |
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| 329 | + { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP, |
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| 330 | + PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_81XX_PTP) }, |
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| 331 | + { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP, |
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| 332 | + PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_83XX_PTP) }, |
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| 329 | 333 | { 0, } |
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| 330 | 334 | }; |
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| 331 | 335 | |
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