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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/net/ethernet/amazon/ena/ena_regs_defs.h
....@@ -1,169 +1,130 @@
1
+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
12 /*
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- * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates.
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- *
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- * This software is available to you under a choice of one of two
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- * licenses.  You may choose to be licensed under the terms of the GNU
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- * General Public License (GPL) Version 2, available from the file
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- * COPYING in the main directory of this source tree, or the
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- * BSD license below:
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- *
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- *     Redistribution and use in source and binary forms, with or
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- *     without modification, are permitted provided that the following
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- *     conditions are met:
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- *
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- *      - Redistributions of source code must retain the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer.
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- *
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- *      - Redistributions in binary form must reproduce the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer in the documentation and/or other materials
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- *        provided with the distribution.
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- *
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- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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- * SOFTWARE.
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+ * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
314  */
325 #ifndef _ENA_REGS_H_
336 #define _ENA_REGS_H_
347 
358 enum ena_regs_reset_reason_types {
36
-	ENA_REGS_RESET_NORMAL			= 0,
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-
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-	ENA_REGS_RESET_KEEP_ALIVE_TO		= 1,
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-
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-	ENA_REGS_RESET_ADMIN_TO			= 2,
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-
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-	ENA_REGS_RESET_MISS_TX_CMPL		= 3,
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-
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-	ENA_REGS_RESET_INV_RX_REQ_ID		= 4,
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-
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-	ENA_REGS_RESET_INV_TX_REQ_ID		= 5,
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-
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-	ENA_REGS_RESET_TOO_MANY_RX_DESCS	= 6,
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-
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-	ENA_REGS_RESET_INIT_ERR			= 7,
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-
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-	ENA_REGS_RESET_DRIVER_INVALID_STATE	= 8,
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-
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-	ENA_REGS_RESET_OS_TRIGGER		= 9,
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-
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-	ENA_REGS_RESET_OS_NETDEV_WD		= 10,
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-
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-	ENA_REGS_RESET_SHUTDOWN			= 11,
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-
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-	ENA_REGS_RESET_USER_TRIGGER		= 12,
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-
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-	ENA_REGS_RESET_GENERIC			= 13,
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-
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-	ENA_REGS_RESET_MISS_INTERRUPT		= 14,
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+	ENA_REGS_RESET_NORMAL                       = 0,
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+	ENA_REGS_RESET_KEEP_ALIVE_TO                = 1,
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+	ENA_REGS_RESET_ADMIN_TO                     = 2,
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+	ENA_REGS_RESET_MISS_TX_CMPL                 = 3,
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+	ENA_REGS_RESET_INV_RX_REQ_ID                = 4,
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+	ENA_REGS_RESET_INV_TX_REQ_ID                = 5,
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+	ENA_REGS_RESET_TOO_MANY_RX_DESCS            = 6,
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+	ENA_REGS_RESET_INIT_ERR                     = 7,
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+	ENA_REGS_RESET_DRIVER_INVALID_STATE         = 8,
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+	ENA_REGS_RESET_OS_TRIGGER                   = 9,
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+	ENA_REGS_RESET_OS_NETDEV_WD                 = 10,
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+	ENA_REGS_RESET_SHUTDOWN                     = 11,
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+	ENA_REGS_RESET_USER_TRIGGER                 = 12,
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+	ENA_REGS_RESET_GENERIC                      = 13,
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+	ENA_REGS_RESET_MISS_INTERRUPT               = 14,
6524 };
6625 
6726 /* ena_registers offsets */
68
-#define ENA_REGS_VERSION_OFF		0x0
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-#define ENA_REGS_CONTROLLER_VERSION_OFF		0x4
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-#define ENA_REGS_CAPS_OFF		0x8
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-#define ENA_REGS_CAPS_EXT_OFF		0xc
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-#define ENA_REGS_AQ_BASE_LO_OFF		0x10
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-#define ENA_REGS_AQ_BASE_HI_OFF		0x14
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-#define ENA_REGS_AQ_CAPS_OFF		0x18
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-#define ENA_REGS_ACQ_BASE_LO_OFF		0x20
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-#define ENA_REGS_ACQ_BASE_HI_OFF		0x24
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-#define ENA_REGS_ACQ_CAPS_OFF		0x28
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-#define ENA_REGS_AQ_DB_OFF		0x2c
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-#define ENA_REGS_ACQ_TAIL_OFF		0x30
80
-#define ENA_REGS_AENQ_CAPS_OFF		0x34
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-#define ENA_REGS_AENQ_BASE_LO_OFF		0x38
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-#define ENA_REGS_AENQ_BASE_HI_OFF		0x3c
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-#define ENA_REGS_AENQ_HEAD_DB_OFF		0x40
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-#define ENA_REGS_AENQ_TAIL_OFF		0x44
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-#define ENA_REGS_INTR_MASK_OFF		0x4c
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-#define ENA_REGS_DEV_CTL_OFF		0x54
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-#define ENA_REGS_DEV_STS_OFF		0x58
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-#define ENA_REGS_MMIO_REG_READ_OFF		0x5c
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-#define ENA_REGS_MMIO_RESP_LO_OFF		0x60
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-#define ENA_REGS_MMIO_RESP_HI_OFF		0x64
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-#define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF		0x68
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+
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+/* 0 base */
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+#define ENA_REGS_VERSION_OFF                                0x0
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+#define ENA_REGS_CONTROLLER_VERSION_OFF                     0x4
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+#define ENA_REGS_CAPS_OFF                                   0x8
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+#define ENA_REGS_CAPS_EXT_OFF                               0xc
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+#define ENA_REGS_AQ_BASE_LO_OFF                             0x10
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+#define ENA_REGS_AQ_BASE_HI_OFF                             0x14
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+#define ENA_REGS_AQ_CAPS_OFF                                0x18
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+#define ENA_REGS_ACQ_BASE_LO_OFF                            0x20
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+#define ENA_REGS_ACQ_BASE_HI_OFF                            0x24
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+#define ENA_REGS_ACQ_CAPS_OFF                               0x28
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+#define ENA_REGS_AQ_DB_OFF                                  0x2c
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+#define ENA_REGS_ACQ_TAIL_OFF                               0x30
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+#define ENA_REGS_AENQ_CAPS_OFF                              0x34
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+#define ENA_REGS_AENQ_BASE_LO_OFF                           0x38
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+#define ENA_REGS_AENQ_BASE_HI_OFF                           0x3c
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+#define ENA_REGS_AENQ_HEAD_DB_OFF                           0x40
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+#define ENA_REGS_AENQ_TAIL_OFF                              0x44
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+#define ENA_REGS_INTR_MASK_OFF                              0x4c
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+#define ENA_REGS_DEV_CTL_OFF                                0x54
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+#define ENA_REGS_DEV_STS_OFF                                0x58
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+#define ENA_REGS_MMIO_REG_READ_OFF                          0x5c
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+#define ENA_REGS_MMIO_RESP_LO_OFF                           0x60
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+#define ENA_REGS_MMIO_RESP_HI_OFF                           0x64
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+#define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF                   0x68
9253 
9354 /* version register */
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-#define ENA_REGS_VERSION_MINOR_VERSION_MASK		0xff
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-#define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT		8
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-#define ENA_REGS_VERSION_MAJOR_VERSION_MASK		0xff00
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+#define ENA_REGS_VERSION_MINOR_VERSION_MASK                 0xff
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+#define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT                8
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+#define ENA_REGS_VERSION_MAJOR_VERSION_MASK                 0xff00
9758 
9859 /* controller_version register */
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-#define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK		0xff
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-#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT		8
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-#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK		0xff00
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-#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT		16
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-#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK		0xff0000
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-#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT		24
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-#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK		0xff000000
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+#define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK   0xff
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+#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT     8
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+#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK      0xff00
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+#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT     16
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+#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK      0xff0000
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+#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT           24
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+#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK            0xff000000
10667 
10768 /* caps register */
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-#define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK		0x1
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-#define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT		1
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-#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK		0x3e
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-#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT		8
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-#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK		0xff00
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-#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT		16
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-#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK		0xf0000
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+#define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK        0x1
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+#define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT                   1
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+#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK                    0x3e
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+#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT                  8
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+#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK                   0xff00
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+#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT                    16
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+#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK                     0xf0000
11576 
11677 /* aq_caps register */
117
-#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK		0xffff
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-#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT		16
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-#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK		0xffff0000
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+#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK                      0xffff
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+#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT                16
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+#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK                 0xffff0000
12081 
12182 /* acq_caps register */
122
-#define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK		0xffff
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-#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT		16
124
-#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK		0xffff0000
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+#define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK                    0xffff
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+#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT              16
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+#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK               0xffff0000
12586 
12687 /* aenq_caps register */
127
-#define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK		0xffff
128
-#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT		16
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-#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK		0xffff0000
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+#define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK                  0xffff
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+#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT            16
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+#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK             0xffff0000
13091 
13192 /* dev_ctl register */
132
-#define ENA_REGS_DEV_CTL_DEV_RESET_MASK		0x1
133
-#define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT		1
134
-#define ENA_REGS_DEV_CTL_AQ_RESTART_MASK		0x2
135
-#define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT		2
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-#define ENA_REGS_DEV_CTL_QUIESCENT_MASK		0x4
137
-#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT		3
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-#define ENA_REGS_DEV_CTL_IO_RESUME_MASK		0x8
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-#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT		28
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-#define ENA_REGS_DEV_CTL_RESET_REASON_MASK		0xf0000000
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+#define ENA_REGS_DEV_CTL_DEV_RESET_MASK                     0x1
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+#define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT                   1
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+#define ENA_REGS_DEV_CTL_AQ_RESTART_MASK                    0x2
96
+#define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT                    2
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+#define ENA_REGS_DEV_CTL_QUIESCENT_MASK                     0x4
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+#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT                    3
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+#define ENA_REGS_DEV_CTL_IO_RESUME_MASK                     0x8
100
+#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT                 28
101
+#define ENA_REGS_DEV_CTL_RESET_REASON_MASK                  0xf0000000
141102 
142103 /* dev_sts register */
143
-#define ENA_REGS_DEV_STS_READY_MASK		0x1
144
-#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT		1
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-#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK		0x2
146
-#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT		2
147
-#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK		0x4
148
-#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT		3
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-#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK		0x8
150
-#define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT		4
151
-#define ENA_REGS_DEV_STS_RESET_FINISHED_MASK		0x10
152
-#define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT		5
153
-#define ENA_REGS_DEV_STS_FATAL_ERROR_MASK		0x20
154
-#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT		6
155
-#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK		0x40
156
-#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT		7
157
-#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK		0x80
104
+#define ENA_REGS_DEV_STS_READY_MASK                         0x1
105
+#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT       1
106
+#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK        0x2
107
+#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT          2
108
+#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK           0x4
109
+#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT            3
110
+#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK             0x8
111
+#define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT               4
112
+#define ENA_REGS_DEV_STS_RESET_FINISHED_MASK                0x10
113
+#define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT                  5
114
+#define ENA_REGS_DEV_STS_FATAL_ERROR_MASK                   0x20
115
+#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT  6
116
+#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK   0x40
117
+#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT     7
118
+#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK      0x80
158119 
159120 /* mmio_reg_read register */
160
-#define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK		0xffff
161
-#define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT		16
162
-#define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK		0xffff0000
121
+#define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK                  0xffff
122
+#define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT                16
123
+#define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK                 0xffff0000
163124 
164125 /* rss_ind_entry_update register */
165
-#define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK		0xffff
166
-#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT		16
167
-#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK		0xffff0000
126
+#define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK            0xffff
127
+#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT          16
128
+#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK           0xffff0000
168129 
169
-#endif /*_ENA_REGS_H_ */
130
+#endif /* _ENA_REGS_H_ */