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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/net/ethernet/amazon/ena/ena_eth_com.h
....@@ -1,33 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
12 /*
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- * Copyright 2015 Amazon.com, Inc. or its affiliates.
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- *
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- * This software is available to you under a choice of one of two
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- * licenses.  You may choose to be licensed under the terms of the GNU
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- * General Public License (GPL) Version 2, available from the file
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- * COPYING in the main directory of this source tree, or the
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- * BSD license below:
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- *
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- *     Redistribution and use in source and binary forms, with or
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- *     without modification, are permitted provided that the following
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- *     conditions are met:
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- *
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- *      - Redistributions of source code must retain the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer.
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- *
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- *      - Redistributions in binary form must reproduce the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer in the documentation and/or other materials
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- *        provided with the distribution.
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- *
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- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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- * SOFTWARE.
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+ * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
314  */
325 
336 #ifndef ENA_ETH_COM_H_
....@@ -67,11 +40,13 @@
6740 	enum ena_eth_io_l4_proto_index l4_proto;
6841 	bool l3_csum_err;
6942 	bool l4_csum_err;
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+	u8 l4_csum_checked;
7044 	/* fragmented packet */
7145 	bool frag;
7246 	u32 hash;
7347 	u16 descs;
7448 	int max_bufs;
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+	u8 pkt_offset;
7550 };
7651 
7752 int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
....@@ -86,8 +61,6 @@
8661 			       struct ena_com_buf *ena_buf,
8762 			       u16 req_id);
8863 
89
-int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id);
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-
9164 bool ena_com_cq_empty(struct ena_com_io_cq *io_cq);
9265 
9366 static inline void ena_com_unmask_intr(struct ena_com_io_cq *io_cq,
....@@ -96,7 +69,7 @@
9669 	writel(intr_reg->intr_control, io_cq->unmask_reg);
9770 }
9871 
99
-static inline int ena_com_sq_empty_space(struct ena_com_io_sq *io_sq)
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+static inline int ena_com_free_q_entries(struct ena_com_io_sq *io_sq)
10073 {
10174 	u16 tail, next_to_comp, cnt;
10275 
....@@ -107,16 +80,87 @@
10780 	return io_sq->q_depth - 1 - cnt;
10881 }
10982 
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+/* Check if the submission queue has enough space to hold required_buffers */
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+static inline bool ena_com_sq_have_enough_space(struct ena_com_io_sq *io_sq,
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+						u16 required_buffers)
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+{
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+	int temp;
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+
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+	if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
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+		return ena_com_free_q_entries(io_sq) >= required_buffers;
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+
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+	/* This calculation doesn't need to be 100% accurate. So to reduce
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+	 * the calculation overhead just Subtract 2 lines from the free descs
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+	 * (one for the header line and one to compensate the devision
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+	 * down calculation.
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+	 */
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+	temp = required_buffers / io_sq->llq_info.descs_per_entry + 2;
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+
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+	return ena_com_free_q_entries(io_sq) > temp;
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+}
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+
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+static inline bool ena_com_meta_desc_changed(struct ena_com_io_sq *io_sq,
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+					     struct ena_com_tx_ctx *ena_tx_ctx)
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+{
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+	if (!ena_tx_ctx->meta_valid)
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+		return false;
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+
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+	return !!memcmp(&io_sq->cached_tx_meta,
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+			&ena_tx_ctx->ena_meta,
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+			sizeof(struct ena_com_tx_meta));
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+}
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+
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+static inline bool is_llq_max_tx_burst_exists(struct ena_com_io_sq *io_sq)
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+{
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+	return (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) &&
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+	       io_sq->llq_info.max_entries_in_tx_burst > 0;
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+}
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+
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+static inline bool ena_com_is_doorbell_needed(struct ena_com_io_sq *io_sq,
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+					      struct ena_com_tx_ctx *ena_tx_ctx)
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+{
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+	struct ena_com_llq_info *llq_info;
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+	int descs_after_first_entry;
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+	int num_entries_needed = 1;
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+	u16 num_descs;
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+
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+	if (!is_llq_max_tx_burst_exists(io_sq))
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+		return false;
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+
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+	llq_info = &io_sq->llq_info;
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+	num_descs = ena_tx_ctx->num_bufs;
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+
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+	if (llq_info->disable_meta_caching ||
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+	    unlikely(ena_com_meta_desc_changed(io_sq, ena_tx_ctx)))
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+		++num_descs;
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+
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+	if (num_descs > llq_info->descs_num_before_header) {
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+		descs_after_first_entry = num_descs - llq_info->descs_num_before_header;
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+		num_entries_needed += DIV_ROUND_UP(descs_after_first_entry,
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+						   llq_info->descs_per_entry);
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+	}
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+
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+	pr_debug("Queue: %d num_descs: %d num_entries_needed: %d\n", io_sq->qid,
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+		 num_descs, num_entries_needed);
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+
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+	return num_entries_needed > io_sq->entries_in_tx_burst_left;
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+}
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+
110149 static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
111150 {
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-	u16 tail;
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+	u16 max_entries_in_tx_burst = io_sq->llq_info.max_entries_in_tx_burst;
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+	u16 tail = io_sq->tail;
113153 
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-	tail = io_sq->tail;
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-
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-	pr_debug("write submission queue doorbell for queue: %d tail: %d\n",
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+	pr_debug("Write submission queue doorbell for queue: %d tail: %d\n",
117155 		 io_sq->qid, tail);
118156 
119157 	writel(tail, io_sq->db_addr);
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+
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+	if (is_llq_max_tx_burst_exists(io_sq)) {
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+		pr_debug("Reset available entries in tx burst for queue %d to %d\n",
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+			 io_sq->qid, max_entries_in_tx_burst);
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+		io_sq->entries_in_tx_burst_left = max_entries_in_tx_burst;
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+	}
120164 
121165 	return 0;
122166 }
....@@ -126,15 +170,17 @@
126170 	u16 unreported_comp, head;
127171 	bool need_update;
128172 
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-	head = io_cq->head;
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-	unreported_comp = head - io_cq->last_head_update;
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-	need_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH);
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+	if (unlikely(io_cq->cq_head_db_reg)) {
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+		head = io_cq->head;
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+		unreported_comp = head - io_cq->last_head_update;
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+		need_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH);
132177 
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-	if (io_cq->cq_head_db_reg && need_update) {
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-		pr_debug("Write completion queue doorbell for queue %d: head: %d\n",
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-			 io_cq->qid, head);
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-		writel(head, io_cq->cq_head_db_reg);
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-		io_cq->last_head_update = head;
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+		if (unlikely(need_update)) {
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+			pr_debug("Write completion queue doorbell for queue %d: head: %d\n",
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+				 io_cq->qid, head);
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+			writel(head, io_cq->cq_head_db_reg);
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+			io_cq->last_head_update = head;
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+		}
138184 	}
139185 
140186 	return 0;
....@@ -159,4 +205,48 @@
159205 	io_sq->next_to_comp += elem;
160206 }
161207 
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+static inline void ena_com_cq_inc_head(struct ena_com_io_cq *io_cq)
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+{
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+	io_cq->head++;
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+
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+	/* Switch phase bit in case of wrap around */
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+	if (unlikely((io_cq->head & (io_cq->q_depth - 1)) == 0))
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+		io_cq->phase ^= 1;
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+}
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+
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+static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq,
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+					     u16 *req_id)
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+{
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+	u8 expected_phase, cdesc_phase;
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+	struct ena_eth_io_tx_cdesc *cdesc;
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+	u16 masked_head;
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+
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+	masked_head = io_cq->head & (io_cq->q_depth - 1);
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+	expected_phase = io_cq->phase;
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+
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+	cdesc = (struct ena_eth_io_tx_cdesc *)
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+		((uintptr_t)io_cq->cdesc_addr.virt_addr +
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+		(masked_head * io_cq->cdesc_entry_size_in_bytes));
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+
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+	/* When the current completion descriptor phase isn't the same as the
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+	 * expected, it mean that the device still didn't update
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+	 * this completion.
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+	 */
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+	cdesc_phase = READ_ONCE(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
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+	if (cdesc_phase != expected_phase)
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+		return -EAGAIN;
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+
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+	dma_rmb();
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+
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+	*req_id = READ_ONCE(cdesc->req_id);
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+	if (unlikely(*req_id >= io_cq->q_depth)) {
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+		pr_err("Invalid req id %d\n", cdesc->req_id);
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+		return -EINVAL;
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+	}
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+
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+	ena_com_cq_inc_head(io_cq);
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+
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+	return 0;
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+}
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+
162252 #endif /* ENA_ETH_COM_H_ */