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2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/net/dsa/mv88e6xxx/global1.c
..
..
@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
1
2
 /*
2
3
  * Marvell 88E6xxx Switch Global (1) Registers support
3
4
  *
..
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@@ -5,11 +6,6 @@
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6
  *
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7
  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
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8
  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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9
  */
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10
 
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11
 #include <linux/bitfield.h>
..
..
@@ -31,100 +27,52 @@
31
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 	return mv88e6xxx_write(chip, addr, reg, val);
32
28
 }
33
29
 
34
-int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
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+int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
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+			  bit, int val)
35
32
 {
36
-	return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask);
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+	return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
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+				  bit, val);
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+}
36
+
37
+int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
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+			   u16 mask, u16 val)
39
+{
40
+	return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
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+				   mask, val);
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42
 }
38
43
 
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44
 /* Offset 0x00: Switch Global Status Register */
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45
 
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 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
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47
 {
43
-	u16 state;
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-	int i, err;
45
-
46
-	for (i = 0; i < 16; i++) {
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-		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
48
-		if (err)
49
-			return err;
50
-
51
-		/* Check the value of the PPUState bits 15:14 */
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-		state &= MV88E6185_G1_STS_PPU_STATE_MASK;
53
-		if (state != MV88E6185_G1_STS_PPU_STATE_POLLING)
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-			return 0;
55
-
56
-		usleep_range(1000, 2000);
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-	}
58
-
59
-	return -ETIMEDOUT;
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+	return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
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+				      MV88E6185_G1_STS_PPU_STATE_MASK,
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+				      MV88E6185_G1_STS_PPU_STATE_DISABLED);
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51
 }
61
52
 
62
53
 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
63
54
 {
64
-	u16 state;
65
-	int i, err;
66
-
67
-	for (i = 0; i < 16; ++i) {
68
-		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
69
-		if (err)
70
-			return err;
71
-
72
-		/* Check the value of the PPUState bits 15:14 */
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-		state &= MV88E6185_G1_STS_PPU_STATE_MASK;
74
-		if (state == MV88E6185_G1_STS_PPU_STATE_POLLING)
75
-			return 0;
76
-
77
-		usleep_range(1000, 2000);
78
-	}
79
-
80
-	return -ETIMEDOUT;
55
+	return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
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+				      MV88E6185_G1_STS_PPU_STATE_MASK,
57
+				      MV88E6185_G1_STS_PPU_STATE_POLLING);
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58
 }
82
59
 
83
60
 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
84
61
 {
85
-	u16 state;
86
-	int i, err;
62
+	int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
87
63
 
88
-	for (i = 0; i < 16; ++i) {
89
-		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
90
-		if (err)
91
-			return err;
92
-
93
-		/* Check the value of the PPUState (or InitState) bit 15 */
94
-		if (state & MV88E6352_G1_STS_PPU_STATE)
95
-			return 0;
96
-
97
-		usleep_range(1000, 2000);
98
-	}
99
-
100
-	return -ETIMEDOUT;
64
+	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
101
65
 }
102
66
 
103
67
 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
104
68
 {
105
-	const unsigned long timeout = jiffies + 1 * HZ;
106
-	u16 val;
107
-	int err;
69
+	int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
108
70
 
109
71
 	/* Wait up to 1 second for the switch to be ready. The InitReady bit 11
110
72
 	 * is set to a one when all units inside the device (ATU, VTU, etc.)
111
73
 	 * have finished their initialization and are ready to accept frames.
112
74
 	 */
113
-	while (time_before(jiffies, timeout)) {
114
-		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
115
-		if (err)
116
-			return err;
117
-
118
-		if (val & MV88E6XXX_G1_STS_INIT_READY)
119
-			break;
120
-
121
-		usleep_range(1000, 2000);
122
-	}
123
-
124
-	if (time_after(jiffies, timeout))
125
-		return -ETIMEDOUT;
126
-
127
-	return 0;
75
+	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
128
76
 }
129
77
 
130
78
 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
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..
@@ -182,7 +130,7 @@
182
130
 	return mv88e6185_g1_wait_ppu_polling(chip);
183
131
 }
184
132
 
185
-int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
133
+int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
186
134
 {
187
135
 	u16 val;
188
136
 	int err;
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@@ -198,7 +146,14 @@
198
146
 	if (err)
199
147
 		return err;
200
148
 
201
-	err = mv88e6xxx_g1_wait_init_ready(chip);
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+	return mv88e6xxx_g1_wait_init_ready(chip);
150
+}
151
+
152
+int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
153
+{
154
+	int err;
155
+
156
+	err = mv88e6250_g1_reset(chip);
202
157
 	if (err)
203
158
 		return err;
204
159
 
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@@ -239,6 +194,25 @@
239
194
 		return err;
240
195
 
241
196
 	return mv88e6185_g1_wait_ppu_disabled(chip);
197
+}
198
+
199
+int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu)
200
+{
201
+	u16 val;
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+	int err;
203
+
204
+	mtu += ETH_HLEN + ETH_FCS_LEN;
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+
206
+	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
207
+	if (err)
208
+		return err;
209
+
210
+	val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632;
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+
212
+	if (mtu > 1518)
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+		val |= MV88E6185_G1_CTL1_MAX_FRAME_1632;
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+
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+	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
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216
 }
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217
 
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 /* Offset 0x10: IP-PRI Mapping Register 0
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@@ -299,11 +273,20 @@
299
273
 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
300
274
 }
301
275
 
276
+int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
277
+{
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+	/* Reset the IEEE Tag priorities to defaults */
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+	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
280
+}
281
+
302
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 /* Offset 0x1a: Monitor Control */
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283
 /* Offset 0x1a: Monitor & MGMT Control on some devices */
304
284
 
305
-int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
285
+int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
286
+				 enum mv88e6xxx_egress_direction direction,
287
+				 int port)
306
288
 {
289
+	int *dest_port_chip;
307
290
 	u16 reg;
308
291
 	int err;
309
292
 
..
..
@@ -311,13 +294,28 @@
311
294
 	if (err)
312
295
 		return err;
313
296
 
314
-	reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK |
315
-		 MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
297
+	switch (direction) {
298
+	case MV88E6XXX_EGRESS_DIR_INGRESS:
299
+		dest_port_chip = &chip->ingress_dest_port;
300
+		reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
301
+		reg |= port <<
302
+		       __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
303
+		break;
304
+	case MV88E6XXX_EGRESS_DIR_EGRESS:
305
+		dest_port_chip = &chip->egress_dest_port;
306
+		reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
307
+		reg |= port <<
308
+		       __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
309
+		break;
310
+	default:
311
+		return -EINVAL;
312
+	}
316
313
 
317
-	reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) |
318
-		port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
314
+	err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
315
+	if (!err)
316
+		*dest_port_chip = port;
319
317
 
320
-	return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
318
+	return err;
321
319
 }
322
320
 
323
321
 /* Older generations also call this the ARP destination. It has been
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@@ -349,22 +347,32 @@
349
347
 	return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
350
348
 }
351
349
 
352
-int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
350
+int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
351
+				 enum mv88e6xxx_egress_direction direction,
352
+				 int port)
353
353
 {
354
+	int *dest_port_chip;
354
355
 	u16 ptr;
355
356
 	int err;
356
357
 
357
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
358
-	err = mv88e6390_g1_monitor_write(chip, ptr, port);
359
-	if (err)
360
-		return err;
358
+	switch (direction) {
359
+	case MV88E6XXX_EGRESS_DIR_INGRESS:
360
+		dest_port_chip = &chip->ingress_dest_port;
361
+		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
362
+		break;
363
+	case MV88E6XXX_EGRESS_DIR_EGRESS:
364
+		dest_port_chip = &chip->egress_dest_port;
365
+		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
366
+		break;
367
+	default:
368
+		return -EINVAL;
369
+	}
361
370
 
362
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
363
371
 	err = mv88e6390_g1_monitor_write(chip, ptr, port);
364
-	if (err)
365
-		return err;
372
+	if (!err)
373
+		*dest_port_chip = port;
366
374
 
367
-	return 0;
375
+	return err;
368
376
 }
369
377
 
370
378
 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
..
..
@@ -384,26 +392,26 @@
384
392
 	u16 ptr;
385
393
 	int err;
386
394
 
387
-	/* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */
388
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO;
395
+	/* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
396
+	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
389
397
 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
390
398
 	if (err)
391
399
 		return err;
392
400
 
393
-	/* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */
394
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI;
401
+	/* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
402
+	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
395
403
 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
396
404
 	if (err)
397
405
 		return err;
398
406
 
399
-	/* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */
400
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO;
407
+	/* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
408
+	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
401
409
 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
402
410
 	if (err)
403
411
 		return err;
404
412
 
405
-	/* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */
406
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI;
413
+	/* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
414
+	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
407
415
 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
408
416
 	if (err)
409
417
 		return err;
..
..
@@ -470,10 +478,11 @@
470
478
 
471
479
 /* Offset 0x1d: Statistics Operation 2 */
472
480
 
473
-int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
481
+static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
474
482
 {
475
-	return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP,
476
-				 MV88E6XXX_G1_STATS_OP_BUSY);
483
+	int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
484
+
485
+	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
477
486
 }
478
487
 
479
488
 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)