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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (C) 1999 - 2010 Intel Corporation. |
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| 3 | 4 | * Copyright (C) 2010 LAPIS SEMICONDUCTOR CO., LTD. |
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| 4 | | - * |
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| 5 | | - * This program is free software; you can redistribute it and/or modify |
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| 6 | | - * it under the terms of the GNU General Public License as published by |
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| 7 | | - * the Free Software Foundation; version 2 of the License. |
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| 8 | | - * |
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| 9 | | - * This program is distributed in the hope that it will be useful, |
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| 10 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 11 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 12 | | - * GNU General Public License for more details. |
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| 13 | | - * |
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| 14 | | - * You should have received a copy of the GNU General Public License |
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| 15 | | - * along with this program; if not, see <http://www.gnu.org/licenses/>. |
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| 16 | 5 | */ |
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| 17 | 6 | |
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| 18 | 7 | #include <linux/interrupt.h> |
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| .. | .. |
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| 472 | 461 | PCH_ID2_DIR | (0x7ff << 2)); |
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| 473 | 462 | iowrite32(0x0, &priv->regs->ifregs[1].id1); |
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| 474 | 463 | |
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| 475 | | - /* Claring NewDat, TxRqst & IntPnd */ |
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| 464 | + /* Clearing NewDat, TxRqst & IntPnd */ |
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| 476 | 465 | pch_can_bit_clear(&priv->regs->ifregs[1].mcont, |
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| 477 | 466 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | |
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| 478 | 467 | PCH_IF_MCONT_TXRQXT); |
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| .. | .. |
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| 500 | 489 | if (!skb) |
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| 501 | 490 | return; |
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| 502 | 491 | |
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| 492 | + errc = ioread32(&priv->regs->errc); |
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| 503 | 493 | if (status & PCH_BUS_OFF) { |
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| 504 | 494 | pch_can_set_tx_all(priv, 0); |
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| 505 | 495 | pch_can_set_rx_all(priv, 0); |
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| .. | .. |
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| 507 | 497 | cf->can_id |= CAN_ERR_BUSOFF; |
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| 508 | 498 | priv->can.can_stats.bus_off++; |
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| 509 | 499 | can_bus_off(ndev); |
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| 500 | + } else { |
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| 501 | + cf->data[6] = errc & PCH_TEC; |
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| 502 | + cf->data[7] = (errc & PCH_REC) >> 8; |
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| 510 | 503 | } |
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| 511 | 504 | |
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| 512 | | - errc = ioread32(&priv->regs->errc); |
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| 513 | 505 | /* Warning interrupt. */ |
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| 514 | 506 | if (status & PCH_EWARN) { |
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| 515 | 507 | state = CAN_STATE_ERROR_WARNING; |
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| .. | .. |
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| 566 | 558 | case PCH_LEC_ALL: /* Written by CPU. No error status */ |
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| 567 | 559 | break; |
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| 568 | 560 | } |
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| 569 | | - |
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| 570 | | - cf->data[6] = errc & PCH_TEC; |
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| 571 | | - cf->data[7] = (errc & PCH_REC) >> 8; |
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| 572 | 561 | |
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| 573 | 562 | priv->can.state = state; |
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| 574 | 563 | netif_receive_skb(skb); |
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| .. | .. |
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| 845 | 834 | struct pch_can_priv *priv = netdev_priv(ndev); |
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| 846 | 835 | int retval; |
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| 847 | 836 | |
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| 848 | | - /* Regstering the interrupt. */ |
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| 837 | + /* Registering the interrupt. */ |
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| 849 | 838 | retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, |
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| 850 | 839 | ndev->name, ndev); |
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| 851 | 840 | if (retval) { |
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| .. | .. |
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| 968 | 957 | free_candev(priv->ndev); |
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| 969 | 958 | } |
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| 970 | 959 | |
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| 971 | | -#ifdef CONFIG_PM |
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| 972 | | -static void pch_can_set_int_custom(struct pch_can_priv *priv) |
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| 960 | +static void __maybe_unused pch_can_set_int_custom(struct pch_can_priv *priv) |
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| 973 | 961 | { |
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| 974 | 962 | /* Clearing the IE, SIE and EIE bits of Can control register. */ |
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| 975 | 963 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); |
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| .. | .. |
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| 980 | 968 | } |
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| 981 | 969 | |
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| 982 | 970 | /* This function retrieves interrupt enabled for the CAN device. */ |
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| 983 | | -static u32 pch_can_get_int_enables(struct pch_can_priv *priv) |
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| 971 | +static u32 __maybe_unused pch_can_get_int_enables(struct pch_can_priv *priv) |
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| 984 | 972 | { |
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| 985 | 973 | /* Obtaining the status of IE, SIE and EIE interrupt bits. */ |
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| 986 | 974 | return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1; |
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| 987 | 975 | } |
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| 988 | 976 | |
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| 989 | | -static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, |
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| 990 | | - enum pch_ifreg dir) |
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| 977 | +static u32 __maybe_unused pch_can_get_rxtx_ir(struct pch_can_priv *priv, |
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| 978 | + u32 buff_num, enum pch_ifreg dir) |
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| 991 | 979 | { |
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| 992 | 980 | u32 ie, enable; |
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| 993 | 981 | |
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| .. | .. |
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| 1008 | 996 | return enable; |
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| 1009 | 997 | } |
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| 1010 | 998 | |
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| 1011 | | -static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, |
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| 1012 | | - u32 buffer_num, int set) |
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| 999 | +static void __maybe_unused pch_can_set_rx_buffer_link(struct pch_can_priv *priv, |
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| 1000 | + u32 buffer_num, int set) |
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| 1013 | 1001 | { |
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| 1014 | 1002 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
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| 1015 | 1003 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); |
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| .. | .. |
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| 1024 | 1012 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); |
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| 1025 | 1013 | } |
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| 1026 | 1014 | |
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| 1027 | | -static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num) |
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| 1015 | +static u32 __maybe_unused pch_can_get_rx_buffer_link(struct pch_can_priv *priv, |
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| 1016 | + u32 buffer_num) |
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| 1028 | 1017 | { |
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| 1029 | 1018 | u32 link; |
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| 1030 | 1019 | |
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| .. | .. |
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| 1038 | 1027 | return link; |
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| 1039 | 1028 | } |
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| 1040 | 1029 | |
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| 1041 | | -static int pch_can_get_buffer_status(struct pch_can_priv *priv) |
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| 1030 | +static int __maybe_unused pch_can_get_buffer_status(struct pch_can_priv *priv) |
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| 1042 | 1031 | { |
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| 1043 | 1032 | return (ioread32(&priv->regs->treq1) & 0xffff) | |
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| 1044 | 1033 | (ioread32(&priv->regs->treq2) << 16); |
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| 1045 | 1034 | } |
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| 1046 | 1035 | |
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| 1047 | | -static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) |
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| 1036 | +static int __maybe_unused pch_can_suspend(struct device *dev_d) |
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| 1048 | 1037 | { |
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| 1049 | 1038 | int i; |
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| 1050 | | - int retval; |
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| 1051 | 1039 | u32 buf_stat; /* Variable for reading the transmit buffer status. */ |
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| 1052 | 1040 | int counter = PCH_COUNTER_LIMIT; |
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| 1053 | 1041 | |
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| 1054 | | - struct net_device *dev = pci_get_drvdata(pdev); |
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| 1042 | + struct net_device *dev = dev_get_drvdata(dev_d); |
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| 1055 | 1043 | struct pch_can_priv *priv = netdev_priv(dev); |
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| 1056 | 1044 | |
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| 1057 | 1045 | /* Stop the CAN controller */ |
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| .. | .. |
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| 1069 | 1057 | udelay(1); |
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| 1070 | 1058 | } |
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| 1071 | 1059 | if (!counter) |
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| 1072 | | - dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); |
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| 1060 | + dev_err(dev_d, "%s -> Transmission time out.\n", __func__); |
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| 1073 | 1061 | |
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| 1074 | 1062 | /* Save interrupt configuration and then disable them */ |
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| 1075 | 1063 | priv->int_enables = pch_can_get_int_enables(priv); |
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| .. | .. |
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| 1092 | 1080 | |
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| 1093 | 1081 | /* Disable all Receive buffers */ |
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| 1094 | 1082 | pch_can_set_rx_all(priv, 0); |
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| 1095 | | - retval = pci_save_state(pdev); |
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| 1096 | | - if (retval) { |
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| 1097 | | - dev_err(&pdev->dev, "pci_save_state failed.\n"); |
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| 1098 | | - } else { |
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| 1099 | | - pci_enable_wake(pdev, PCI_D3hot, 0); |
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| 1100 | | - pci_disable_device(pdev); |
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| 1101 | | - pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
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| 1102 | | - } |
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| 1103 | 1083 | |
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| 1104 | | - return retval; |
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| 1084 | + return 0; |
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| 1105 | 1085 | } |
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| 1106 | 1086 | |
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| 1107 | | -static int pch_can_resume(struct pci_dev *pdev) |
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| 1087 | +static int __maybe_unused pch_can_resume(struct device *dev_d) |
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| 1108 | 1088 | { |
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| 1109 | 1089 | int i; |
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| 1110 | | - int retval; |
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| 1111 | | - struct net_device *dev = pci_get_drvdata(pdev); |
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| 1090 | + struct net_device *dev = dev_get_drvdata(dev_d); |
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| 1112 | 1091 | struct pch_can_priv *priv = netdev_priv(dev); |
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| 1113 | | - |
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| 1114 | | - pci_set_power_state(pdev, PCI_D0); |
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| 1115 | | - pci_restore_state(pdev); |
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| 1116 | | - retval = pci_enable_device(pdev); |
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| 1117 | | - if (retval) { |
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| 1118 | | - dev_err(&pdev->dev, "pci_enable_device failed.\n"); |
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| 1119 | | - return retval; |
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| 1120 | | - } |
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| 1121 | | - |
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| 1122 | | - pci_enable_wake(pdev, PCI_D3hot, 0); |
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| 1123 | 1092 | |
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| 1124 | 1093 | priv->can.state = CAN_STATE_ERROR_ACTIVE; |
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| 1125 | 1094 | |
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| .. | .. |
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| 1157 | 1126 | /* Restore Run Mode */ |
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| 1158 | 1127 | pch_can_set_run_mode(priv, PCH_CAN_RUN); |
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| 1159 | 1128 | |
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| 1160 | | - return retval; |
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| 1129 | + return 0; |
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| 1161 | 1130 | } |
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| 1162 | | -#else |
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| 1163 | | -#define pch_can_suspend NULL |
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| 1164 | | -#define pch_can_resume NULL |
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| 1165 | | -#endif |
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| 1166 | 1131 | |
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| 1167 | 1132 | static int pch_can_get_berr_counter(const struct net_device *dev, |
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| 1168 | 1133 | struct can_berr_counter *bec) |
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| .. | .. |
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| 1263 | 1228 | return rc; |
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| 1264 | 1229 | } |
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| 1265 | 1230 | |
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| 1231 | +static SIMPLE_DEV_PM_OPS(pch_can_pm_ops, |
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| 1232 | + pch_can_suspend, |
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| 1233 | + pch_can_resume); |
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| 1234 | + |
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| 1266 | 1235 | static struct pci_driver pch_can_pci_driver = { |
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| 1267 | 1236 | .name = "pch_can", |
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| 1268 | 1237 | .id_table = pch_pci_tbl, |
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| 1269 | 1238 | .probe = pch_can_probe, |
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| 1270 | 1239 | .remove = pch_can_remove, |
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| 1271 | | - .suspend = pch_can_suspend, |
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| 1272 | | - .resume = pch_can_resume, |
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| 1240 | + .driver.pm = &pch_can_pm_ops, |
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| 1273 | 1241 | }; |
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| 1274 | 1242 | |
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| 1275 | 1243 | module_pci_driver(pch_can_pci_driver); |
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