~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,20 +1,14 @@
1		-/*
2		- * CAN bus driver for Bosch M_CAN controller
3		- *
4		- * Copyright (C) 2014 Freescale Semiconductor, Inc.
5		- * Dong Aisheng <b29396@freescale.com>
6		- *
7		- * Bosch M_CAN user manual can be obtained from:
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+// CAN bus driver for Bosch M_CAN controller
	3	+// Copyright (C) 2014 Freescale Semiconductor, Inc.
	4	+// Dong Aisheng <b29396@freescale.com>
	5	+// Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
	6	+
	7	+/* Bosch M_CAN user manual can be obtained from:
8	8	* http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
9	9	* mcan_users_manual_v302.pdf
10		- *
11		- * This file is licensed under the terms of the GNU General Public
12		- * License version 2. This program is licensed "as is" without any
13		- * warranty of any kind, whether express or implied.
14	10	*/
15	11
16		-#include <linux/clk.h>
17		-#include <linux/delay.h>
18	12	#include <linux/interrupt.h>
19	13	#include <linux/io.h>
20	14	#include <linux/kernel.h>
..	..	@@ -28,11 +22,7 @@
28	22	#include <linux/can/dev.h>
29	23	#include <linux/pinctrl/consumer.h>
30	24
31		-/* napi related */
32		-#define M_CAN_NAPI_WEIGHT 64
33		-
34		-/* message ram configuration data length */
35		-#define MRAM_CFG_LEN 8
	25	+#include "m_can.h"
36	26
37	27	/* registers definition */
38	28	enum m_can_reg {
..	..	@@ -86,28 +76,11 @@
86	76	M_CAN_TXEFA = 0xf8,
87	77	};
88	78
89		-/* m_can lec values */
90		-enum m_can_lec_type {
91		- LEC_NO_ERROR = 0,
92		- LEC_STUFF_ERROR,
93		- LEC_FORM_ERROR,
94		- LEC_ACK_ERROR,
95		- LEC_BIT1_ERROR,
96		- LEC_BIT0_ERROR,
97		- LEC_CRC_ERROR,
98		- LEC_UNUSED,
99		-};
	79	+/* napi related */
	80	+#define M_CAN_NAPI_WEIGHT 64
100	81
101		-enum m_can_mram_cfg {
102		- MRAM_SIDF = 0,
103		- MRAM_XIDF,
104		- MRAM_RXF0,
105		- MRAM_RXF1,
106		- MRAM_RXB,
107		- MRAM_TXE,
108		- MRAM_TXB,
109		- MRAM_CFG_NUM,
110		-};
	82	+/* message ram configuration data length */
	83	+#define MRAM_CFG_LEN 8
111	84
112	85	/* Core Release Register (CREL) */
113	86	#define CREL_REL_SHIFT 28
..	..	@@ -150,6 +123,7 @@
150	123	#define CCCR_CME_CANFD_BRS 0x2
151	124	#define CCCR_TXP BIT(14)
152	125	#define CCCR_TEST BIT(7)
	126	+#define CCCR_DAR BIT(6)
153	127	#define CCCR_MON BIT(5)
154	128	#define CCCR_CSR BIT(4)
155	129	#define CCCR_CSA BIT(3)
..	..	@@ -347,90 +321,81 @@
347	321	#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
348	322	#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
349	323
350		-/* address offset and element number for each FIFO/Buffer in the Message RAM */
351		-struct mram_cfg {
352		- u16 off;
353		- u8 num;
354		-};
355		-
356		-/* m_can private data structure */
357		-struct m_can_priv {
358		- struct can_priv can; /* must be the first member */
359		- struct napi_struct napi;
360		- struct net_device *dev;
361		- struct device *device;
362		- struct clk *hclk;
363		- struct clk *cclk;
364		- void __iomem *base;
365		- u32 irqstatus;
366		- int version;
367		-
368		- /* message ram configuration */
369		- void __iomem *mram_base;
370		- struct mram_cfg mcfg[MRAM_CFG_NUM];
371		-};
372		-
373		-static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg)
	324	+static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg)
374	325	{
375		- return readl(priv->base + reg);
	326	+ return cdev->ops->read_reg(cdev, reg);
376	327	}
377	328
378		-static inline void m_can_write(const struct m_can_priv *priv,
379		- enum m_can_reg reg, u32 val)
	329	+static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg,
	330	+ u32 val)
380	331	{
381		- writel(val, priv->base + reg);
	332	+ cdev->ops->write_reg(cdev, reg, val);
382	333	}
383	334
384		-static inline u32 m_can_fifo_read(const struct m_can_priv *priv,
385		- u32 fgi, unsigned int offset)
	335	+static u32 m_can_fifo_read(struct m_can_classdev *cdev,
	336	+ u32 fgi, unsigned int offset)
386	337	{
387		- return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off +
388		- fgi * RXF0_ELEMENT_SIZE + offset);
	338	+ u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
	339	+ offset;
	340	+
	341	+ return cdev->ops->read_fifo(cdev, addr_offset);
389	342	}
390	343
391		-static inline void m_can_fifo_write(const struct m_can_priv *priv,
392		- u32 fpi, unsigned int offset, u32 val)
	344	+static void m_can_fifo_write(struct m_can_classdev *cdev,
	345	+ u32 fpi, unsigned int offset, u32 val)
393	346	{
394		- writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off +
395		- fpi * TXB_ELEMENT_SIZE + offset);
	347	+ u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
	348	+ offset;
	349	+
	350	+ cdev->ops->write_fifo(cdev, addr_offset, val);
396	351	}
397	352
398		-static inline u32 m_can_txe_fifo_read(const struct m_can_priv *priv,
399		- u32 fgi,
400		- u32 offset) {
401		- return readl(priv->mram_base + priv->mcfg[MRAM_TXE].off +
402		- fgi * TXE_ELEMENT_SIZE + offset);
	353	+static inline void m_can_fifo_write_no_off(struct m_can_classdev *cdev,
	354	+ u32 fpi, u32 val)
	355	+{
	356	+ cdev->ops->write_fifo(cdev, fpi, val);
403	357	}
404	358
405		-static inline bool m_can_tx_fifo_full(const struct m_can_priv *priv)
	359	+static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset)
406	360	{
407		- return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF);
	361	+ u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
	362	+ offset;
	363	+
	364	+ return cdev->ops->read_fifo(cdev, addr_offset);
408	365	}
409	366
410		-static inline void m_can_config_endisable(const struct m_can_priv *priv,
411		- bool enable)
	367	+static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev)
412	368	{
413		- u32 cccr = m_can_read(priv, M_CAN_CCCR);
	369	+ return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF);
	370	+}
	371	+
	372	+void m_can_config_endisable(struct m_can_classdev *cdev, bool enable)
	373	+{
	374	+ u32 cccr = m_can_read(cdev, M_CAN_CCCR);
414	375	u32 timeout = 10;
415	376	u32 val = 0;
416	377
	378	+ /* Clear the Clock stop request if it was set */
	379	+ if (cccr & CCCR_CSR)
	380	+ cccr &= ~CCCR_CSR;
	381	+
417	382	if (enable) {
418	383	/* enable m_can configuration */
419		- m_can_write(priv, M_CAN_CCCR, cccr \| CCCR_INIT);
	384	+ m_can_write(cdev, M_CAN_CCCR, cccr \| CCCR_INIT);
420	385	udelay(5);
421	386	/* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
422		- m_can_write(priv, M_CAN_CCCR, cccr \| CCCR_INIT \| CCCR_CCE);
	387	+ m_can_write(cdev, M_CAN_CCCR, cccr \| CCCR_INIT \| CCCR_CCE);
423	388	} else {
424		- m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT \| CCCR_CCE));
	389	+ m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT \| CCCR_CCE));
425	390	}
426	391
427	392	/* there's a delay for module initialization */
428	393	if (enable)
429	394	val = CCCR_INIT \| CCCR_CCE;
430	395
431		- while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT \| CCCR_CCE)) != val) {
	396	+ while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT \| CCCR_CCE)) != val) {
432	397	if (timeout == 0) {
433		- netdev_warn(priv->dev, "Failed to init module\n");
	398	+ netdev_warn(cdev->net, "Failed to init module\n");
434	399	return;
435	400	}
436	401	timeout--;
..	..	@@ -438,21 +403,38 @@
438	403	}
439	404	}
440	405
441		-static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv)
	406	+static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev)
442	407	{
443	408	/* Only interrupt line 0 is used in this driver */
444		- m_can_write(priv, M_CAN_ILE, ILE_EINT0);
	409	+ m_can_write(cdev, M_CAN_ILE, ILE_EINT0);
445	410	}
446	411
447		-static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
	412	+static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev)
448	413	{
449		- m_can_write(priv, M_CAN_ILE, 0x0);
	414	+ m_can_write(cdev, M_CAN_ILE, 0x0);
	415	+}
	416	+
	417	+static void m_can_clean(struct net_device *net)
	418	+{
	419	+ struct m_can_classdev *cdev = netdev_priv(net);
	420	+
	421	+ if (cdev->tx_skb) {
	422	+ int putidx = 0;
	423	+
	424	+ net->stats.tx_errors++;
	425	+ if (cdev->version > 30)
	426	+ putidx = ((m_can_read(cdev, M_CAN_TXFQS) &
	427	+ TXFQS_TFQPI_MASK) >> TXFQS_TFQPI_SHIFT);
	428	+
	429	+ can_free_echo_skb(cdev->net, putidx);
	430	+ cdev->tx_skb = NULL;
	431	+ }
450	432	}
451	433
452	434	static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
453	435	{
454	436	struct net_device_stats *stats = &dev->stats;
455		- struct m_can_priv *priv = netdev_priv(dev);
	437	+ struct m_can_classdev *cdev = netdev_priv(dev);
456	438	struct canfd_frame *cf;
457	439	struct sk_buff *skb;
458	440	u32 id, fgi, dlc;
..	..	@@ -460,7 +442,7 @@
460	442
461	443	/* calculate the fifo get index for where to read data */
462	444	fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT;
463		- dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
	445	+ dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC);
464	446	if (dlc & RX_BUF_FDF)
465	447	skb = alloc_canfd_skb(dev, &cf);
466	448	else
..	..	@@ -475,7 +457,7 @@
475	457	else
476	458	cf->len = get_can_dlc((dlc >> 16) & 0x0F);
477	459
478		- id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID);
	460	+ id = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID);
479	461	if (id & RX_BUF_XTD)
480	462	cf->can_id = (id & CAN_EFF_MASK) \| CAN_EFF_FLAG;
481	463	else
..	..	@@ -494,12 +476,12 @@
494	476
495	477	for (i = 0; i < cf->len; i += 4)
496	478	(u32 )(cf->data + i) =
497		- m_can_fifo_read(priv, fgi,
	479	+ m_can_fifo_read(cdev, fgi,
498	480	M_CAN_FIFO_DATA(i / 4));
499	481	}
500	482
501	483	/* acknowledge rx fifo 0 */
502		- m_can_write(priv, M_CAN_RXF0A, fgi);
	484	+ m_can_write(cdev, M_CAN_RXF0A, fgi);
503	485
504	486	stats->rx_packets++;
505	487	stats->rx_bytes += cf->len;
..	..	@@ -509,11 +491,11 @@
509	491
510	492	static int m_can_do_rx_poll(struct net_device *dev, int quota)
511	493	{
512		- struct m_can_priv *priv = netdev_priv(dev);
	494	+ struct m_can_classdev *cdev = netdev_priv(dev);
513	495	u32 pkts = 0;
514	496	u32 rxfs;
515	497
516		- rxfs = m_can_read(priv, M_CAN_RXF0S);
	498	+ rxfs = m_can_read(cdev, M_CAN_RXF0S);
517	499	if (!(rxfs & RXFS_FFL_MASK)) {
518	500	netdev_dbg(dev, "no messages in fifo0\n");
519	501	return 0;
..	..	@@ -524,7 +506,7 @@
524	506
525	507	quota--;
526	508	pkts++;
527		- rxfs = m_can_read(priv, M_CAN_RXF0S);
	509	+ rxfs = m_can_read(cdev, M_CAN_RXF0S);
528	510	}
529	511
530	512	if (pkts)
..	..	@@ -559,12 +541,12 @@
559	541	static int m_can_handle_lec_err(struct net_device *dev,
560	542	enum m_can_lec_type lec_type)
561	543	{
562		- struct m_can_priv *priv = netdev_priv(dev);
	544	+ struct m_can_classdev *cdev = netdev_priv(dev);
563	545	struct net_device_stats *stats = &dev->stats;
564	546	struct can_frame *cf;
565	547	struct sk_buff *skb;
566	548
567		- priv->can.can_stats.bus_error++;
	549	+ cdev->can.can_stats.bus_error++;
568	550	stats->rx_errors++;
569	551
570	552	/* propagate the error condition to the CAN stack */
..	..	@@ -616,47 +598,51 @@
616	598	static int __m_can_get_berr_counter(const struct net_device *dev,
617	599	struct can_berr_counter *bec)
618	600	{
619		- struct m_can_priv *priv = netdev_priv(dev);
	601	+ struct m_can_classdev *cdev = netdev_priv(dev);
620	602	unsigned int ecr;
621	603
622		- ecr = m_can_read(priv, M_CAN_ECR);
	604	+ ecr = m_can_read(cdev, M_CAN_ECR);
623	605	bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
624	606	bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT;
625	607
626	608	return 0;
627	609	}
628	610
629		-static int m_can_clk_start(struct m_can_priv *priv)
	611	+static int m_can_clk_start(struct m_can_classdev *cdev)
630	612	{
631	613	int err;
632	614
633		- err = pm_runtime_get_sync(priv->device);
	615	+ if (cdev->pm_clock_support == 0)
	616	+ return 0;
	617	+
	618	+ err = pm_runtime_get_sync(cdev->dev);
634	619	if (err < 0) {
635		- pm_runtime_put_noidle(priv->device);
	620	+ pm_runtime_put_noidle(cdev->dev);
636	621	return err;
637	622	}
638	623
639	624	return 0;
640	625	}
641	626
642		-static void m_can_clk_stop(struct m_can_priv *priv)
	627	+static void m_can_clk_stop(struct m_can_classdev *cdev)
643	628	{
644		- pm_runtime_put_sync(priv->device);
	629	+ if (cdev->pm_clock_support)
	630	+ pm_runtime_put_sync(cdev->dev);
645	631	}
646	632
647	633	static int m_can_get_berr_counter(const struct net_device *dev,
648	634	struct can_berr_counter *bec)
649	635	{
650		- struct m_can_priv *priv = netdev_priv(dev);
	636	+ struct m_can_classdev *cdev = netdev_priv(dev);
651	637	int err;
652	638
653		- err = m_can_clk_start(priv);
	639	+ err = m_can_clk_start(cdev);
654	640	if (err)
655	641	return err;
656	642
657	643	__m_can_get_berr_counter(dev, bec);
658	644
659		- m_can_clk_stop(priv);
	645	+ m_can_clk_stop(cdev);
660	646
661	647	return 0;
662	648	}
..	..	@@ -664,7 +650,7 @@
664	650	static int m_can_handle_state_change(struct net_device *dev,
665	651	enum can_state new_state)
666	652	{
667		- struct m_can_priv *priv = netdev_priv(dev);
	653	+ struct m_can_classdev *cdev = netdev_priv(dev);
668	654	struct net_device_stats *stats = &dev->stats;
669	655	struct can_frame *cf;
670	656	struct sk_buff *skb;
..	..	@@ -674,19 +660,19 @@
674	660	switch (new_state) {
675	661	case CAN_STATE_ERROR_WARNING:
676	662	/* error warning state */
677		- priv->can.can_stats.error_warning++;
678		- priv->can.state = CAN_STATE_ERROR_WARNING;
	663	+ cdev->can.can_stats.error_warning++;
	664	+ cdev->can.state = CAN_STATE_ERROR_WARNING;
679	665	break;
680	666	case CAN_STATE_ERROR_PASSIVE:
681	667	/* error passive state */
682		- priv->can.can_stats.error_passive++;
683		- priv->can.state = CAN_STATE_ERROR_PASSIVE;
	668	+ cdev->can.can_stats.error_passive++;
	669	+ cdev->can.state = CAN_STATE_ERROR_PASSIVE;
684	670	break;
685	671	case CAN_STATE_BUS_OFF:
686	672	/* bus-off state */
687		- priv->can.state = CAN_STATE_BUS_OFF;
688		- m_can_disable_all_interrupts(priv);
689		- priv->can.can_stats.bus_off++;
	673	+ cdev->can.state = CAN_STATE_BUS_OFF;
	674	+ m_can_disable_all_interrupts(cdev);
	675	+ cdev->can.can_stats.bus_off++;
690	676	can_bus_off(dev);
691	677	break;
692	678	default:
..	..	@@ -713,7 +699,7 @@
713	699	case CAN_STATE_ERROR_PASSIVE:
714	700	/* error passive state */
715	701	cf->can_id \|= CAN_ERR_CRTL;
716		- ecr = m_can_read(priv, M_CAN_ECR);
	702	+ ecr = m_can_read(cdev, M_CAN_ECR);
717	703	if (ecr & ECR_RP)
718	704	cf->data[1] \|= CAN_ERR_CRTL_RX_PASSIVE;
719	705	if (bec.txerr > 127)
..	..	@@ -738,25 +724,22 @@
738	724
739	725	static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
740	726	{
741		- struct m_can_priv *priv = netdev_priv(dev);
	727	+ struct m_can_classdev *cdev = netdev_priv(dev);
742	728	int work_done = 0;
743	729
744		- if ((psr & PSR_EW) &&
745		- (priv->can.state != CAN_STATE_ERROR_WARNING)) {
	730	+ if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) {
746	731	netdev_dbg(dev, "entered error warning state\n");
747	732	work_done += m_can_handle_state_change(dev,
748	733	CAN_STATE_ERROR_WARNING);
749	734	}
750	735
751		- if ((psr & PSR_EP) &&
752		- (priv->can.state != CAN_STATE_ERROR_PASSIVE)) {
	736	+ if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) {
753	737	netdev_dbg(dev, "entered error passive state\n");
754	738	work_done += m_can_handle_state_change(dev,
755	739	CAN_STATE_ERROR_PASSIVE);
756	740	}
757	741
758		- if ((psr & PSR_BO) &&
759		- (priv->can.state != CAN_STATE_BUS_OFF)) {
	742	+ if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) {
760	743	netdev_dbg(dev, "entered error bus off state\n");
761	744	work_done += m_can_handle_state_change(dev,
762	745	CAN_STATE_BUS_OFF);
..	..	@@ -786,19 +769,61 @@
786	769	return psr && (psr != LEC_UNUSED);
787	770	}
788	771
	772	+static inline bool m_can_is_protocol_err(u32 irqstatus)
	773	+{
	774	+ return irqstatus & IR_ERR_LEC_31X;
	775	+}
	776	+
	777	+static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus)
	778	+{
	779	+ struct net_device_stats *stats = &dev->stats;
	780	+ struct m_can_classdev *cdev = netdev_priv(dev);
	781	+ struct can_frame *cf;
	782	+ struct sk_buff *skb;
	783	+
	784	+ /* propagate the error condition to the CAN stack */
	785	+ skb = alloc_can_err_skb(dev, &cf);
	786	+
	787	+ /* update tx error stats since there is protocol error */
	788	+ stats->tx_errors++;
	789	+
	790	+ /* update arbitration lost status */
	791	+ if (cdev->version >= 31 && (irqstatus & IR_PEA)) {
	792	+ netdev_dbg(dev, "Protocol error in Arbitration fail\n");
	793	+ cdev->can.can_stats.arbitration_lost++;
	794	+ if (skb) {
	795	+ cf->can_id \|= CAN_ERR_LOSTARB;
	796	+ cf->data[0] \|= CAN_ERR_LOSTARB_UNSPEC;
	797	+ }
	798	+ }
	799	+
	800	+ if (unlikely(!skb)) {
	801	+ netdev_dbg(dev, "allocation of skb failed\n");
	802	+ return 0;
	803	+ }
	804	+ netif_receive_skb(skb);
	805	+
	806	+ return 1;
	807	+}
	808	+
789	809	static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
790	810	u32 psr)
791	811	{
792		- struct m_can_priv *priv = netdev_priv(dev);
	812	+ struct m_can_classdev *cdev = netdev_priv(dev);
793	813	int work_done = 0;
794	814
795	815	if (irqstatus & IR_RF0L)
796	816	work_done += m_can_handle_lost_msg(dev);
797	817
798	818	/* handle lec errors on the bus */
799		- if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
	819	+ if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
800	820	is_lec_err(psr))
801	821	work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
	822	+
	823	+ /* handle protocol errors in arbitration phase */
	824	+ if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
	825	+ m_can_is_protocol_err(irqstatus))
	826	+ work_done += m_can_handle_protocol_error(dev, irqstatus);
802	827
803	828	/* other unproccessed error interrupts */
804	829	m_can_handle_other_err(dev, irqstatus);
..	..	@@ -806,14 +831,13 @@
806	831	return work_done;
807	832	}
808	833
809		-static int m_can_poll(struct napi_struct *napi, int quota)
	834	+static int m_can_rx_handler(struct net_device *dev, int quota)
810	835	{
811		- struct net_device *dev = napi->dev;
812		- struct m_can_priv *priv = netdev_priv(dev);
	836	+ struct m_can_classdev *cdev = netdev_priv(dev);
813	837	int work_done = 0;
814	838	u32 irqstatus, psr;
815	839
816		- irqstatus = priv->irqstatus \| m_can_read(priv, M_CAN_IR);
	840	+ irqstatus = cdev->irqstatus \| m_can_read(cdev, M_CAN_IR);
817	841	if (!irqstatus)
818	842	goto end;
819	843
..	..	@@ -827,18 +851,19 @@
827	851	* whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127.
828	852	* In this case, reset MCAN_IR.MRAF. No further action is required.
829	853	*/
830		- if ((priv->version <= 31) && (irqstatus & IR_MRAF) &&
831		- (m_can_read(priv, M_CAN_ECR) & ECR_RP)) {
	854	+ if (cdev->version <= 31 && irqstatus & IR_MRAF &&
	855	+ m_can_read(cdev, M_CAN_ECR) & ECR_RP) {
832	856	struct can_berr_counter bec;
833	857
834	858	__m_can_get_berr_counter(dev, &bec);
835	859	if (bec.rxerr == 127) {
836		- m_can_write(priv, M_CAN_IR, IR_MRAF);
	860	+ m_can_write(cdev, M_CAN_IR, IR_MRAF);
837	861	irqstatus &= ~IR_MRAF;
838	862	}
839	863	}
840	864
841		- psr = m_can_read(priv, M_CAN_PSR);
	865	+ psr = m_can_read(cdev, M_CAN_PSR);
	866	+
842	867	if (irqstatus & IR_ERR_STATE)
843	868	work_done += m_can_handle_state_errors(dev, psr);
844	869
..	..	@@ -847,13 +872,33 @@
847	872
848	873	if (irqstatus & IR_RF0N)
849	874	work_done += m_can_do_rx_poll(dev, (quota - work_done));
	875	+end:
	876	+ return work_done;
	877	+}
850	878
	879	+static int m_can_rx_peripheral(struct net_device *dev)
	880	+{
	881	+ struct m_can_classdev *cdev = netdev_priv(dev);
	882	+
	883	+ m_can_rx_handler(dev, M_CAN_NAPI_WEIGHT);
	884	+
	885	+ m_can_enable_all_interrupts(cdev);
	886	+
	887	+ return 0;
	888	+}
	889	+
	890	+static int m_can_poll(struct napi_struct *napi, int quota)
	891	+{
	892	+ struct net_device *dev = napi->dev;
	893	+ struct m_can_classdev *cdev = netdev_priv(dev);
	894	+ int work_done;
	895	+
	896	+ work_done = m_can_rx_handler(dev, quota);
851	897	if (work_done < quota) {
852	898	napi_complete_done(napi, work_done);
853		- m_can_enable_all_interrupts(priv);
	899	+ m_can_enable_all_interrupts(cdev);
854	900	}
855	901
856		-end:
857	902	return work_done;
858	903	}
859	904
..	..	@@ -865,11 +910,11 @@
865	910	int i = 0;
866	911	unsigned int msg_mark;
867	912
868		- struct m_can_priv *priv = netdev_priv(dev);
	913	+ struct m_can_classdev *cdev = netdev_priv(dev);
869	914	struct net_device_stats *stats = &dev->stats;
870	915
871	916	/* read tx event fifo status */
872		- m_can_txefs = m_can_read(priv, M_CAN_TXEFS);
	917	+ m_can_txefs = m_can_read(cdev, M_CAN_TXEFS);
873	918
874	919	/* Get Tx Event fifo element count */
875	920	txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
..	..	@@ -878,15 +923,15 @@
878	923	/* Get and process all sent elements */
879	924	for (i = 0; i < txe_count; i++) {
880	925	/* retrieve get index */
881		- fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
	926	+ fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
882	927	>> TXEFS_EFGI_SHIFT;
883	928
884	929	/* get message marker */
885		- msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) &
	930	+ msg_mark = (m_can_txe_fifo_read(cdev, fgi, 4) &
886	931	TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
887	932
888	933	/* ack txe element */
889		- m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
	934	+ m_can_write(cdev, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
890	935	(fgi << TXEFA_EFAI_SHIFT)));
891	936
892	937	/* update stats */
..	..	@@ -898,17 +943,22 @@
898	943	static irqreturn_t m_can_isr(int irq, void *dev_id)
899	944	{
900	945	struct net_device dev = (struct net_device )dev_id;
901		- struct m_can_priv *priv = netdev_priv(dev);
	946	+ struct m_can_classdev *cdev = netdev_priv(dev);
902	947	struct net_device_stats *stats = &dev->stats;
903	948	u32 ir;
904	949
905		- ir = m_can_read(priv, M_CAN_IR);
	950	+ if (pm_runtime_suspended(cdev->dev))
	951	+ return IRQ_NONE;
	952	+ ir = m_can_read(cdev, M_CAN_IR);
906	953	if (!ir)
907	954	return IRQ_NONE;
908	955
909	956	/* ACK all irqs */
910	957	if (ir & IR_ALL_INT)
911		- m_can_write(priv, M_CAN_IR, ir);
	958	+ m_can_write(cdev, M_CAN_IR, ir);
	959	+
	960	+ if (cdev->ops->clear_interrupts)
	961	+ cdev->ops->clear_interrupts(cdev);
912	962
913	963	/* schedule NAPI in case of
914	964	* - rx IRQ
..	..	@@ -916,12 +966,15 @@
916	966	* - bus error IRQ and bus error reporting
917	967	*/
918	968	if ((ir & IR_RF0N) \|\| (ir & IR_ERR_ALL_30X)) {
919		- priv->irqstatus = ir;
920		- m_can_disable_all_interrupts(priv);
921		- napi_schedule(&priv->napi);
	969	+ cdev->irqstatus = ir;
	970	+ m_can_disable_all_interrupts(cdev);
	971	+ if (!cdev->is_peripheral)
	972	+ napi_schedule(&cdev->napi);
	973	+ else
	974	+ m_can_rx_peripheral(dev);
922	975	}
923	976
924		- if (priv->version == 30) {
	977	+ if (cdev->version == 30) {
925	978	if (ir & IR_TC) {
926	979	/* Transmission Complete Interrupt*/
927	980	stats->tx_bytes += can_get_echo_skb(dev, 0);
..	..	@@ -935,7 +988,7 @@
935	988	m_can_echo_tx_event(dev);
936	989	can_led_event(dev, CAN_LED_EVENT_TX);
937	990	if (netif_queue_stopped(dev) &&
938		- !m_can_tx_fifo_full(priv))
	991	+ !m_can_tx_fifo_full(cdev))
939	992	netif_wake_queue(dev);
940	993	}
941	994	}
..	..	@@ -993,9 +1046,9 @@
993	1046
994	1047	static int m_can_set_bittiming(struct net_device *dev)
995	1048	{
996		- struct m_can_priv *priv = netdev_priv(dev);
997		- const struct can_bittiming *bt = &priv->can.bittiming;
998		- const struct can_bittiming *dbt = &priv->can.data_bittiming;
	1049	+ struct m_can_classdev *cdev = netdev_priv(dev);
	1050	+ const struct can_bittiming *bt = &cdev->can.bittiming;
	1051	+ const struct can_bittiming *dbt = &cdev->can.data_bittiming;
999	1052	u16 brp, sjw, tseg1, tseg2;
1000	1053	u32 reg_btp;
1001	1054
..	..	@@ -1005,9 +1058,9 @@
1005	1058	tseg2 = bt->phase_seg2 - 1;
1006	1059	reg_btp = (brp << NBTP_NBRP_SHIFT) \| (sjw << NBTP_NSJW_SHIFT) \|
1007	1060	(tseg1 << NBTP_NTSEG1_SHIFT) \| (tseg2 << NBTP_NTSEG2_SHIFT);
1008		- m_can_write(priv, M_CAN_NBTP, reg_btp);
	1061	+ m_can_write(cdev, M_CAN_NBTP, reg_btp);
1009	1062
1010		- if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
	1063	+ if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1011	1064	reg_btp = 0;
1012	1065	brp = dbt->brp - 1;
1013	1066	sjw = dbt->sjw - 1;
..	..	@@ -1029,7 +1082,7 @@
1029	1082	/* Equation based on Bosch's M_CAN User Manual's
1030	1083	* Transmitter Delay Compensation Section
1031	1084	*/
1032		- tdco = (priv->can.clock.freq / 1000) *
	1085	+ tdco = (cdev->can.clock.freq / 1000) *
1033	1086	ssp / dbt->bitrate;
1034	1087
1035	1088	/* Max valid TDCO value is 127 */
..	..	@@ -1040,7 +1093,7 @@
1040	1093	}
1041	1094
1042	1095	reg_btp \|= DBTP_TDC;
1043		- m_can_write(priv, M_CAN_TDCR,
	1096	+ m_can_write(cdev, M_CAN_TDCR,
1044	1097	tdco << TDCR_TDCO_SHIFT);
1045	1098	}
1046	1099
..	..	@@ -1049,7 +1102,7 @@
1049	1102	(tseg1 << DBTP_DTSEG1_SHIFT) \|
1050	1103	(tseg2 << DBTP_DTSEG2_SHIFT);
1051	1104
1052		- m_can_write(priv, M_CAN_DBTP, reg_btp);
	1105	+ m_can_write(cdev, M_CAN_DBTP, reg_btp);
1053	1106	}
1054	1107
1055	1108	return 0;
..	..	@@ -1066,129 +1119,137 @@
1066	1119	*/
1067	1120	static void m_can_chip_config(struct net_device *dev)
1068	1121	{
1069		- struct m_can_priv *priv = netdev_priv(dev);
	1122	+ struct m_can_classdev *cdev = netdev_priv(dev);
1070	1123	u32 cccr, test;
1071	1124
1072		- m_can_config_endisable(priv, true);
	1125	+ m_can_config_endisable(cdev, true);
1073	1126
1074	1127	/* RX Buffer/FIFO Element Size 64 bytes data field */
1075		- m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_64BYTES);
	1128	+ m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES);
1076	1129
1077	1130	/* Accept Non-matching Frames Into FIFO 0 */
1078		- m_can_write(priv, M_CAN_GFC, 0x0);
	1131	+ m_can_write(cdev, M_CAN_GFC, 0x0);
1079	1132
1080		- if (priv->version == 30) {
	1133	+ if (cdev->version == 30) {
1081	1134	/* only support one Tx Buffer currently */
1082		- m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) \|
1083		- priv->mcfg[MRAM_TXB].off);
	1135	+ m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) \|
	1136	+ cdev->mcfg[MRAM_TXB].off);
1084	1137	} else {
1085	1138	/* TX FIFO is used for newer IP Core versions */
1086		- m_can_write(priv, M_CAN_TXBC,
1087		- (priv->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) \|
1088		- (priv->mcfg[MRAM_TXB].off));
	1139	+ m_can_write(cdev, M_CAN_TXBC,
	1140	+ (cdev->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) \|
	1141	+ (cdev->mcfg[MRAM_TXB].off));
1089	1142	}
1090	1143
1091	1144	/* support 64 bytes payload */
1092		- m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES);
	1145	+ m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES);
1093	1146
1094	1147	/* TX Event FIFO */
1095		- if (priv->version == 30) {
1096		- m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) \|
1097		- priv->mcfg[MRAM_TXE].off);
	1148	+ if (cdev->version == 30) {
	1149	+ m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) \|
	1150	+ cdev->mcfg[MRAM_TXE].off);
1098	1151	} else {
1099	1152	/* Full TX Event FIFO is used */
1100		- m_can_write(priv, M_CAN_TXEFC,
1101		- ((priv->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT)
	1153	+ m_can_write(cdev, M_CAN_TXEFC,
	1154	+ ((cdev->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT)
1102	1155	& TXEFC_EFS_MASK) \|
1103		- priv->mcfg[MRAM_TXE].off);
	1156	+ cdev->mcfg[MRAM_TXE].off);
1104	1157	}
1105	1158
1106	1159	/* rx fifo configuration, blocking mode, fifo size 1 */
1107		- m_can_write(priv, M_CAN_RXF0C,
1108		- (priv->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) \|
1109		- priv->mcfg[MRAM_RXF0].off);
	1160	+ m_can_write(cdev, M_CAN_RXF0C,
	1161	+ (cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) \|
	1162	+ cdev->mcfg[MRAM_RXF0].off);
1110	1163
1111		- m_can_write(priv, M_CAN_RXF1C,
1112		- (priv->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) \|
1113		- priv->mcfg[MRAM_RXF1].off);
	1164	+ m_can_write(cdev, M_CAN_RXF1C,
	1165	+ (cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) \|
	1166	+ cdev->mcfg[MRAM_RXF1].off);
1114	1167
1115		- cccr = m_can_read(priv, M_CAN_CCCR);
1116		- test = m_can_read(priv, M_CAN_TEST);
	1168	+ cccr = m_can_read(cdev, M_CAN_CCCR);
	1169	+ test = m_can_read(cdev, M_CAN_TEST);
1117	1170	test &= ~TEST_LBCK;
1118		- if (priv->version == 30) {
	1171	+ if (cdev->version == 30) {
1119	1172	/* Version 3.0.x */
1120	1173
1121		- cccr &= ~(CCCR_TEST \| CCCR_MON \|
	1174	+ cccr &= ~(CCCR_TEST \| CCCR_MON \| CCCR_DAR \|
1122	1175	(CCCR_CMR_MASK << CCCR_CMR_SHIFT) \|
1123	1176	(CCCR_CME_MASK << CCCR_CME_SHIFT));
1124	1177
1125		- if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
	1178	+ if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1126	1179	cccr \|= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
1127	1180
1128	1181	} else {
1129	1182	/* Version 3.1.x or 3.2.x */
1130	1183	cccr &= ~(CCCR_TEST \| CCCR_MON \| CCCR_BRSE \| CCCR_FDOE \|
1131		- CCCR_NISO);
	1184	+ CCCR_NISO \| CCCR_DAR);
1132	1185
1133	1186	/* Only 3.2.x has NISO Bit implemented */
1134		- if (priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
	1187	+ if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
1135	1188	cccr \|= CCCR_NISO;
1136	1189
1137		- if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
	1190	+ if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1138	1191	cccr \|= (CCCR_BRSE \| CCCR_FDOE);
1139	1192	}
1140	1193
1141	1194	/* Loopback Mode */
1142		- if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
	1195	+ if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1143	1196	cccr \|= CCCR_TEST \| CCCR_MON;
1144	1197	test \|= TEST_LBCK;
1145	1198	}
1146	1199
1147	1200	/* Enable Monitoring (all versions) */
1148		- if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
	1201	+ if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1149	1202	cccr \|= CCCR_MON;
1150	1203
	1204	+ /* Disable Auto Retransmission (all versions) */
	1205	+ if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
	1206	+ cccr \|= CCCR_DAR;
	1207	+
1151	1208	/* Write config */
1152		- m_can_write(priv, M_CAN_CCCR, cccr);
1153		- m_can_write(priv, M_CAN_TEST, test);
	1209	+ m_can_write(cdev, M_CAN_CCCR, cccr);
	1210	+ m_can_write(cdev, M_CAN_TEST, test);
1154	1211
1155	1212	/* Enable interrupts */
1156		- m_can_write(priv, M_CAN_IR, IR_ALL_INT);
1157		- if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1158		- if (priv->version == 30)
1159		- m_can_write(priv, M_CAN_IE, IR_ALL_INT &
	1213	+ m_can_write(cdev, M_CAN_IR, IR_ALL_INT);
	1214	+ if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
	1215	+ if (cdev->version == 30)
	1216	+ m_can_write(cdev, M_CAN_IE, IR_ALL_INT &
1160	1217	~(IR_ERR_LEC_30X));
1161	1218	else
1162		- m_can_write(priv, M_CAN_IE, IR_ALL_INT &
	1219	+ m_can_write(cdev, M_CAN_IE, IR_ALL_INT &
1163	1220	~(IR_ERR_LEC_31X));
1164	1221	else
1165		- m_can_write(priv, M_CAN_IE, IR_ALL_INT);
	1222	+ m_can_write(cdev, M_CAN_IE, IR_ALL_INT);
1166	1223
1167	1224	/* route all interrupts to INT0 */
1168		- m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0);
	1225	+ m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0);
1169	1226
1170	1227	/* set bittiming params */
1171	1228	m_can_set_bittiming(dev);
1172	1229
1173		- m_can_config_endisable(priv, false);
	1230	+ m_can_config_endisable(cdev, false);
	1231	+
	1232	+ if (cdev->ops->init)
	1233	+ cdev->ops->init(cdev);
1174	1234	}
1175	1235
1176	1236	static void m_can_start(struct net_device *dev)
1177	1237	{
1178		- struct m_can_priv *priv = netdev_priv(dev);
	1238	+ struct m_can_classdev *cdev = netdev_priv(dev);
1179	1239
1180	1240	/* basic m_can configuration */
1181	1241	m_can_chip_config(dev);
1182	1242
1183		- priv->can.state = CAN_STATE_ERROR_ACTIVE;
	1243	+ cdev->can.state = CAN_STATE_ERROR_ACTIVE;
1184	1244
1185		- m_can_enable_all_interrupts(priv);
	1245	+ m_can_enable_all_interrupts(cdev);
1186	1246	}
1187	1247
1188	1248	static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
1189	1249	{
1190	1250	switch (mode) {
1191	1251	case CAN_MODE_START:
	1252	+ m_can_clean(dev);
1192	1253	m_can_start(dev);
1193	1254	netif_wake_queue(dev);
1194	1255	break;
..	..	@@ -1204,20 +1265,17 @@
1204	1265	* else it returns the release and step coded as:
1205	1266	* return value = 10 * <release> + 1 * <step>
1206	1267	*/
1207		-static int m_can_check_core_release(void __iomem *m_can_base)
	1268	+static int m_can_check_core_release(struct m_can_classdev *cdev)
1208	1269	{
1209	1270	u32 crel_reg;
1210	1271	u8 rel;
1211	1272	u8 step;
1212	1273	int res;
1213		- struct m_can_priv temp_priv = {
1214		- .base = m_can_base
1215		- };
1216	1274
1217	1275	/* Read Core Release Version and split into version number
1218	1276	* Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
1219	1277	*/
1220		- crel_reg = m_can_read(&temp_priv, M_CAN_CREL);
	1278	+ crel_reg = m_can_read(cdev, M_CAN_CREL);
1221	1279	rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT);
1222	1280	step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT);
1223	1281
..	..	@@ -1235,152 +1293,148 @@
1235	1293	/* Selectable Non ISO support only in version 3.2.x
1236	1294	* This function checks if the bit is writable.
1237	1295	*/
1238		-static bool m_can_niso_supported(const struct m_can_priv *priv)
	1296	+static bool m_can_niso_supported(struct m_can_classdev *cdev)
1239	1297	{
1240		- u32 cccr_reg, cccr_poll;
1241		- int niso_timeout;
	1298	+ u32 cccr_reg, cccr_poll = 0;
	1299	+ int niso_timeout = -ETIMEDOUT;
	1300	+ int i;
1242	1301
1243		- m_can_config_endisable(priv, true);
1244		- cccr_reg = m_can_read(priv, M_CAN_CCCR);
	1302	+ m_can_config_endisable(cdev, true);
	1303	+ cccr_reg = m_can_read(cdev, M_CAN_CCCR);
1245	1304	cccr_reg \|= CCCR_NISO;
1246		- m_can_write(priv, M_CAN_CCCR, cccr_reg);
	1305	+ m_can_write(cdev, M_CAN_CCCR, cccr_reg);
1247	1306
1248		- niso_timeout = readl_poll_timeout((priv->base + M_CAN_CCCR), cccr_poll,
1249		- (cccr_poll == cccr_reg), 0, 10);
	1307	+ for (i = 0; i <= 10; i++) {
	1308	+ cccr_poll = m_can_read(cdev, M_CAN_CCCR);
	1309	+ if (cccr_poll == cccr_reg) {
	1310	+ niso_timeout = 0;
	1311	+ break;
	1312	+ }
	1313	+
	1314	+ usleep_range(1, 5);
	1315	+ }
1250	1316
1251	1317	/* Clear NISO */
1252	1318	cccr_reg &= ~(CCCR_NISO);
1253		- m_can_write(priv, M_CAN_CCCR, cccr_reg);
	1319	+ m_can_write(cdev, M_CAN_CCCR, cccr_reg);
1254	1320
1255		- m_can_config_endisable(priv, false);
	1321	+ m_can_config_endisable(cdev, false);
1256	1322
1257	1323	/* return false if time out (-ETIMEDOUT), else return true */
1258	1324	return !niso_timeout;
1259	1325	}
1260	1326
1261		-static int m_can_dev_setup(struct platform_device pdev, struct net_device dev,
1262		- void __iomem *addr)
	1327	+static int m_can_dev_setup(struct m_can_classdev *m_can_dev)
1263	1328	{
1264		- struct m_can_priv *priv;
	1329	+ struct net_device *dev = m_can_dev->net;
1265	1330	int m_can_version;
1266	1331
1267		- m_can_version = m_can_check_core_release(addr);
	1332	+ m_can_version = m_can_check_core_release(m_can_dev);
1268	1333	/* return if unsupported version */
1269	1334	if (!m_can_version) {
1270		- dev_err(&pdev->dev, "Unsupported version number: %2d",
	1335	+ dev_err(m_can_dev->dev, "Unsupported version number: %2d",
1271	1336	m_can_version);
1272	1337	return -EINVAL;
1273	1338	}
1274	1339
1275		- priv = netdev_priv(dev);
1276		- netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
	1340	+ if (!m_can_dev->is_peripheral)
	1341	+ netif_napi_add(dev, &m_can_dev->napi,
	1342	+ m_can_poll, M_CAN_NAPI_WEIGHT);
1277	1343
1278	1344	/* Shared properties of all M_CAN versions */
1279		- priv->version = m_can_version;
1280		- priv->dev = dev;
1281		- priv->base = addr;
1282		- priv->can.do_set_mode = m_can_set_mode;
1283		- priv->can.do_get_berr_counter = m_can_get_berr_counter;
	1345	+ m_can_dev->version = m_can_version;
	1346	+ m_can_dev->can.do_set_mode = m_can_set_mode;
	1347	+ m_can_dev->can.do_get_berr_counter = m_can_get_berr_counter;
1284	1348
1285	1349	/* Set M_CAN supported operations */
1286		- priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK \|
	1350	+ m_can_dev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK \|
1287	1351	CAN_CTRLMODE_LISTENONLY \|
1288	1352	CAN_CTRLMODE_BERR_REPORTING \|
1289		- CAN_CTRLMODE_FD;
	1353	+ CAN_CTRLMODE_FD \|
	1354	+ CAN_CTRLMODE_ONE_SHOT;
1290	1355
1291	1356	/* Set properties depending on M_CAN version */
1292		- switch (priv->version) {
	1357	+ switch (m_can_dev->version) {
1293	1358	case 30:
1294	1359	/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
1295	1360	can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1296		- priv->can.bittiming_const = &m_can_bittiming_const_30X;
1297		- priv->can.data_bittiming_const =
1298		- &m_can_data_bittiming_const_30X;
	1361	+ m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
	1362	+ m_can_dev->bit_timing : &m_can_bittiming_const_30X;
	1363	+
	1364	+ m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
	1365	+ m_can_dev->data_timing :
	1366	+ &m_can_data_bittiming_const_30X;
1299	1367	break;
1300	1368	case 31:
1301	1369	/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
1302	1370	can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1303		- priv->can.bittiming_const = &m_can_bittiming_const_31X;
1304		- priv->can.data_bittiming_const =
1305		- &m_can_data_bittiming_const_31X;
	1371	+ m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
	1372	+ m_can_dev->bit_timing : &m_can_bittiming_const_31X;
	1373	+
	1374	+ m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
	1375	+ m_can_dev->data_timing :
	1376	+ &m_can_data_bittiming_const_31X;
1306	1377	break;
1307	1378	case 32:
1308		- priv->can.bittiming_const = &m_can_bittiming_const_31X;
1309		- priv->can.data_bittiming_const =
1310		- &m_can_data_bittiming_const_31X;
1311		- priv->can.ctrlmode_supported \|= (m_can_niso_supported(priv)
	1379	+ case 33:
	1380	+ /* Support both MCAN version v3.2.x and v3.3.0 */
	1381	+ m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
	1382	+ m_can_dev->bit_timing : &m_can_bittiming_const_31X;
	1383	+
	1384	+ m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
	1385	+ m_can_dev->data_timing :
	1386	+ &m_can_data_bittiming_const_31X;
	1387	+
	1388	+ m_can_dev->can.ctrlmode_supported \|=
	1389	+ (m_can_niso_supported(m_can_dev)
1312	1390	? CAN_CTRLMODE_FD_NON_ISO
1313	1391	: 0);
1314	1392	break;
1315	1393	default:
1316		- dev_err(&pdev->dev, "Unsupported version number: %2d",
1317		- priv->version);
	1394	+ dev_err(m_can_dev->dev, "Unsupported version number: %2d",
	1395	+ m_can_dev->version);
1318	1396	return -EINVAL;
1319	1397	}
1320	1398
1321		- return 0;
1322		-}
1323		-
1324		-static int m_can_open(struct net_device *dev)
1325		-{
1326		- struct m_can_priv *priv = netdev_priv(dev);
1327		- int err;
1328		-
1329		- err = m_can_clk_start(priv);
1330		- if (err)
1331		- return err;
1332		-
1333		- /* open the can device */
1334		- err = open_candev(dev);
1335		- if (err) {
1336		- netdev_err(dev, "failed to open can device\n");
1337		- goto exit_disable_clks;
1338		- }
1339		-
1340		- /* register interrupt handler */
1341		- err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
1342		- dev);
1343		- if (err < 0) {
1344		- netdev_err(dev, "failed to request interrupt\n");
1345		- goto exit_irq_fail;
1346		- }
1347		-
1348		- /* start the m_can controller */
1349		- m_can_start(dev);
1350		-
1351		- can_led_event(dev, CAN_LED_EVENT_OPEN);
1352		- napi_enable(&priv->napi);
1353		- netif_start_queue(dev);
	1399	+ if (m_can_dev->ops->init)
	1400	+ m_can_dev->ops->init(m_can_dev);
1354	1401
1355	1402	return 0;
1356		-
1357		-exit_irq_fail:
1358		- close_candev(dev);
1359		-exit_disable_clks:
1360		- m_can_clk_stop(priv);
1361		- return err;
1362	1403	}
1363	1404
1364	1405	static void m_can_stop(struct net_device *dev)
1365	1406	{
1366		- struct m_can_priv *priv = netdev_priv(dev);
	1407	+ struct m_can_classdev *cdev = netdev_priv(dev);
1367	1408
1368	1409	/* disable all interrupts */
1369		- m_can_disable_all_interrupts(priv);
	1410	+ m_can_disable_all_interrupts(cdev);
	1411	+
	1412	+ /* Set init mode to disengage from the network */
	1413	+ m_can_config_endisable(cdev, true);
1370	1414
1371	1415	/* set the state as STOPPED */
1372		- priv->can.state = CAN_STATE_STOPPED;
	1416	+ cdev->can.state = CAN_STATE_STOPPED;
1373	1417	}
1374	1418
1375	1419	static int m_can_close(struct net_device *dev)
1376	1420	{
1377		- struct m_can_priv *priv = netdev_priv(dev);
	1421	+ struct m_can_classdev *cdev = netdev_priv(dev);
1378	1422
1379	1423	netif_stop_queue(dev);
1380		- napi_disable(&priv->napi);
	1424	+
	1425	+ if (!cdev->is_peripheral)
	1426	+ napi_disable(&cdev->napi);
	1427	+
1381	1428	m_can_stop(dev);
1382		- m_can_clk_stop(priv);
	1429	+ m_can_clk_stop(cdev);
1383	1430	free_irq(dev->irq, dev);
	1431	+
	1432	+ if (cdev->is_peripheral) {
	1433	+ cdev->tx_skb = NULL;
	1434	+ destroy_workqueue(cdev->tx_wq);
	1435	+ cdev->tx_wq = NULL;
	1436	+ }
	1437	+
1384	1438	close_candev(dev);
1385	1439	can_led_event(dev, CAN_LED_EVENT_STOP);
1386	1440
..	..	@@ -1389,29 +1443,28 @@
1389	1443
1390	1444	static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
1391	1445	{
1392		- struct m_can_priv *priv = netdev_priv(dev);
	1446	+ struct m_can_classdev *cdev = netdev_priv(dev);
1393	1447	/get wrap around for loopback skb index /
1394		- unsigned int wrap = priv->can.echo_skb_max;
	1448	+ unsigned int wrap = cdev->can.echo_skb_max;
1395	1449	int next_idx;
1396	1450
1397	1451	/* calculate next index */
1398	1452	next_idx = (++putidx >= wrap ? 0 : putidx);
1399	1453
1400	1454	/* check if occupied */
1401		- return !!priv->can.echo_skb[next_idx];
	1455	+ return !!cdev->can.echo_skb[next_idx];
1402	1456	}
1403	1457
1404		-static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
1405		- struct net_device *dev)
	1458	+static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
1406	1459	{
1407		- struct m_can_priv *priv = netdev_priv(dev);
1408		- struct canfd_frame cf = (struct canfd_frame )skb->data;
	1460	+ struct canfd_frame cf = (struct canfd_frame )cdev->tx_skb->data;
	1461	+ struct net_device *dev = cdev->net;
	1462	+ struct sk_buff *skb = cdev->tx_skb;
1409	1463	u32 id, cccr, fdflags;
1410	1464	int i;
1411	1465	int putidx;
1412	1466
1413		- if (can_dropped_invalid_skb(dev, skb))
1414		- return NETDEV_TX_OK;
	1467	+ cdev->tx_skb = NULL;
1415	1468
1416	1469	/* Generate ID field for TX buffer Element */
1417	1470	/* Common to all supported M_CAN versions */
..	..	@@ -1425,23 +1478,21 @@
1425	1478	if (cf->can_id & CAN_RTR_FLAG)
1426	1479	id \|= TX_BUF_RTR;
1427	1480
1428		- if (priv->version == 30) {
	1481	+ if (cdev->version == 30) {
1429	1482	netif_stop_queue(dev);
1430	1483
1431	1484	/* message ram configuration */
1432		- m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
1433		- m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC,
	1485	+ m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, id);
	1486	+ m_can_fifo_write(cdev, 0, M_CAN_FIFO_DLC,
1434	1487	can_len2dlc(cf->len) << 16);
1435	1488
1436	1489	for (i = 0; i < cf->len; i += 4)
1437		- m_can_fifo_write(priv, 0,
	1490	+ m_can_fifo_write(cdev, 0,
1438	1491	M_CAN_FIFO_DATA(i / 4),
1439	1492	(u32 )(cf->data + i));
1440	1493
1441		- can_put_echo_skb(skb, dev, 0);
1442		-
1443		- if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1444		- cccr = m_can_read(priv, M_CAN_CCCR);
	1494	+ if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
	1495	+ cccr = m_can_read(cdev, M_CAN_CCCR);
1445	1496	cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
1446	1497	if (can_is_canfd_skb(skb)) {
1447	1498	if (cf->flags & CANFD_BRS)
..	..	@@ -1453,28 +1504,38 @@
1453	1504	} else {
1454	1505	cccr \|= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
1455	1506	}
1456		- m_can_write(priv, M_CAN_CCCR, cccr);
	1507	+ m_can_write(cdev, M_CAN_CCCR, cccr);
1457	1508	}
1458		- m_can_write(priv, M_CAN_TXBTIE, 0x1);
1459		- m_can_write(priv, M_CAN_TXBAR, 0x1);
	1509	+ m_can_write(cdev, M_CAN_TXBTIE, 0x1);
	1510	+
	1511	+ can_put_echo_skb(skb, dev, 0);
	1512	+
	1513	+ m_can_write(cdev, M_CAN_TXBAR, 0x1);
1460	1514	/* End of xmit function for version 3.0.x */
1461	1515	} else {
1462	1516	/* Transmit routine for version >= v3.1.x */
1463	1517
1464	1518	/* Check if FIFO full */
1465		- if (m_can_tx_fifo_full(priv)) {
	1519	+ if (m_can_tx_fifo_full(cdev)) {
1466	1520	/* This shouldn't happen */
1467	1521	netif_stop_queue(dev);
1468	1522	netdev_warn(dev,
1469	1523	"TX queue active although FIFO is full.");
1470		- return NETDEV_TX_BUSY;
	1524	+
	1525	+ if (cdev->is_peripheral) {
	1526	+ kfree_skb(skb);
	1527	+ dev->stats.tx_dropped++;
	1528	+ return NETDEV_TX_OK;
	1529	+ } else {
	1530	+ return NETDEV_TX_BUSY;
	1531	+ }
1471	1532	}
1472	1533
1473	1534	/* get put index for frame */
1474		- putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
	1535	+ putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
1475	1536	>> TXFQS_TFQPI_SHIFT);
1476	1537	/* Write ID Field to FIFO Element */
1477		- m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id);
	1538	+ m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id);
1478	1539
1479	1540	/* get CAN FD configuration of frame */
1480	1541	fdflags = 0;
..	..	@@ -1489,14 +1550,14 @@
1489	1550	* it is used in TX interrupt for
1490	1551	* sending the correct echo frame
1491	1552	*/
1492		- m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC,
	1553	+ m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC,
1493	1554	((putidx << TX_BUF_MM_SHIFT) &
1494	1555	TX_BUF_MM_MASK) \|
1495	1556	(can_len2dlc(cf->len) << 16) \|
1496	1557	fdflags \| TX_BUF_EFC);
1497	1558
1498	1559	for (i = 0; i < cf->len; i += 4)
1499		- m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4),
	1560	+ m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA(i / 4),
1500	1561	(u32 )(cf->data + i));
1501	1562
1502	1563	/* Push loopback echo.
..	..	@@ -1505,15 +1566,120 @@
1505	1566	can_put_echo_skb(skb, dev, putidx);
1506	1567
1507	1568	/* Enable TX FIFO element to start transfer */
1508		- m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
	1569	+ m_can_write(cdev, M_CAN_TXBAR, (1 << putidx));
1509	1570
1510	1571	/* stop network queue if fifo full */
1511		- if (m_can_tx_fifo_full(priv) \|\|
1512		- m_can_next_echo_skb_occupied(dev, putidx))
1513		- netif_stop_queue(dev);
	1572	+ if (m_can_tx_fifo_full(cdev) \|\|
	1573	+ m_can_next_echo_skb_occupied(dev, putidx))
	1574	+ netif_stop_queue(dev);
1514	1575	}
1515	1576
1516	1577	return NETDEV_TX_OK;
	1578	+}
	1579	+
	1580	+static void m_can_tx_work_queue(struct work_struct *ws)
	1581	+{
	1582	+ struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev,
	1583	+ tx_work);
	1584	+
	1585	+ m_can_tx_handler(cdev);
	1586	+}
	1587	+
	1588	+static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
	1589	+ struct net_device *dev)
	1590	+{
	1591	+ struct m_can_classdev *cdev = netdev_priv(dev);
	1592	+
	1593	+ if (can_dropped_invalid_skb(dev, skb))
	1594	+ return NETDEV_TX_OK;
	1595	+
	1596	+ if (cdev->is_peripheral) {
	1597	+ if (cdev->tx_skb) {
	1598	+ netdev_err(dev, "hard_xmit called while tx busy\n");
	1599	+ return NETDEV_TX_BUSY;
	1600	+ }
	1601	+
	1602	+ if (cdev->can.state == CAN_STATE_BUS_OFF) {
	1603	+ m_can_clean(dev);
	1604	+ } else {
	1605	+ /* Need to stop the queue to avoid numerous requests
	1606	+ * from being sent. Suggested improvement is to create
	1607	+ * a queueing mechanism that will queue the skbs and
	1608	+ * process them in order.
	1609	+ */
	1610	+ cdev->tx_skb = skb;
	1611	+ netif_stop_queue(cdev->net);
	1612	+ queue_work(cdev->tx_wq, &cdev->tx_work);
	1613	+ }
	1614	+ } else {
	1615	+ cdev->tx_skb = skb;
	1616	+ return m_can_tx_handler(cdev);
	1617	+ }
	1618	+
	1619	+ return NETDEV_TX_OK;
	1620	+}
	1621	+
	1622	+static int m_can_open(struct net_device *dev)
	1623	+{
	1624	+ struct m_can_classdev *cdev = netdev_priv(dev);
	1625	+ int err;
	1626	+
	1627	+ err = m_can_clk_start(cdev);
	1628	+ if (err)
	1629	+ return err;
	1630	+
	1631	+ /* open the can device */
	1632	+ err = open_candev(dev);
	1633	+ if (err) {
	1634	+ netdev_err(dev, "failed to open can device\n");
	1635	+ goto exit_disable_clks;
	1636	+ }
	1637	+
	1638	+ /* register interrupt handler */
	1639	+ if (cdev->is_peripheral) {
	1640	+ cdev->tx_skb = NULL;
	1641	+ cdev->tx_wq = alloc_workqueue("mcan_wq",
	1642	+ WQ_FREEZABLE \| WQ_MEM_RECLAIM, 0);
	1643	+ if (!cdev->tx_wq) {
	1644	+ err = -ENOMEM;
	1645	+ goto out_wq_fail;
	1646	+ }
	1647	+
	1648	+ INIT_WORK(&cdev->tx_work, m_can_tx_work_queue);
	1649	+
	1650	+ err = request_threaded_irq(dev->irq, NULL, m_can_isr,
	1651	+ IRQF_ONESHOT,
	1652	+ dev->name, dev);
	1653	+ } else {
	1654	+ err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
	1655	+ dev);
	1656	+ }
	1657	+
	1658	+ if (err < 0) {
	1659	+ netdev_err(dev, "failed to request interrupt\n");
	1660	+ goto exit_irq_fail;
	1661	+ }
	1662	+
	1663	+ /* start the m_can controller */
	1664	+ m_can_start(dev);
	1665	+
	1666	+ can_led_event(dev, CAN_LED_EVENT_OPEN);
	1667	+
	1668	+ if (!cdev->is_peripheral)
	1669	+ napi_enable(&cdev->napi);
	1670	+
	1671	+ netif_start_queue(dev);
	1672	+
	1673	+ return 0;
	1674	+
	1675	+exit_irq_fail:
	1676	+ if (cdev->is_peripheral)
	1677	+ destroy_workqueue(cdev->tx_wq);
	1678	+out_wq_fail:
	1679	+ close_candev(dev);
	1680	+exit_disable_clks:
	1681	+ m_can_clk_stop(cdev);
	1682	+ return err;
1517	1683	}
1518	1684
1519	1685	static const struct net_device_ops m_can_netdev_ops = {
..	..	@@ -1531,114 +1697,91 @@
1531	1697	return register_candev(dev);
1532	1698	}
1533	1699
1534		-static void m_can_init_ram(struct m_can_priv *priv)
	1700	+static void m_can_of_parse_mram(struct m_can_classdev *cdev,
	1701	+ const u32 *mram_config_vals)
	1702	+{
	1703	+ cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0];
	1704	+ cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1];
	1705	+ cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off +
	1706	+ cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
	1707	+ cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2];
	1708	+ cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off +
	1709	+ cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
	1710	+ cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
	1711	+ (RXFC_FS_MASK >> RXFC_FS_SHIFT);
	1712	+ cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off +
	1713	+ cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
	1714	+ cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
	1715	+ (RXFC_FS_MASK >> RXFC_FS_SHIFT);
	1716	+ cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off +
	1717	+ cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
	1718	+ cdev->mcfg[MRAM_RXB].num = mram_config_vals[5];
	1719	+ cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off +
	1720	+ cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
	1721	+ cdev->mcfg[MRAM_TXE].num = mram_config_vals[6];
	1722	+ cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off +
	1723	+ cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
	1724	+ cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] &
	1725	+ (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
	1726	+
	1727	+ dev_dbg(cdev->dev,
	1728	+ "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
	1729	+ cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num,
	1730	+ cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num,
	1731	+ cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num,
	1732	+ cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num,
	1733	+ cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num,
	1734	+ cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num,
	1735	+ cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num);
	1736	+}
	1737	+
	1738	+void m_can_init_ram(struct m_can_classdev *cdev)
1535	1739	{
1536	1740	int end, i, start;
1537	1741
1538	1742	/* initialize the entire Message RAM in use to avoid possible
1539	1743	* ECC/parity checksum errors when reading an uninitialized buffer
1540	1744	*/
1541		- start = priv->mcfg[MRAM_SIDF].off;
1542		- end = priv->mcfg[MRAM_TXB].off +
1543		- priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
	1745	+ start = cdev->mcfg[MRAM_SIDF].off;
	1746	+ end = cdev->mcfg[MRAM_TXB].off +
	1747	+ cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
	1748	+
1544	1749	for (i = start; i < end; i += 4)
1545		- writel(0x0, priv->mram_base + i);
	1750	+ m_can_fifo_write_no_off(cdev, i, 0x0);
1546	1751	}
	1752	+EXPORT_SYMBOL_GPL(m_can_init_ram);
1547	1753
1548		-static void m_can_of_parse_mram(struct m_can_priv *priv,
1549		- const u32 *mram_config_vals)
	1754	+int m_can_class_get_clocks(struct m_can_classdev *m_can_dev)
1550	1755	{
1551		- priv->mcfg[MRAM_SIDF].off = mram_config_vals[0];
1552		- priv->mcfg[MRAM_SIDF].num = mram_config_vals[1];
1553		- priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off +
1554		- priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1555		- priv->mcfg[MRAM_XIDF].num = mram_config_vals[2];
1556		- priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
1557		- priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1558		- priv->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
1559		- (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1560		- priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
1561		- priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1562		- priv->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
1563		- (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1564		- priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
1565		- priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1566		- priv->mcfg[MRAM_RXB].num = mram_config_vals[5];
1567		- priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off +
1568		- priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1569		- priv->mcfg[MRAM_TXE].num = mram_config_vals[6];
1570		- priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
1571		- priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1572		- priv->mcfg[MRAM_TXB].num = mram_config_vals[7] &
1573		- (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
	1756	+ int ret = 0;
1574	1757
1575		- dev_dbg(priv->device,
1576		- "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1577		- priv->mram_base,
1578		- priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
1579		- priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
1580		- priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num,
1581		- priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num,
1582		- priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num,
1583		- priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num,
1584		- priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num);
	1758	+ m_can_dev->hclk = devm_clk_get(m_can_dev->dev, "hclk");
	1759	+ m_can_dev->cclk = devm_clk_get(m_can_dev->dev, "cclk");
1585	1760
1586		- m_can_init_ram(priv);
	1761	+ if (IS_ERR(m_can_dev->cclk)) {
	1762	+ dev_err(m_can_dev->dev, "no clock found\n");
	1763	+ ret = -ENODEV;
	1764	+ }
	1765	+
	1766	+ return ret;
1587	1767	}
	1768	+EXPORT_SYMBOL_GPL(m_can_class_get_clocks);
1588	1769
1589		-static int m_can_plat_probe(struct platform_device *pdev)
	1770	+struct m_can_classdev m_can_class_allocate_dev(struct device dev)
1590	1771	{
1591		- struct net_device *dev;
1592		- struct m_can_priv *priv;
1593		- struct resource *res;
1594		- void __iomem *addr;
1595		- void __iomem *mram_addr;
1596		- struct clk hclk, cclk;
1597		- int irq, ret;
1598		- struct device_node *np;
	1772	+ struct m_can_classdev *class_dev = NULL;
1599	1773	u32 mram_config_vals[MRAM_CFG_LEN];
	1774	+ struct net_device *net_dev;
1600	1775	u32 tx_fifo_size;
	1776	+ int ret;
1601	1777
1602		- np = pdev->dev.of_node;
1603		-
1604		- hclk = devm_clk_get(&pdev->dev, "hclk");
1605		- cclk = devm_clk_get(&pdev->dev, "cclk");
1606		-
1607		- if (IS_ERR(hclk) \|\| IS_ERR(cclk)) {
1608		- dev_err(&pdev->dev, "no clock found\n");
1609		- ret = -ENODEV;
1610		- goto failed_ret;
1611		- }
1612		-
1613		- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
1614		- addr = devm_ioremap_resource(&pdev->dev, res);
1615		- irq = platform_get_irq_byname(pdev, "int0");
1616		-
1617		- if (IS_ERR(addr) \|\| irq < 0) {
1618		- ret = -EINVAL;
1619		- goto failed_ret;
1620		- }
1621		-
1622		- /* message ram could be shared */
1623		- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
1624		- if (!res) {
1625		- ret = -ENODEV;
1626		- goto failed_ret;
1627		- }
1628		-
1629		- mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1630		- if (!mram_addr) {
1631		- ret = -ENOMEM;
1632		- goto failed_ret;
1633		- }
1634		-
1635		- /* get message ram configuration */
1636		- ret = of_property_read_u32_array(np, "bosch,mram-cfg",
1637		- mram_config_vals,
1638		- sizeof(mram_config_vals) / 4);
	1778	+ ret = fwnode_property_read_u32_array(dev_fwnode(dev),
	1779	+ "bosch,mram-cfg",
	1780	+ mram_config_vals,
	1781	+ sizeof(mram_config_vals) / 4);
1639	1782	if (ret) {
1640		- dev_err(&pdev->dev, "Could not get Message RAM configuration.");
1641		- goto failed_ret;
	1783	+ dev_err(dev, "Could not get Message RAM configuration.");
	1784	+ goto out;
1642	1785	}
1643	1786
1644	1787	/* Get TX FIFO size
..	..	@@ -1647,101 +1790,115 @@
1647	1790	tx_fifo_size = mram_config_vals[7];
1648	1791
1649	1792	/* allocate the m_can device */
1650		- dev = alloc_candev(sizeof(*priv), tx_fifo_size);
1651		- if (!dev) {
1652		- ret = -ENOMEM;
1653		- goto failed_ret;
	1793	+ net_dev = alloc_candev(sizeof(*class_dev), tx_fifo_size);
	1794	+ if (!net_dev) {
	1795	+ dev_err(dev, "Failed to allocate CAN device");
	1796	+ goto out;
1654	1797	}
1655	1798
1656		- priv = netdev_priv(dev);
1657		- dev->irq = irq;
1658		- priv->device = &pdev->dev;
1659		- priv->hclk = hclk;
1660		- priv->cclk = cclk;
1661		- priv->can.clock.freq = clk_get_rate(cclk);
1662		- priv->mram_base = mram_addr;
	1799	+ class_dev = netdev_priv(net_dev);
	1800	+ if (!class_dev) {
	1801	+ dev_err(dev, "Failed to init netdev cdevate");
	1802	+ goto out;
	1803	+ }
1663	1804
1664		- platform_set_drvdata(pdev, dev);
1665		- SET_NETDEV_DEV(dev, &pdev->dev);
	1805	+ class_dev->net = net_dev;
	1806	+ class_dev->dev = dev;
	1807	+ SET_NETDEV_DEV(net_dev, dev);
1666	1808
1667		- /* Enable clocks. Necessary to read Core Release in order to determine
1668		- * M_CAN version
1669		- */
1670		- pm_runtime_enable(&pdev->dev);
1671		- ret = m_can_clk_start(priv);
1672		- if (ret)
1673		- goto pm_runtime_fail;
	1809	+ m_can_of_parse_mram(class_dev, mram_config_vals);
	1810	+out:
	1811	+ return class_dev;
	1812	+}
	1813	+EXPORT_SYMBOL_GPL(m_can_class_allocate_dev);
1674	1814
1675		- ret = m_can_dev_setup(pdev, dev, addr);
	1815	+void m_can_class_free_dev(struct net_device *net)
	1816	+{
	1817	+ free_candev(net);
	1818	+}
	1819	+EXPORT_SYMBOL_GPL(m_can_class_free_dev);
	1820	+
	1821	+int m_can_class_register(struct m_can_classdev *m_can_dev)
	1822	+{
	1823	+ int ret;
	1824	+
	1825	+ if (m_can_dev->pm_clock_support) {
	1826	+ pm_runtime_enable(m_can_dev->dev);
	1827	+ ret = m_can_clk_start(m_can_dev);
	1828	+ if (ret)
	1829	+ goto pm_runtime_fail;
	1830	+ }
	1831	+
	1832	+ ret = m_can_dev_setup(m_can_dev);
1676	1833	if (ret)
1677	1834	goto clk_disable;
1678	1835
1679		- ret = register_m_can_dev(dev);
	1836	+ ret = register_m_can_dev(m_can_dev->net);
1680	1837	if (ret) {
1681		- dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
1682		- KBUILD_MODNAME, ret);
	1838	+ dev_err(m_can_dev->dev, "registering %s failed (err=%d)\n",
	1839	+ m_can_dev->net->name, ret);
1683	1840	goto clk_disable;
1684	1841	}
1685	1842
1686		- m_can_of_parse_mram(priv, mram_config_vals);
	1843	+ devm_can_led_init(m_can_dev->net);
1687	1844
1688		- devm_can_led_init(dev);
	1845	+ of_can_transceiver(m_can_dev->net);
1689	1846
1690		- of_can_transceiver(dev);
1691		-
1692		- dev_info(&pdev->dev, "%s device registered (irq=%d, version=%d)\n",
1693		- KBUILD_MODNAME, dev->irq, priv->version);
	1847	+ dev_info(m_can_dev->dev, "%s device registered (irq=%d, version=%d)\n",
	1848	+ KBUILD_MODNAME, m_can_dev->net->irq, m_can_dev->version);
1694	1849
1695	1850	/* Probe finished
1696	1851	* Stop clocks. They will be reactivated once the M_CAN device is opened
1697	1852	*/
1698	1853	clk_disable:
1699		- m_can_clk_stop(priv);
	1854	+ m_can_clk_stop(m_can_dev);
1700	1855	pm_runtime_fail:
1701	1856	if (ret) {
1702		- pm_runtime_disable(&pdev->dev);
1703		- free_candev(dev);
	1857	+ if (m_can_dev->pm_clock_support)
	1858	+ pm_runtime_disable(m_can_dev->dev);
1704	1859	}
1705		-failed_ret:
	1860	+
1706	1861	return ret;
1707	1862	}
	1863	+EXPORT_SYMBOL_GPL(m_can_class_register);
1708	1864
1709		-static __maybe_unused int m_can_suspend(struct device *dev)
	1865	+int m_can_class_suspend(struct device *dev)
1710	1866	{
1711	1867	struct net_device *ndev = dev_get_drvdata(dev);
1712		- struct m_can_priv *priv = netdev_priv(ndev);
	1868	+ struct m_can_classdev *cdev = netdev_priv(ndev);
1713	1869
1714	1870	if (netif_running(ndev)) {
1715	1871	netif_stop_queue(ndev);
1716	1872	netif_device_detach(ndev);
1717	1873	m_can_stop(ndev);
1718		- m_can_clk_stop(priv);
	1874	+ m_can_clk_stop(cdev);
1719	1875	}
1720	1876
1721	1877	pinctrl_pm_select_sleep_state(dev);
1722	1878
1723		- priv->can.state = CAN_STATE_SLEEPING;
	1879	+ cdev->can.state = CAN_STATE_SLEEPING;
1724	1880
1725	1881	return 0;
1726	1882	}
	1883	+EXPORT_SYMBOL_GPL(m_can_class_suspend);
1727	1884
1728		-static __maybe_unused int m_can_resume(struct device *dev)
	1885	+int m_can_class_resume(struct device *dev)
1729	1886	{
1730	1887	struct net_device *ndev = dev_get_drvdata(dev);
1731		- struct m_can_priv *priv = netdev_priv(ndev);
	1888	+ struct m_can_classdev *cdev = netdev_priv(ndev);
1732	1889
1733	1890	pinctrl_pm_select_default_state(dev);
1734	1891
1735		- priv->can.state = CAN_STATE_ERROR_ACTIVE;
	1892	+ cdev->can.state = CAN_STATE_ERROR_ACTIVE;
1736	1893
1737	1894	if (netif_running(ndev)) {
1738	1895	int ret;
1739	1896
1740		- ret = m_can_clk_start(priv);
	1897	+ ret = m_can_clk_start(cdev);
1741	1898	if (ret)
1742	1899	return ret;
1743	1900
1744		- m_can_init_ram(priv);
	1901	+ m_can_init_ram(cdev);
1745	1902	m_can_start(ndev);
1746	1903	netif_device_attach(ndev);
1747	1904	netif_start_queue(ndev);
..	..	@@ -1749,79 +1906,15 @@
1749	1906
1750	1907	return 0;
1751	1908	}
	1909	+EXPORT_SYMBOL_GPL(m_can_class_resume);
1752	1910
1753		-static void unregister_m_can_dev(struct net_device *dev)
	1911	+void m_can_class_unregister(struct m_can_classdev *m_can_dev)
1754	1912	{
1755		- unregister_candev(dev);
	1913	+ unregister_candev(m_can_dev->net);
1756	1914	}
1757		-
1758		-static int m_can_plat_remove(struct platform_device *pdev)
1759		-{
1760		- struct net_device *dev = platform_get_drvdata(pdev);
1761		-
1762		- unregister_m_can_dev(dev);
1763		-
1764		- pm_runtime_disable(&pdev->dev);
1765		-
1766		- platform_set_drvdata(pdev, NULL);
1767		-
1768		- free_candev(dev);
1769		-
1770		- return 0;
1771		-}
1772		-
1773		-static int __maybe_unused m_can_runtime_suspend(struct device *dev)
1774		-{
1775		- struct net_device *ndev = dev_get_drvdata(dev);
1776		- struct m_can_priv *priv = netdev_priv(ndev);
1777		-
1778		- clk_disable_unprepare(priv->cclk);
1779		- clk_disable_unprepare(priv->hclk);
1780		-
1781		- return 0;
1782		-}
1783		-
1784		-static int __maybe_unused m_can_runtime_resume(struct device *dev)
1785		-{
1786		- struct net_device *ndev = dev_get_drvdata(dev);
1787		- struct m_can_priv *priv = netdev_priv(ndev);
1788		- int err;
1789		-
1790		- err = clk_prepare_enable(priv->hclk);
1791		- if (err)
1792		- return err;
1793		-
1794		- err = clk_prepare_enable(priv->cclk);
1795		- if (err)
1796		- clk_disable_unprepare(priv->hclk);
1797		-
1798		- return err;
1799		-}
1800		-
1801		-static const struct dev_pm_ops m_can_pmops = {
1802		- SET_RUNTIME_PM_OPS(m_can_runtime_suspend,
1803		- m_can_runtime_resume, NULL)
1804		- SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
1805		-};
1806		-
1807		-static const struct of_device_id m_can_of_table[] = {
1808		- { .compatible = "bosch,m_can", .data = NULL },
1809		- { /* sentinel */ },
1810		-};
1811		-MODULE_DEVICE_TABLE(of, m_can_of_table);
1812		-
1813		-static struct platform_driver m_can_plat_driver = {
1814		- .driver = {
1815		- .name = KBUILD_MODNAME,
1816		- .of_match_table = m_can_of_table,
1817		- .pm = &m_can_pmops,
1818		- },
1819		- .probe = m_can_plat_probe,
1820		- .remove = m_can_plat_remove,
1821		-};
1822		-
1823		-module_platform_driver(m_can_plat_driver);
	1915	+EXPORT_SYMBOL_GPL(m_can_class_unregister);
1824	1916
1825	1917	MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
	1918	+MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
1826	1919	MODULE_LICENSE("GPL v2");
1827	1920	MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");