disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/media/platform/rockchip/isp/rkisp.c
..
..
@@ -87,12 +87,6 @@
87
87
 
88
88
 static void rkisp_config_cmsk(struct rkisp_device *dev);
89
89
 
90
-struct backup_reg {
91
-	const u32 base;
92
-	const u32 shd;
93
-	u32 val;
94
-};
95
-
96
90
 static inline struct rkisp_device *sd_to_isp_dev(struct v4l2_subdev *sd)
97
91
 {
98
92
 	return container_of(sd->v4l2_dev, struct rkisp_device, v4l2_dev);
..
..
@@ -213,17 +207,16 @@
213
207
 		max_h = CIF_ISP_INPUT_H_MAX_V21;
214
208
 		break;
215
209
 	case ISP_V30:
216
-		if (dev->hw_dev->is_unite) {
217
-			max_w = CIF_ISP_INPUT_W_MAX_V30_UNITE;
218
-			max_h = CIF_ISP_INPUT_H_MAX_V30_UNITE;
219
-		} else {
220
-			max_w = CIF_ISP_INPUT_W_MAX_V30;
221
-			max_h = CIF_ISP_INPUT_H_MAX_V30;
222
-		}
210
+		max_w = dev->hw_dev->unite ?
211
+			CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
212
+		max_h = dev->hw_dev->unite ?
213
+			CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
223
214
 		break;
224
215
 	case ISP_V32:
225
-		max_w = CIF_ISP_INPUT_W_MAX_V32;
226
-		max_h = CIF_ISP_INPUT_H_MAX_V32;
216
+		max_w = dev->hw_dev->unite ?
217
+			CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
218
+		max_h = dev->hw_dev->unite ?
219
+			CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
227
220
 		break;
228
221
 	case ISP_V32_L:
229
222
 		max_w = CIF_ISP_INPUT_W_MAX_V32_L;
..
..
@@ -518,7 +511,9 @@
518
511
 	do_div(data_rate, 1000 * 1000);
519
512
 	/* increase margin: 25% * num */
520
513
 	data_rate += (data_rate >> 2) * num;
521
-
514
+	/* one frame two-run, data double */
515
+	if (hw->is_multi_overflow && num > 1)
516
+		data_rate *= 2;
522
517
 	/* compare with isp clock adjustment table */
523
518
 	for (i = 0; i < hw->num_clk_rate_tbl; i++)
524
519
 		if (data_rate <= hw->clk_rate_tbl[i].clk_rate)
..
..
@@ -528,7 +523,7 @@
528
523
 
529
524
 	/* set isp clock rate */
530
525
 	rkisp_set_clk_rate(hw->clks[0], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
531
-	if (hw->is_unite)
526
+	if (hw->unite == ISP_UNITE_TWO)
532
527
 		rkisp_set_clk_rate(hw->clks[5], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
533
528
 	/* aclk equal to core clk */
534
529
 	if (dev->isp_ver == ISP_V32)
..
..
@@ -541,48 +536,39 @@
541
536
 	struct rkisp_hw_dev *hw = dev->hw_dev;
542
537
 
543
538
 	if (on) {
544
-		/* enable bay3d and mi */
539
+		/* enable mi */
545
540
 		rkisp_update_regs(dev, ISP3X_MI_WR_CTRL, ISP3X_MI_WR_CTRL);
546
541
 		rkisp_update_regs(dev, ISP3X_ISP_CTRL1, ISP3X_ISP_CTRL1);
547
-		if (dev->isp_ver == ISP_V21) {
548
-			rkisp_update_regs(dev, ISP21_BAY3D_CTRL, ISP21_BAY3D_CTRL);
549
-		} else if (dev->isp_ver == ISP_V30) {
542
+		if (dev->isp_ver == ISP_V30) {
550
543
 			rkisp_update_regs(dev, ISP3X_MPFBC_CTRL, ISP3X_MPFBC_CTRL);
551
544
 			rkisp_update_regs(dev, ISP3X_MI_BP_WR_CTRL, ISP3X_MI_BP_WR_CTRL);
552
-			rkisp_update_regs(dev, ISP3X_BAY3D_CTRL, ISP3X_BAY3D_CTRL);
553
545
 			rkisp_update_regs(dev, ISP3X_SWS_CFG, ISP3X_SWS_CFG);
554
546
 		} else if (dev->isp_ver == ISP_V32) {
555
547
 			rkisp_update_regs(dev, ISP3X_MI_BP_WR_CTRL, ISP3X_MI_BP_WR_CTRL);
556
548
 			rkisp_update_regs(dev, ISP32_MI_BPDS_WR_CTRL, ISP32_MI_BPDS_WR_CTRL);
557
549
 			rkisp_update_regs(dev, ISP32_MI_MPDS_WR_CTRL, ISP32_MI_MPDS_WR_CTRL);
558
-			rkisp_update_regs(dev, ISP3X_BAY3D_CTRL, ISP3X_BAY3D_CTRL);
559
550
 		}
560
551
 	} else {
561
-		/* disabled bay3d and mi. rv1106 sdmmc workaround, 3a_wr no close */
552
+		/* disabled mi. rv1106 sdmmc workaround, 3a_wr no close */
562
553
 		writel(CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN,
563
554
 		       hw->base_addr + ISP3X_MI_WR_CTRL);
564
-		if (dev->isp_ver == ISP_V21) {
565
-			writel(0, hw->base_addr + ISP21_BAY3D_CTRL);
566
-		} else if (dev->isp_ver == ISP_V30) {
555
+		if (dev->isp_ver == ISP_V30) {
567
556
 			writel(0, hw->base_addr + ISP3X_MPFBC_CTRL);
568
557
 			writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL);
569
-			writel(0, hw->base_addr + ISP3X_BAY3D_CTRL);
570
558
 			writel(0xc, hw->base_addr + ISP3X_SWS_CFG);
571
-			if (hw->is_unite) {
559
+			if (hw->unite == ISP_UNITE_TWO) {
572
560
 				writel(0, hw->base_next_addr + ISP3X_MI_WR_CTRL);
573
561
 				writel(0, hw->base_next_addr + ISP3X_MPFBC_CTRL);
574
562
 				writel(0, hw->base_next_addr + ISP3X_MI_BP_WR_CTRL);
575
-				writel(0, hw->base_next_addr + ISP3X_BAY3D_CTRL);
576
563
 				writel(0xc, hw->base_next_addr + ISP3X_SWS_CFG);
577
564
 			}
578
565
 		} else if (dev->isp_ver == ISP_V32) {
579
566
 			writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL);
580
567
 			writel(0, hw->base_addr + ISP32_MI_BPDS_WR_CTRL);
581
568
 			writel(0, hw->base_addr + ISP32_MI_MPDS_WR_CTRL);
582
-			writel(0, hw->base_addr + ISP3X_BAY3D_CTRL);
583
569
 		}
584
570
 	}
585
-	rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite);
571
+	rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
586
572
 }
587
573
 
588
574
 /*
..
..
@@ -602,7 +588,8 @@
602
588
 	hw->cur_dev_id = dev->dev_id;
603
589
 	rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true);
604
590
 
605
-	if (hw->is_multi_overflow && is_try)
591
+	/* isp process the same frame */
592
+	if (is_try)
606
593
 		goto run_next;
607
594
 
608
595
 	val = 0;
..
..
@@ -632,13 +619,12 @@
632
619
 	}
633
620
 
634
621
 	if (rd_mode != dev->rd_mode) {
635
-		rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK,
636
-				     val, false, hw->is_unite);
622
+		rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK, val, false);
637
623
 		dev->skip_frame = 2;
638
624
 		is_upd = true;
639
625
 	}
640
626
 
641
-	if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL && !is_try) {
627
+	if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL) {
642
628
 		if (dev->rd_mode != rd_mode && dev->br_dev.en) {
643
629
 			tmp = dev->isp_sdev.in_crop.height;
644
630
 			val = rkisp_read(dev, CIF_DUAL_CROP_CTRL, false);
..
..
@@ -659,12 +645,15 @@
659
645
 	}
660
646
 	dev->rd_mode = rd_mode;
661
647
 
662
-	rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt,
663
-			       dev->isp_sdev.quantization);
664
-	rkisp_params_cfg(params_vdev, cur_frame_id);
665
-	rkisp_config_cmsk(dev);
666
-	rkisp_stream_frame_start(dev, 0);
667
-	if (!hw->is_single && !is_try) {
648
+	if (hw->unite != ISP_UNITE_ONE || dev->unite_index == ISP_UNITE_LEFT) {
649
+		rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt,
650
+				       dev->isp_sdev.quantization);
651
+		rkisp_params_cfg(params_vdev, cur_frame_id);
652
+		rkisp_config_cmsk(dev);
653
+		rkisp_stream_frame_start(dev, 0);
654
+	}
655
+
656
+	if (!hw->is_single) {
668
657
 		/* multi sensor need to reset isp resize mode if scale up */
669
658
 		val = 0;
670
659
 		if (rkisp_read(dev, ISP3X_MAIN_RESIZE_CTRL, true) & 0xf0)
..
..
@@ -700,7 +689,7 @@
700
689
 		} else {
701
690
 			if (dev->isp_ver == ISP_V32_L)
702
691
 				rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
703
-			rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite);
692
+			rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
704
693
 		}
705
694
 		/* sensor mode & index */
706
695
 		if (dev->isp_ver >= ISP_V21) {
..
..
@@ -711,7 +700,7 @@
711
700
 			else
712
701
 				val |= ISP21_SENSOR_MODE(dev->multi_mode);
713
702
 			writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
714
-			if (hw->is_unite)
703
+			if (hw->unite == ISP_UNITE_TWO)
715
704
 				writel(val, hw->base_next_addr + ISP_ACQ_H_OFFS);
716
705
 			v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
717
706
 				 "sensor mode:%d index:%d | 0x%x\n",
..
..
@@ -731,36 +720,98 @@
731
720
 	else
732
721
 		dev->rdbk_cnt_x1++;
733
722
 	dev->rdbk_cnt++;
734
-
735
-	rkisp_params_cfgsram(params_vdev);
736
-	params_vdev->rdbk_times = dma2frm + 1;
723
+	if (dev->isp_ver == ISP_V20)
724
+		params_vdev->rdbk_times = dma2frm + 1;
737
725
 
738
726
 run_next:
739
-	if (hw->is_multi_overflow && !dev->is_first_double) {
740
-		stats_vdev->rdbk_drop = false;
741
-		if (dev->sw_rd_cnt) {
742
-			rkisp_multi_overflow_hdl(dev, false);
743
-			params_vdev->rdbk_times += dev->sw_rd_cnt;
744
-			stats_vdev->rdbk_drop = true;
745
-			is_upd = true;
746
-		} else if (is_try) {
727
+	rkisp_params_cfgsram(params_vdev, true);
728
+	stats_vdev->rdbk_drop = false;
729
+	if (dev->is_frame_double) {
730
+		is_upd = true;
731
+		if (is_try) {
732
+			/* the frame second running to on mi */
747
733
 			rkisp_multi_overflow_hdl(dev, true);
748
-			is_upd = true;
734
+			rkisp_update_regs(dev, ISP_LDCH_BASE, ISP_LDCH_BASE);
735
+
736
+			val = ISP3X_YNR_FST_FRAME | ISP3X_DHAZ_FST_FRAME | ISP3X_CNR_FST_FRAME;
737
+			if (dev->isp_ver == ISP_V32)
738
+				val |= ISP32_SHP_FST_FRAME;
739
+			else
740
+				val |= ISP3X_CNR_FST_FRAME;
741
+			rkisp_unite_clear_bits(dev, ISP3X_ISP_CTRL1, val, false);
742
+			val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN);
743
+			writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN);
744
+			if (hw->unite == ISP_UNITE_TWO)
745
+				writel(val, hw->base_next_addr + ISP3X_DRC_IIRWG_GAIN);
746
+			val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO);
747
+			writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO);
748
+			if (hw->unite == ISP_UNITE_TWO)
749
+				writel(val, hw->base_next_addr + ISP3X_DRC_EXPLRATIO);
750
+			val = rkisp_read_reg_cache(dev, ISP3X_YNR_GLOBAL_CTRL);
751
+			writel(val, hw->base_addr + ISP3X_YNR_GLOBAL_CTRL);
752
+			if (hw->unite == ISP_UNITE_TWO)
753
+				writel(val, hw->base_next_addr + ISP3X_YNR_GLOBAL_CTRL);
754
+			if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30) {
755
+				val = rkisp_read_reg_cache(dev, ISP3X_CNR_CTRL);
756
+				writel(val, hw->base_addr + ISP3X_CNR_CTRL);
757
+				if (hw->unite == ISP_UNITE_TWO)
758
+					writel(val, hw->base_next_addr + ISP3X_CNR_CTRL);
759
+			}
760
+		} else {
761
+			/* the frame first running to off mi to save bandwidth */
762
+			rkisp_multi_overflow_hdl(dev, false);
763
+
764
+			/* FST_FRAME no to read sram thumb */
765
+			val = ISP3X_YNR_FST_FRAME | ISP3X_DHAZ_FST_FRAME;
766
+			if (dev->isp_ver == ISP_V32)
767
+				val |= ISP32_SHP_FST_FRAME;
768
+			else
769
+				val |= ISP3X_CNR_FST_FRAME;
770
+			rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL1, 0, val, false);
771
+			/* ADRC low iir thumb weight for first sensor switch */
772
+			val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN);
773
+			val &= ~ISP3X_DRC_IIR_WEIGHT_MASK;
774
+			writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN);
775
+			if (hw->unite == ISP_UNITE_TWO)
776
+				writel(val, hw->base_next_addr + ISP3X_DRC_IIRWG_GAIN);
777
+			/* ADRC iir5x5 and cur3x3 weight */
778
+			val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO);
779
+			val &= ~ISP3X_DRC_WEIPRE_FRAME_MASK;
780
+			writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO);
781
+			if (hw->unite == ISP_UNITE_TWO)
782
+				writel(val, hw->base_next_addr + ISP3X_DRC_EXPLRATIO);
783
+			/* YNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */
784
+			val = rkisp_read_reg_cache(dev, ISP3X_YNR_GLOBAL_CTRL);
785
+			val |= ISP3X_YNR_THUMB_MIX_CUR_EN;
786
+			writel(val, hw->base_addr + ISP3X_YNR_GLOBAL_CTRL);
787
+			if (hw->unite == ISP_UNITE_TWO)
788
+				writel(val, hw->base_next_addr + ISP3X_YNR_GLOBAL_CTRL);
789
+			if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30) {
790
+				/* CNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */
791
+				val = rkisp_read_reg_cache(dev, ISP3X_CNR_CTRL);
792
+				val |= ISP3X_CNR_THUMB_MIX_CUR_EN;
793
+				writel(val, hw->base_addr + ISP3X_CNR_CTRL);
794
+				if (hw->unite == ISP_UNITE_TWO)
795
+					writel(val, hw->base_next_addr + ISP3X_CNR_CTRL);
796
+			}
797
+			stats_vdev->rdbk_drop = true;
749
798
 		}
750
799
 	}
751
800
 
752
-	/* read 3d lut at frame end */
801
+	/* disable isp force update to read 3dlut
802
+	 * 3dlut auto update at frame end for single sensor
803
+	 */
753
804
 	if (hw->is_single && is_upd &&
754
805
 	    rkisp_read_reg_cache(dev, ISP_3DLUT_UPDATE) & 0x1) {
755
-		rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true, hw->is_unite);
806
+		rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true);
756
807
 		is_3dlut_upd = true;
757
808
 	}
758
809
 	if (is_upd) {
759
810
 		val = rkisp_read(dev, ISP_CTRL, false);
760
811
 		val |= CIF_ISP_CTRL_ISP_CFG_UPD;
761
-		rkisp_unite_write(dev, ISP_CTRL, val, true, hw->is_unite);
812
+		rkisp_unite_write(dev, ISP_CTRL, val, true);
762
813
 		/* bayer pat after ISP_CFG_UPD for multi sensor to read lsc r/g/b table */
763
-		rkisp_update_regs(dev, ISP_ACQ_PROP, ISP_ACQ_PROP);
814
+		rkisp_update_regs(dev, ISP3X_ISP_CTRL1, ISP3X_ISP_CTRL1);
764
815
 		/* fix ldch multi sensor case:
765
816
 		 * ldch will pre-read data when en and isp force upd or frame end,
766
817
 		 * udelay for ldch pre-read data.
..
..
@@ -771,12 +822,12 @@
771
822
 			udelay(50);
772
823
 			val &= ~(BIT(0) | BIT(31));
773
824
 			writel(val, hw->base_addr + ISP_LDCH_BASE);
774
-			if (hw->is_unite)
825
+			if (hw->unite == ISP_UNITE_TWO)
775
826
 				writel(val, hw->base_next_addr + ISP_LDCH_BASE);
776
827
 		}
777
828
 	}
778
829
 	if (is_3dlut_upd)
779
-		rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true, hw->is_unite);
830
+		rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true);
780
831
 
781
832
 	/* if output stream enable, wait it end */
782
833
 	val = rkisp_read(dev, CIF_MI_CTRL_SHD, true);
..
..
@@ -807,11 +858,13 @@
807
858
 	val &= ~SW_IBUF_OP_MODE(0xf);
808
859
 	tmp = SW_IBUF_OP_MODE(dev->rd_mode);
809
860
 	val |= tmp | SW_CSI2RX_EN | SW_DMA_2FRM_MODE(dma2frm);
861
+	if (dev->isp_ver > ISP_V20)
862
+		dma2frm = dev->sw_rd_cnt;
810
863
 	v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
811
-		 "readback frame:%d time:%d 0x%x\n",
812
-		 cur_frame_id, dma2frm + 1, val);
864
+		 "readback frame:%d time:%d 0x%x try:%d\n",
865
+		 cur_frame_id, dma2frm + 1, val, is_try);
813
866
 	if (!hw->is_shutdown)
814
-		rkisp_unite_write(dev, CSI2RX_CTRL0, val, true, hw->is_unite);
867
+		rkisp_unite_write(dev, CSI2RX_CTRL0, val, true);
815
868
 }
816
869
 
817
870
 static void rkisp_fast_switch_rx_buf(struct rkisp_device *dev, bool is_current)
..
..
@@ -819,6 +872,9 @@
819
872
 	struct rkisp_stream *stream;
820
873
 	struct rkisp_buffer *buf;
821
874
 	u32 i, val;
875
+
876
+	if (!dev->is_rtt_first)
877
+		return;
822
878
 
823
879
 	for (i = RKISP_STREAM_RAWRD0; i < RKISP_MAX_DMARX_STREAM; i++) {
824
880
 		stream = &dev->dmarx_dev.stream[i];
..
..
@@ -865,6 +921,12 @@
865
921
 			isp = dev;
866
922
 			is_try = true;
867
923
 			times = 0;
924
+			if (hw->unite == ISP_UNITE_ONE) {
925
+				if (dev->sw_rd_cnt < 2)
926
+					isp->unite_index = ISP_UNITE_RIGHT;
927
+				if (!hw->is_multi_overflow || (dev->sw_rd_cnt & 0x1))
928
+					is_try = false;
929
+			}
868
930
 			goto end;
869
931
 		}
870
932
 		hw->is_idle = true;
..
..
@@ -878,11 +940,16 @@
878
940
 		goto end;
879
941
 	if (!IS_HDR_RDBK(dev->rd_mode))
880
942
 		goto end;
943
+	if (dev->is_suspend) {
944
+		if (dev->suspend_sync)
945
+			complete(&dev->pm_cmpl);
946
+		goto end;
947
+	}
881
948
 
882
949
 	for (i = 0; i < hw->dev_num; i++) {
883
950
 		isp = hw->isp[i];
884
951
 		if (!isp ||
885
-		    (isp && !(isp->isp_state & ISP_START)))
952
+		    (isp && (!(isp->isp_state & ISP_START) || isp->is_suspend)))
886
953
 			continue;
887
954
 		rkisp_rdbk_trigger_event(isp, T_CMD_LEN, &len[i]);
888
955
 		if (max < len[i]) {
..
..
@@ -892,7 +959,7 @@
892
959
 	}
893
960
 
894
961
 	/* wait 2 frame to start isp for fast */
895
-	if (dev->is_pre_on && max == 1 && !atomic_read(&dev->isp_sdev.frm_sync_seq))
962
+	if (dev->is_rtt_first && max == 1 && !atomic_read(&dev->isp_sdev.frm_sync_seq))
896
963
 		goto end;
897
964
 
898
965
 	if (max) {
..
..
@@ -914,17 +981,42 @@
914
981
 		times = t.times;
915
982
 		hw->cur_dev_id = id;
916
983
 		hw->is_idle = false;
984
+		/* this frame will read count by isp */
917
985
 		isp->sw_rd_cnt = 0;
918
-		if (hw->is_multi_overflow && (hw->pre_dev_id != id)) {
986
+		/* frame double for multi camera resolution out of hardware limit
987
+		 * first for HW save this camera information, and second to output image
988
+		 */
989
+		isp->is_frame_double = false;
990
+		if (hw->is_multi_overflow &&
991
+		    (hw->unite == ISP_UNITE_ONE ||
992
+		     (hw->pre_dev_id != -1 && hw->pre_dev_id != id))) {
993
+			isp->is_frame_double = true;
919
994
 			isp->sw_rd_cnt = 1;
920
995
 			times = 0;
921
996
 		}
922
-		if (isp->is_pre_on && t.frame_id == 0) {
997
+		/* resolution out of hardware limit
998
+		 * frame is vertically divided into left and right
999
+		 */
1000
+		isp->unite_index = ISP_UNITE_LEFT;
1001
+		if (hw->unite == ISP_UNITE_ONE) {
1002
+			isp->sw_rd_cnt *= 2;
1003
+			isp->sw_rd_cnt += 1;
1004
+		}
1005
+		/* first frame handle twice for thunderboot
1006
+		 * first output stats to AIQ and wait new params to run second
1007
+		 */
1008
+		if (isp->is_rtt_first && t.frame_id == 0) {
923
1009
 			isp->is_first_double = true;
924
1010
 			isp->skip_frame = 1;
925
-			isp->sw_rd_cnt = 0;
1011
+			if (hw->unite != ISP_UNITE_ONE) {
1012
+				isp->sw_rd_cnt = 0;
1013
+				isp->is_frame_double = false;
1014
+			}
926
1015
 			rkisp_fast_switch_rx_buf(isp, false);
1016
+		} else {
1017
+			isp->is_rtt_first = false;
927
1018
 		}
1019
+		isp->params_vdev.rdbk_times = isp->sw_rd_cnt + 1;
928
1020
 	}
929
1021
 end:
930
1022
 	spin_unlock_irqrestore(&hw->rdbk_lock, lock_flags);
..
..
@@ -982,12 +1074,6 @@
982
1074
 {
983
1075
 	u32 val = 0;
984
1076
 
985
-	if (dev->hw_dev->is_multi_overflow &&
986
-	    dev->sw_rd_cnt &&
987
-	    irq & ISP_FRAME_END &&
988
-	    !dev->is_first_double)
989
-		goto end;
990
-
991
1077
 	dev->irq_ends |= (irq & dev->irq_ends_mask);
992
1078
 	v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
993
1079
 		 "%s irq:0x%x ends:0x%x mask:0x%x\n",
..
..
@@ -1002,8 +1088,12 @@
1002
1088
 	    !IS_HDR_RDBK(dev->rd_mode))
1003
1089
 		return;
1004
1090
 
1091
+	if (dev->sw_rd_cnt)
1092
+		goto end;
1093
+
1005
1094
 	if (dev->is_first_double) {
1006
1095
 		rkisp_fast_switch_rx_buf(dev, true);
1096
+		dev->is_rtt_first = false;
1007
1097
 		dev->skip_frame = 0;
1008
1098
 		dev->irq_ends = 0;
1009
1099
 		return;
..
..
@@ -1068,26 +1158,25 @@
1068
1158
 {
1069
1159
 	struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop;
1070
1160
 	u32 width = out_crop->width, mult = 1;
1071
-	bool is_unite = dev->hw_dev->is_unite;
1161
+	u32 unite = dev->hw_dev->unite;
1072
1162
 
1073
1163
 	/* isp2.0 no ism */
1074
1164
 	if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 ||
1075
1165
 	    dev->isp_ver == ISP_V32_L)
1076
1166
 		return;
1077
1167
 
1078
-	if (is_unite)
1168
+	if (unite)
1079
1169
 		width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1080
-	rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false, is_unite);
1081
-	rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false, is_unite);
1082
-	rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false, is_unite);
1083
-	rkisp_unite_write(dev, CIF_ISP_IS_DISPLACE, 0, false, is_unite);
1084
-	rkisp_unite_write(dev, CIF_ISP_IS_H_OFFS, out_crop->left, false, is_unite);
1085
-	rkisp_unite_write(dev, CIF_ISP_IS_V_OFFS, out_crop->top, false, is_unite);
1086
-	rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false, is_unite);
1170
+	rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false);
1171
+	rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false);
1172
+	rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false);
1173
+	rkisp_unite_write(dev, CIF_ISP_IS_DISPLACE, 0, false);
1174
+	rkisp_unite_write(dev, CIF_ISP_IS_H_OFFS, out_crop->left, false);
1175
+	rkisp_unite_write(dev, CIF_ISP_IS_V_OFFS, out_crop->top, false);
1176
+	rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false);
1087
1177
 	if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced)
1088
1178
 		mult = 2;
1089
-	rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult,
1090
-			  false, is_unite);
1179
+	rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult, false);
1091
1180
 
1092
1181
 	if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32)
1093
1182
 		return;
..
..
@@ -1096,86 +1185,19 @@
1096
1185
 	rkisp_write(dev, CIF_ISP_IS_CTRL, 1, false);
1097
1186
 }
1098
1187
 
1099
-static int rkisp_reset_handle_v2x(struct rkisp_device *dev)
1188
+static int rkisp_reset_handle(struct rkisp_device *dev)
1100
1189
 {
1101
-	void __iomem *base = dev->base_addr;
1102
-	void *reg_buf = NULL;
1103
-	u32 *reg, *reg1, i;
1104
-	struct backup_reg backup[] = {
1105
-		{
1106
-			.base = MI_MP_WR_Y_BASE,
1107
-			.shd = MI_MP_WR_Y_BASE_SHD,
1108
-		}, {
1109
-			.base = MI_MP_WR_CB_BASE,
1110
-			.shd = MI_MP_WR_CB_BASE_SHD,
1111
-		}, {
1112
-			.base = MI_MP_WR_CR_BASE,
1113
-			.shd = MI_MP_WR_CR_BASE_SHD,
1114
-		}, {
1115
-			.base = MI_SP_WR_Y_BASE,
1116
-			.shd = MI_SP_WR_Y_BASE_SHD,
1117
-		}, {
1118
-			.base = MI_SP_WR_CB_BASE,
1119
-			.shd = MI_SP_WR_CB_BASE_AD_SHD,
1120
-		}, {
1121
-			.base = MI_SP_WR_CR_BASE,
1122
-			.shd = MI_SP_WR_CR_BASE_AD_SHD,
1123
-		}, {
1124
-			.base = MI_RAW0_WR_BASE,
1125
-			.shd = MI_RAW0_WR_BASE_SHD,
1126
-		}, {
1127
-			.base = MI_RAW1_WR_BASE,
1128
-			.shd = MI_RAW1_WR_BASE_SHD,
1129
-		}, {
1130
-			.base = MI_RAW2_WR_BASE,
1131
-			.shd = MI_RAW2_WR_BASE_SHD,
1132
-		}, {
1133
-			.base = MI_RAW3_WR_BASE,
1134
-			.shd = MI_RAW3_WR_BASE_SHD,
1135
-		}, {
1136
-			.base = MI_RAW0_RD_BASE,
1137
-			.shd = MI_RAW0_RD_BASE_SHD,
1138
-		}, {
1139
-			.base = MI_RAW1_RD_BASE,
1140
-			.shd = MI_RAW1_RD_BASE_SHD,
1141
-		}, {
1142
-			.base = MI_RAW2_RD_BASE,
1143
-			.shd = MI_RAW2_RD_BASE_SHD,
1144
-		}, {
1145
-			.base = MI_GAIN_WR_BASE,
1146
-			.shd = MI_GAIN_WR_BASE_SHD,
1147
-		}
1148
-	};
1149
-
1150
-	reg_buf = kzalloc(RKISP_ISP_SW_REG_SIZE, GFP_KERNEL);
1151
-	if (!reg_buf)
1152
-		return -ENOMEM;
1190
+	u32 val;
1153
1191
 
1154
1192
 	dev_info(dev->dev, "%s enter\n", __func__);
1193
+	rkisp_hw_reg_save(dev->hw_dev);
1155
1194
 
1156
-	memcpy_fromio(reg_buf, base, RKISP_ISP_SW_REG_SIZE);
1157
1195
 	rkisp_soft_reset(dev->hw_dev, true);
1158
1196
 
1159
-	/* process special reg */
1160
-	reg = reg_buf + ISP_CTRL;
1161
-	*reg &= ~(CIF_ISP_CTRL_ISP_ENABLE |
1162
-		  CIF_ISP_CTRL_ISP_INFORM_ENABLE |
1163
-		  CIF_ISP_CTRL_ISP_CFG_UPD);
1164
-	reg = reg_buf + MI_WR_INIT;
1165
-	*reg = 0;
1166
-	reg = reg_buf + CSI2RX_CTRL0;
1167
-	*reg &= ~SW_CSI2RX_EN;
1168
-	/* skip mmu range */
1169
-	memcpy_toio(base, reg_buf, ISP21_MI_BAY3D_RD_BASE_SHD);
1170
-	memcpy_toio(base + CSI2RX_CTRL0, reg_buf + CSI2RX_CTRL0,
1171
-		    RKISP_ISP_SW_REG_SIZE - CSI2RX_CTRL0);
1172
-	/* config shd_reg to base_reg */
1173
-	for (i = 0; i < ARRAY_SIZE(backup); i++) {
1174
-		reg = reg_buf + backup[i].base;
1175
-		reg1 = reg_buf + backup[i].shd;
1176
-		backup[i].val = *reg;
1177
-		writel(*reg1, base + backup[i].base);
1178
-	}
1197
+	rkisp_hw_reg_restore(dev->hw_dev);
1198
+
1199
+	val = CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR;
1200
+	rkisp_unite_set_bits(dev, CIF_ISP_IMSC, 0, val, true);
1179
1201
 
1180
1202
 	/* clear state */
1181
1203
 	dev->isp_err_cnt = 0;
..
..
@@ -1183,40 +1205,12 @@
1183
1205
 	rkisp_set_state(&dev->isp_state, ISP_FRAME_END);
1184
1206
 	dev->hw_dev->monitor.state = ISP_FRAME_END;
1185
1207
 
1186
-	/* update module */
1187
-	reg = reg_buf + DUAL_CROP_CTRL;
1188
-	if (*reg & 0xf)
1189
-		writel(*reg | CIF_DUAL_CROP_CFG_UPD, base + DUAL_CROP_CTRL);
1190
-	reg = reg_buf + SELF_RESIZE_CTRL;
1191
-	if (*reg & 0xf)
1192
-		writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + SELF_RESIZE_CTRL);
1193
-	reg = reg_buf + MAIN_RESIZE_CTRL;
1194
-	if (*reg & 0xf)
1195
-		writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + MAIN_RESIZE_CTRL);
1196
-
1197
-	/* update mi and isp, base_reg will update to shd_reg */
1198
-	force_cfg_update(dev);
1199
-	reg = reg_buf + ISP_CTRL;
1200
-	*reg |= CIF_ISP_CTRL_ISP_ENABLE |
1201
-		CIF_ISP_CTRL_ISP_INFORM_ENABLE |
1202
-		CIF_ISP_CTRL_ISP_CFG_UPD;
1203
-	writel(*reg, base + ISP_CTRL);
1204
-	udelay(50);
1205
-	/* config base_reg */
1206
-	for (i = 0; i < ARRAY_SIZE(backup); i++)
1207
-		writel(backup[i].val, base + backup[i].base);
1208
-	/* mpfbc base_reg = shd_reg, write is base but read is shd */
1209
-	if (dev->isp_ver == ISP_V20)
1210
-		writel(rkisp_read_reg_cache(dev, ISP_MPFBC_HEAD_PTR),
1211
-		       base + ISP_MPFBC_HEAD_PTR);
1212
-	rkisp_set_bits(dev, CIF_ISP_IMSC, 0, CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR, true);
1213
1208
 	if (IS_HDR_RDBK(dev->hdr.op_mode)) {
1214
1209
 		if (!dev->hw_dev->is_idle)
1215
1210
 			rkisp_trigger_read_back(dev, 1, 0, true);
1216
1211
 		else
1217
1212
 			rkisp_rdbk_trigger_event(dev, T_CMD_QUEUE, NULL);
1218
1213
 	}
1219
-	kfree(reg_buf);
1220
1214
 	dev_info(dev->dev, "%s exit\n", __func__);
1221
1215
 	return 0;
1222
1216
 }
..
..
@@ -1230,11 +1224,6 @@
1230
1224
 	struct rkisp_pipeline *p;
1231
1225
 	int ret, i, j, timeout = 5, mipi_irq_cnt = 0;
1232
1226
 
1233
-	if (!monitor->reset_handle) {
1234
-		monitor->is_en = false;
1235
-		return;
1236
-	}
1237
-
1238
1227
 	dev_info(hw->dev, "%s enter\n", __func__);
1239
1228
 	while (!(monitor->state & ISP_STOP) && monitor->is_en) {
1240
1229
 		ret = wait_for_completion_timeout(&monitor->cmpl,
..
..
@@ -1242,8 +1231,11 @@
1242
1231
 		/* isp stop to exit
1243
1232
 		 * isp err to reset
1244
1233
 		 * mipi err wait isp idle, then reset
1234
+		 * online vicap if isp err, notify vicap reset, then vicap notify isp reset
1235
+		 * by ioctl RKISP_VICAP_CMD_SET_STREAM
1245
1236
 		 */
1246
1237
 		if (monitor->state & ISP_STOP ||
1238
+		    monitor->state & ISP_CIF_RESET ||
1247
1239
 		    (ret && !(monitor->state & ISP_ERROR)) ||
1248
1240
 		    (!ret &&
1249
1241
 		     monitor->state & ISP_FRAME_END &&
..
..
@@ -1292,10 +1284,22 @@
1292
1284
 
1293
1285
 		/* restart isp */
1294
1286
 		isp = hw->isp[hw->cur_dev_id];
1295
-		ret = monitor->reset_handle(isp);
1296
-		if (ret) {
1297
-			monitor->is_en = false;
1298
-			break;
1287
+		if (!IS_HDR_RDBK(isp->hdr.op_mode) && isp->isp_ver >= ISP_V30) {
1288
+			struct v4l2_subdev *remote = NULL;
1289
+			struct v4l2_subdev *isp_subdev = NULL;
1290
+
1291
+			isp_subdev = &(isp->isp_sdev.sd);
1292
+			remote = get_remote_sensor(isp_subdev);
1293
+			v4l2_subdev_call(remote, core, ioctl,
1294
+				RKISP_VICAP_CMD_SET_RESET, NULL);
1295
+			monitor->state |= ISP_CIF_RESET;
1296
+			continue;
1297
+		} else {
1298
+			ret = rkisp_reset_handle(isp);
1299
+			if (ret) {
1300
+				monitor->is_en = false;
1301
+				break;
1302
+			}
1299
1303
 		}
1300
1304
 
1301
1305
 		for (i = 0; i < hw->dev_num; i++) {
..
..
@@ -1329,9 +1333,6 @@
1329
1333
 	struct rkisp_monitor *monitor = &dev->hw_dev->monitor;
1330
1334
 
1331
1335
 	monitor->dev = dev->hw_dev;
1332
-	monitor->reset_handle = NULL;
1333
-	if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21)
1334
-		monitor->reset_handle = rkisp_reset_handle_v2x;
1335
1336
 
1336
1337
 	init_completion(&monitor->cmpl);
1337
1338
 	INIT_WORK(&monitor->work, rkisp_restart_monitor);
..
..
@@ -1389,20 +1390,18 @@
1389
1390
 
1390
1391
 	for (i = 0; i < 9; i++)
1391
1392
 		rkisp_unite_write(dev, CIF_ISP_CC_COEFF_0 + i * 4,
1392
-				  *(coeff + i), false, dev->hw_dev->is_unite);
1393
+				  *(coeff + i), false);
1393
1394
 
1394
1395
 	val = rkisp_read_reg_cache(dev, CIF_ISP_CTRL);
1395
1396
 
1396
1397
 	if (dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
1397
1398
 		rkisp_unite_write(dev, CIF_ISP_CTRL, val |
1398
1399
 				  CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
1399
-				  CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA,
1400
-				  false, dev->hw_dev->is_unite);
1400
+				  CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA, false);
1401
1401
 	else
1402
1402
 		rkisp_unite_write(dev, CIF_ISP_CTRL, val &
1403
1403
 				  ~(CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
1404
-				  CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA),
1405
-				  false, dev->hw_dev->is_unite);
1404
+				  CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA), false);
1406
1405
 }
1407
1406
 
1408
1407
 static void rkisp_config_cmsk_single(struct rkisp_device *dev,
..
..
@@ -1498,6 +1497,7 @@
1498
1497
 			left.win[0].win_en &= ~BIT(i);
1499
1498
 			left.win[1].win_en &= ~BIT(i);
1500
1499
 			left.win[2].win_en &= ~BIT(i);
1500
+			right.win[i].h_offs = h_offs - w + RKMOUDLE_UNITE_EXTEND_PIXEL;
1501
1501
 		} else {
1502
1502
 			/* cmsk window at dual isp */
1503
1503
 			left.win[i].h_size = ALIGN(w - h_offs, 8);
..
..
@@ -1601,7 +1601,7 @@
1601
1601
 	cfg = dev->cmsk_cfg;
1602
1602
 	spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
1603
1603
 
1604
-	if (!dev->hw_dev->is_unite)
1604
+	if (!dev->hw_dev->unite)
1605
1605
 		rkisp_config_cmsk_single(dev, &cfg);
1606
1606
 	else
1607
1607
 		rkisp_config_cmsk_dual(dev, &cfg);
..
..
@@ -1616,7 +1616,7 @@
1616
1616
 	struct ispsd_out_fmt *out_fmt;
1617
1617
 	struct v4l2_rect *in_crop;
1618
1618
 	struct rkisp_sensor_info *sensor;
1619
-	bool is_unite = dev->hw_dev->is_unite;
1619
+	bool is_unite = !!dev->hw_dev->unite;
1620
1620
 	u32 isp_ctrl = 0;
1621
1621
 	u32 irq_mask = 0;
1622
1622
 	u32 signal = 0;
..
..
@@ -1646,22 +1646,20 @@
1646
1646
 			    in_fmt->mbus_code == MEDIA_BUS_FMT_Y10_1X10 ||
1647
1647
 			    in_fmt->mbus_code == MEDIA_BUS_FMT_Y12_1X12) {
1648
1648
 				if (dev->isp_ver >= ISP_V20)
1649
-					rkisp_unite_write(dev, ISP_DEBAYER_CONTROL,
1650
-							  0, false, is_unite);
1649
+					rkisp_unite_write(dev, ISP_DEBAYER_CONTROL, 0, false);
1651
1650
 				else
1652
1651
 					rkisp_write(dev, CIF_ISP_DEMOSAIC,
1653
-						CIF_ISP_DEMOSAIC_BYPASS |
1654
-						CIF_ISP_DEMOSAIC_TH(0xc), false);
1652
+						    CIF_ISP_DEMOSAIC_BYPASS |
1653
+						    CIF_ISP_DEMOSAIC_TH(0xc), false);
1655
1654
 			} else {
1656
1655
 				if (dev->isp_ver >= ISP_V20)
1657
1656
 					rkisp_unite_write(dev, ISP_DEBAYER_CONTROL,
1658
1657
 							  SW_DEBAYER_EN |
1659
1658
 							  SW_DEBAYER_FILTER_G_EN |
1660
-							  SW_DEBAYER_FILTER_C_EN,
1661
-							  false, is_unite);
1659
+							  SW_DEBAYER_FILTER_C_EN, false);
1662
1660
 				else
1663
1661
 					rkisp_write(dev, CIF_ISP_DEMOSAIC,
1664
-						CIF_ISP_DEMOSAIC_TH(0xc), false);
1662
+						    CIF_ISP_DEMOSAIC_TH(0xc), false);
1665
1663
 			}
1666
1664
 
1667
1665
 			if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
..
..
@@ -1714,38 +1712,31 @@
1714
1712
 	if (rkisp_read_reg_cache(dev, CIF_ISP_CTRL) & ISP32_MIR_ENABLE)
1715
1713
 		isp_ctrl |= ISP32_MIR_ENABLE;
1716
1714
 
1717
-	rkisp_unite_write(dev, CIF_ISP_CTRL, isp_ctrl, false, is_unite);
1715
+	rkisp_unite_write(dev, CIF_ISP_CTRL, isp_ctrl, false);
1718
1716
 	acq_prop |= signal | in_fmt->yuv_seq |
1719
1717
 		CIF_ISP_ACQ_PROP_BAYER_PAT(in_fmt->bayer_pat) |
1720
1718
 		CIF_ISP_ACQ_PROP_FIELD_SEL_ALL;
1721
-	rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false, is_unite);
1722
-	rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true, is_unite);
1719
+	rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false);
1720
+	rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true);
1723
1721
 
1724
1722
 	if (is_unite)
1725
1723
 		width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1726
1724
 	/* Acquisition Size */
1727
-	rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left,
1728
-			  false, is_unite);
1729
-	rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top,
1730
-			  false, is_unite);
1731
-	rkisp_unite_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * width,
1732
-			  false, is_unite);
1725
+	rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left, false);
1726
+	rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top, false);
1727
+	rkisp_unite_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * width, false);
1733
1728
 
1734
1729
 	/* ISP Out Area differ with ACQ is only FIFO, so don't crop in this */
1735
-	rkisp_unite_write(dev, CIF_ISP_OUT_H_OFFS, 0, true, is_unite);
1736
-	rkisp_unite_write(dev, CIF_ISP_OUT_V_OFFS, 0, true, is_unite);
1737
-	rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false, is_unite);
1730
+	rkisp_unite_write(dev, CIF_ISP_OUT_H_OFFS, 0, true);
1731
+	rkisp_unite_write(dev, CIF_ISP_OUT_V_OFFS, 0, true);
1732
+	rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false);
1738
1733
 
1739
1734
 	if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) {
1740
-		rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2,
1741
-				  false, is_unite);
1742
-		rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2,
1743
-				  false, is_unite);
1735
+		rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2, false);
1736
+		rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2, false);
1744
1737
 	} else {
1745
-		rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line,
1746
-				  false, is_unite);
1747
-		rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line,
1748
-				  false, is_unite);
1738
+		rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line, false);
1739
+		rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line, false);
1749
1740
 	}
1750
1741
 
1751
1742
 	/* interrupt mask */
..
..
@@ -1754,7 +1745,7 @@
1754
1745
 		irq_mask |= ISP2X_LSC_LUT_ERR;
1755
1746
 	if (dev->is_pre_on)
1756
1747
 		irq_mask |= CIF_ISP_FRAME_IN;
1757
-	rkisp_unite_write(dev, CIF_ISP_IMSC, irq_mask, true, is_unite);
1748
+	rkisp_unite_write(dev, CIF_ISP_IMSC, irq_mask, true);
1758
1749
 
1759
1750
 	if ((dev->isp_ver == ISP_V20 ||
1760
1751
 	     dev->isp_ver == ISP_V21) &&
..
..
@@ -1909,8 +1900,7 @@
1909
1900
 	if (dev->isp_ver == ISP_V32)
1910
1901
 		dpcl |= BIT(0);
1911
1902
 
1912
-	rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true,
1913
-			     dev->hw_dev->is_unite);
1903
+	rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true);
1914
1904
 	return ret;
1915
1905
 }
1916
1906
 
..
..
@@ -2007,9 +1997,9 @@
2007
1997
 
2008
1998
 	v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2009
1999
 		 "%s refcnt:%d\n", __func__,
2010
-		 atomic_read(&dev->hw_dev->refcnt));
2000
+		 atomic_read(&hw->refcnt));
2011
2001
 
2012
-	if (atomic_read(&dev->hw_dev->refcnt) > 1)
2002
+	if (atomic_read(&hw->refcnt) > 1)
2013
2003
 		goto end;
2014
2004
 	/*
2015
2005
 	 * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
..
..
@@ -2065,7 +2055,7 @@
2065
2055
 
2066
2056
 	val = readl(base + CIF_ISP_CTRL);
2067
2057
 	writel(val | CIF_ISP_CTRL_ISP_CFG_UPD, base + CIF_ISP_CTRL);
2068
-	if (hw->is_unite)
2058
+	if (hw->unite == ISP_UNITE_TWO)
2069
2059
 		rkisp_next_write(dev, CIF_ISP_CTRL,
2070
2060
 				 val | CIF_ISP_CTRL_ISP_CFG_UPD, true);
2071
2061
 
..
..
@@ -2082,11 +2072,11 @@
2082
2072
 		safe_rate = hw->clk_rate_tbl[0].clk_rate * 1000000UL;
2083
2073
 		if (old_rate > safe_rate) {
2084
2074
 			rkisp_set_clk_rate(hw->clks[0], safe_rate);
2085
-			if (hw->is_unite)
2075
+			if (hw->unite == ISP_UNITE_TWO)
2086
2076
 				rkisp_set_clk_rate(hw->clks[5], safe_rate);
2087
2077
 			udelay(100);
2088
2078
 		}
2089
-		rkisp_soft_reset(dev->hw_dev, false);
2079
+		rkisp_soft_reset(hw, false);
2090
2080
 	}
2091
2081
 
2092
2082
 	if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
..
..
@@ -2097,18 +2087,20 @@
2097
2087
 		writel(0, base + CIF_ISP_CSI0_MASK3);
2098
2088
 	} else if (dev->isp_ver >= ISP_V20) {
2099
2089
 		writel(0, base + CSI2RX_CSI2_RESETN);
2100
-		if (hw->is_unite)
2090
+		if (hw->unite == ISP_UNITE_TWO)
2101
2091
 			rkisp_next_write(dev, CSI2RX_CSI2_RESETN, 0, true);
2102
2092
 	}
2103
2093
 
2104
2094
 	hw->is_dvfs = false;
2105
2095
 	hw->is_runing = false;
2106
-	dev->hw_dev->is_idle = true;
2107
-	dev->hw_dev->is_mi_update = false;
2096
+	hw->is_idle = true;
2097
+	hw->is_mi_update = false;
2098
+	hw->pre_dev_id = -1;
2108
2099
 end:
2109
2100
 	dev->irq_ends_mask = 0;
2110
2101
 	dev->hdr.op_mode = 0;
2111
2102
 	dev->sw_rd_cnt = 0;
2103
+	dev->stats_vdev.rdbk_drop = false;
2112
2104
 	rkisp_set_state(&dev->isp_state, ISP_STOP);
2113
2105
 
2114
2106
 	if (dev->isp_ver >= ISP_V20)
..
..
@@ -2154,12 +2146,9 @@
2154
2146
 			val = dev->isp_sdev.out_crop.height / 15;
2155
2147
 			val = dev->cap_dev.wait_line / val;
2156
2148
 			val = ISP3X_RAWAF_INELINE0(val) | ISP3X_RAWAF_INTLINE0_EN;
2157
-			rkisp_unite_write(dev, ISP3X_RAWAF_INT_LINE,
2158
-				val, false, dev->hw_dev->is_unite);
2159
-			rkisp_unite_set_bits(dev, ISP_ISP3A_IMSC, 0,
2160
-				ISP2X_3A_RAWAF, false, dev->hw_dev->is_unite);
2161
-			rkisp_unite_clear_bits(dev, CIF_ISP_IMSC,
2162
-				ISP2X_LSC_LUT_ERR, false, dev->hw_dev->is_unite);
2149
+			rkisp_unite_write(dev, ISP3X_RAWAF_INT_LINE, val, false);
2150
+			rkisp_unite_set_bits(dev, ISP_ISP3A_IMSC, 0, ISP2X_3A_RAWAF, false);
2151
+			rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, ISP2X_LSC_LUT_ERR, false);
2163
2152
 			dev->rawaf_irq_cnt = 0;
2164
2153
 		}
2165
2154
 	}
..
..
@@ -2187,12 +2176,11 @@
2187
2176
 		val |= NOC_HURRY_PRIORITY(2) | NOC_HURRY_W_MODE(2) | NOC_HURRY_R_MODE(1);
2188
2177
 	if (atomic_read(&dev->hw_dev->refcnt) > 1)
2189
2178
 		is_direct = false;
2190
-	rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct, dev->hw_dev->is_unite);
2179
+	rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct);
2191
2180
 	rkisp_clear_reg_cache_bits(dev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_CFG_UPD);
2192
2181
 
2193
2182
 	dev->isp_err_cnt = 0;
2194
2183
 	dev->isp_isr_cnt = 0;
2195
-	dev->isp_state = ISP_START | ISP_FRAME_END;
2196
2184
 	dev->irq_ends_mask |= ISP_FRAME_END;
2197
2185
 	dev->irq_ends = 0;
2198
2186
 
..
..
@@ -2668,14 +2656,16 @@
2668
2656
 				max_h = CIF_ISP_INPUT_H_MAX_V21;
2669
2657
 				break;
2670
2658
 			case ISP_V30:
2671
-				max_w = dev->hw_dev->is_unite ?
2659
+				max_w = dev->hw_dev->unite ?
2672
2660
 					CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
2673
-				max_h = dev->hw_dev->is_unite ?
2661
+				max_h = dev->hw_dev->unite ?
2674
2662
 					CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
2675
2663
 				break;
2676
2664
 			case ISP_V32:
2677
-				max_w = CIF_ISP_INPUT_W_MAX_V32;
2678
-				max_h = CIF_ISP_INPUT_H_MAX_V32;
2665
+				max_w = dev->hw_dev->unite ?
2666
+					CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
2667
+				max_h = dev->hw_dev->unite ?
2668
+					CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
2679
2669
 				break;
2680
2670
 			case ISP_V32_L:
2681
2671
 				max_w = CIF_ISP_INPUT_W_MAX_V32_L;
..
..
@@ -2865,6 +2855,7 @@
2865
2855
 {
2866
2856
 	struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
2867
2857
 	struct rkisp_hw_dev *hw_dev = isp_dev->hw_dev;
2858
+	int ret;
2868
2859
 
2869
2860
 	if (!on) {
2870
2861
 		if (IS_HDR_RDBK(isp_dev->rd_mode)) {
..
..
@@ -2877,10 +2868,13 @@
2877
2868
 					wake_up(&s->done);
2878
2869
 			}
2879
2870
 		}
2880
-		wait_event_timeout(isp_dev->sync_onoff,
2881
-				   isp_dev->isp_state & ISP_STOP ||
2882
-				   !IS_HDR_RDBK(isp_dev->rd_mode),
2883
-				   msecs_to_jiffies(50));
2871
+		ret = wait_event_timeout(isp_dev->sync_onoff,
2872
+					 isp_dev->isp_state & ISP_STOP ||
2873
+					 !IS_HDR_RDBK(isp_dev->rd_mode),
2874
+					 msecs_to_jiffies(500));
2875
+		if (!ret)
2876
+			v4l2_warn(&isp_dev->v4l2_dev, "%s wait timeout, mode:%d state:0x%x\n",
2877
+				  __func__, isp_dev->rd_mode, isp_dev->isp_state);
2884
2878
 		rkisp_isp_stop(isp_dev);
2885
2879
 		atomic_dec(&hw_dev->refcnt);
2886
2880
 		rkisp_params_stream_stop(&isp_dev->params_vdev);
..
..
@@ -2901,6 +2895,7 @@
2901
2895
 	rkisp_config_cif(isp_dev);
2902
2896
 	rkisp_isp_start(isp_dev);
2903
2897
 	rkisp_global_update_mi(isp_dev);
2898
+	isp_dev->isp_state = ISP_START | ISP_FRAME_END;
2904
2899
 	rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, NULL);
2905
2900
 	return 0;
2906
2901
 }
..
..
@@ -2936,7 +2931,7 @@
2936
2931
 	u32 val = pool->buf.buff_addr[RKISP_PLANE_Y];
2937
2932
 
2938
2933
 	rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
2939
-	if (dev->hw_dev->is_unite) {
2934
+	if (dev->hw_dev->unite == ISP_UNITE_TWO) {
2940
2935
 		u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
2941
2936
 
2942
2937
 		if (stream->memory)
..
..
@@ -3054,7 +3049,8 @@
3054
3049
 
3055
3050
 	pool->dbufs = dbufs;
3056
3051
 	v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
3057
-		 "%s type:0x%x dbufs[%d]:%p", __func__, dbufs->type, i, dbufs);
3052
+		 "%s type:0x%x first:%d dbufs[%d]:%p", __func__,
3053
+		 dbufs->type, dbufs->is_first, i, dbufs);
3058
3054
 
3059
3055
 	if (dbufs->is_resmem) {
3060
3056
 		dma = dbufs->dma;
..
..
@@ -3412,11 +3408,64 @@
3412
3408
 	if (dev->is_bigmode)
3413
3409
 		mode |= RKISP_ISP_BIGMODE;
3414
3410
 	info->mode = mode;
3415
-	if (dev->hw_dev->is_unite)
3411
+	if (dev->hw_dev->unite)
3416
3412
 		info->act_width = in_crop->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
3417
3413
 	else
3418
3414
 		info->act_width = in_crop->width;
3419
3415
 	info->act_height = in_crop->height;
3416
+	return 0;
3417
+}
3418
+
3419
+static int rkisp_set_work_mode_by_vicap(struct rkisp_device *isp_dev,
3420
+					struct rkisp_vicap_mode *vicap_mode)
3421
+{
3422
+	struct rkisp_hw_dev *hw = isp_dev->hw_dev;
3423
+	int rd_mode = isp_dev->rd_mode;
3424
+
3425
+	isp_dev->is_suspend_one_frame = false;
3426
+	if (vicap_mode->rdbk_mode == RKISP_VICAP_ONLINE) {
3427
+		if (!hw->is_single)
3428
+			return -EINVAL;
3429
+		/* switch to online mode for single sensor */
3430
+		switch (rd_mode) {
3431
+		case HDR_RDBK_FRAME3:
3432
+			isp_dev->rd_mode = HDR_LINEX3_DDR;
3433
+			break;
3434
+		case HDR_RDBK_FRAME2:
3435
+			isp_dev->rd_mode = HDR_LINEX2_DDR;
3436
+			break;
3437
+		default:
3438
+			isp_dev->rd_mode = HDR_NORMAL;
3439
+		}
3440
+	} else if (vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO ||
3441
+		   vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME) {
3442
+		/* switch to readback mode */
3443
+		switch (rd_mode) {
3444
+		case HDR_LINEX3_DDR:
3445
+			isp_dev->rd_mode = HDR_RDBK_FRAME3;
3446
+			break;
3447
+		case HDR_LINEX2_DDR:
3448
+			isp_dev->rd_mode = HDR_RDBK_FRAME2;
3449
+			break;
3450
+		default:
3451
+			isp_dev->rd_mode = HDR_RDBK_FRAME1;
3452
+		}
3453
+		if (vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME)
3454
+			isp_dev->is_suspend_one_frame = true;
3455
+	} else {
3456
+		return -EINVAL;
3457
+	}
3458
+	isp_dev->hdr.op_mode = isp_dev->rd_mode;
3459
+	if (rd_mode != isp_dev->rd_mode && hw->cur_dev_id == isp_dev->dev_id) {
3460
+		rkisp_unite_write(isp_dev, CSI2RX_CTRL0,
3461
+				  SW_IBUF_OP_MODE(isp_dev->rd_mode), true);
3462
+		if (IS_HDR_RDBK(isp_dev->rd_mode))
3463
+			rkisp_unite_set_bits(isp_dev, CTRL_SWS_CFG, 0,
3464
+					     SW_MPIP_DROP_FRM_DIS, true);
3465
+		else
3466
+			rkisp_unite_clear_bits(isp_dev, CTRL_SWS_CFG,
3467
+					       SW_MPIP_DROP_FRM_DIS, true);
3468
+	}
3420
3469
 	return 0;
3421
3470
 }
3422
3471
 
..
..
@@ -3445,7 +3494,7 @@
3445
3494
 		rkisp_get_info(isp_dev, arg);
3446
3495
 		break;
3447
3496
 	case RKISP_CMD_GET_TB_HEAD_V32:
3448
-		if (isp_dev->tb_head.complete != RKISP_TB_OK || !isp_dev->is_pre_on) {
3497
+		if (isp_dev->tb_head.complete != RKISP_TB_OK) {
3449
3498
 			ret = -EINVAL;
3450
3499
 			break;
3451
3500
 		}
..
..
@@ -3543,6 +3592,16 @@
3543
3592
 			isp_dev->hw_dev->is_multi_overflow = false;
3544
3593
 			rkisp_hw_enum_isp_size(isp_dev->hw_dev);
3545
3594
 		}
3595
+		break;
3596
+	case RKISP_VICAP_CMD_SET_STREAM:
3597
+		ret = rkisp_reset_handle(isp_dev);
3598
+		if (!ret) {
3599
+			if (isp_dev->hw_dev->monitor.state & ISP_CIF_RESET)
3600
+				isp_dev->hw_dev->monitor.state &= ~ISP_CIF_RESET;
3601
+		}
3602
+		break;
3603
+	case RKISP_VICAP_CMD_MODE:
3604
+		ret = rkisp_set_work_mode_by_vicap(isp_dev, arg);
3546
3605
 		break;
3547
3606
 	default:
3548
3607
 		ret = -ENOIOCTLCMD;
..
..
@@ -3646,6 +3705,9 @@
3646
3705
 	case RKISP_CMD_MULTI_DEV_FORCE_ENUM:
3647
3706
 		ret = rkisp_ioctl(sd, cmd, NULL);
3648
3707
 		break;
3708
+	case RKISP_VICAP_CMD_SET_STREAM:
3709
+		ret = rkisp_ioctl(sd, cmd, NULL);
3710
+		break;
3649
3711
 	default:
3650
3712
 		ret = -ENOIOCTLCMD;
3651
3713
 	}
..
..
@@ -3699,7 +3761,7 @@
3699
3761
 	struct ispsd_in_fmt *in_fmt = &isp_sd->in_fmt;
3700
3762
 	struct ispsd_out_fmt *out_fmt = &isp_sd->out_fmt;
3701
3763
 
3702
-	*in_fmt = rkisp_isp_input_formats[0];
3764
+	*in_fmt = rkisp_isp_input_formats[8];
3703
3765
 	in_frm->width = RKISP_DEFAULT_WIDTH;
3704
3766
 	in_frm->height = RKISP_DEFAULT_HEIGHT;
3705
3767
 	in_frm->code = in_fmt->mbus_code;
..
..
@@ -3765,6 +3827,7 @@
3765
3827
 	atomic_set(&isp_sdev->frm_sync_seq, 0);
3766
3828
 	rkisp_monitor_init(isp_dev);
3767
3829
 	INIT_WORK(&isp_dev->rdbk_work, rkisp_rdbk_work);
3830
+	init_completion(&isp_dev->pm_cmpl);
3768
3831
 	return 0;
3769
3832
 err_cleanup_media_entity:
3770
3833
 	media_entity_cleanup(&sd->entity);
..
..
@@ -3804,9 +3867,54 @@
3804
3867
 	(cond) ? 0 : -ETIMEDOUT; \
3805
3868
 })
3806
3869
 
3870
+void rkisp_save_tb_info(struct rkisp_device *isp_dev)
3871
+{
3872
+	struct rkisp_isp_params_vdev *params_vdev = &isp_dev->params_vdev;
3873
+	void *resmem_va = phys_to_virt(isp_dev->resmem_pa);
3874
+	struct rkisp_thunderboot_resmem_head *head = resmem_va;
3875
+	int size = 0, offset = 0;
3876
+	void *param = NULL;
3877
+
3878
+	switch (isp_dev->isp_ver) {
3879
+	case ISP_V32:
3880
+		size = sizeof(struct rkisp32_thunderboot_resmem_head);
3881
+		offset = size * isp_dev->dev_id;
3882
+		break;
3883
+	default:
3884
+		break;
3885
+	}
3886
+
3887
+	if (size && size < isp_dev->resmem_size) {
3888
+		dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr + offset,
3889
+					size, DMA_FROM_DEVICE);
3890
+		if (isp_dev->is_rtt_first)
3891
+			params_vdev->is_first_cfg = true;
3892
+		if (isp_dev->isp_ver == ISP_V32) {
3893
+			struct rkisp32_thunderboot_resmem_head *tmp = resmem_va + offset;
3894
+
3895
+			param = &tmp->cfg;
3896
+			head = &tmp->head;
3897
+			v4l2_info(&isp_dev->v4l2_dev,
3898
+				  "tb param module en:0x%llx upd:0x%llx cfg upd:0x%llx\n",
3899
+				  tmp->cfg.module_en_update,
3900
+				  tmp->cfg.module_ens,
3901
+				  tmp->cfg.module_cfg_update);
3902
+		}
3903
+		if (param && (isp_dev->isp_state & ISP_STOP))
3904
+			params_vdev->ops->save_first_param(params_vdev, param);
3905
+	} else if (size > isp_dev->resmem_size) {
3906
+		v4l2_err(&isp_dev->v4l2_dev,
3907
+			 "resmem size:%zu no enough for head:%d\n",
3908
+			 isp_dev->resmem_size, size);
3909
+		head->complete = RKISP_TB_NG;
3910
+	}
3911
+	memcpy(&isp_dev->tb_head, head, sizeof(*head));
3912
+}
3913
+
3807
3914
 #ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
3808
3915
 void rkisp_chk_tb_over(struct rkisp_device *isp_dev)
3809
3916
 {
3917
+	struct rkisp_isp_params_vdev *params_vdev = &isp_dev->params_vdev;
3810
3918
 	struct rkisp_hw_dev *hw = isp_dev->hw_dev;
3811
3919
 	struct rkisp_thunderboot_resmem_head *head;
3812
3920
 	enum rkisp_tb_state tb_state;
..
..
@@ -3815,19 +3923,20 @@
3815
3923
 	if (!isp_dev->is_thunderboot)
3816
3924
 		return;
3817
3925
 
3926
+	if (isp_dev->isp_ver == ISP_V32 && params_vdev->is_first_cfg)
3927
+		goto end;
3928
+
3818
3929
 	resmem_va = phys_to_virt(isp_dev->resmem_pa);
3819
3930
 	head = (struct rkisp_thunderboot_resmem_head *)resmem_va;
3820
3931
 	dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr,
3821
3932
 				sizeof(struct rkisp_thunderboot_resmem_head),
3822
3933
 				DMA_FROM_DEVICE);
3823
3934
 
3824
-	shm_head_poll_timeout(isp_dev, !!head->complete, 5000, 200 * USEC_PER_MSEC);
3935
+	shm_head_poll_timeout(isp_dev, !!head->complete, 5000, 400 * USEC_PER_MSEC);
3825
3936
 	if (head->complete != RKISP_TB_OK) {
3826
3937
 		v4l2_err(&isp_dev->v4l2_dev, "wait thunderboot over timeout\n");
3827
3938
 	} else {
3828
-		struct rkisp_isp_params_vdev *params_vdev = &isp_dev->params_vdev;
3829
-		void *param = NULL;
3830
-		u32 size = 0, offset = 0, timeout = 50;
3939
+		int i, timeout = 50;
3831
3940
 
3832
3941
 		/* wait for all isp dev to register */
3833
3942
 		if (head->camera_num > 1) {
..
..
@@ -3837,48 +3946,23 @@
3837
3946
 					break;
3838
3947
 				usleep_range(200, 210);
3839
3948
 			}
3840
-		}
3841
-
3842
-		switch (isp_dev->isp_ver) {
3843
-		case ISP_V32:
3844
-			size = sizeof(struct rkisp32_thunderboot_resmem_head);
3845
-			offset = size * isp_dev->dev_id;
3846
-			break;
3847
-		default:
3848
-			break;
3849
-		}
3850
-
3851
-		if (size && size < isp_dev->resmem_size) {
3852
-			dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr + offset,
3853
-						size, DMA_FROM_DEVICE);
3854
-			params_vdev->is_first_cfg = true;
3855
-			if (isp_dev->isp_ver == ISP_V32) {
3856
-				struct rkisp32_thunderboot_resmem_head *tmp = resmem_va + offset;
3857
-
3858
-				param = &tmp->cfg;
3859
-				head = &tmp->head;
3860
-				v4l2_info(&isp_dev->v4l2_dev,
3861
-					  "tb param module en:0x%llx upd:0x%llx cfg upd:0x%llx\n",
3862
-					  tmp->cfg.module_en_update,
3863
-					  tmp->cfg.module_ens,
3864
-					  tmp->cfg.module_cfg_update);
3949
+			if (head->camera_num > hw->dev_num) {
3950
+				v4l2_err(&isp_dev->v4l2_dev,
3951
+					 "thunderboot invalid camera num:%d, dev num:%d\n",
3952
+					 head->camera_num, hw->dev_num);
3953
+				goto end;
3865
3954
 			}
3866
-			if (param)
3867
-				params_vdev->ops->save_first_param(params_vdev, param);
3868
-		} else if (size > isp_dev->resmem_size) {
3869
-			v4l2_err(&isp_dev->v4l2_dev,
3870
-				 "resmem size:%zu no enough for head:%d\n",
3871
-				 isp_dev->resmem_size, size);
3872
-			head->complete = RKISP_TB_NG;
3873
3955
 		}
3956
+		for (i = 0; i < head->camera_num; i++)
3957
+			rkisp_save_tb_info(hw->isp[i]);
3874
3958
 	}
3875
-	memcpy(&isp_dev->tb_head, head, sizeof(*head));
3959
+end:
3960
+	head = &isp_dev->tb_head;
3876
3961
 	v4l2_info(&isp_dev->v4l2_dev,
3877
-		  "thunderboot info: %d, %d, %d, %d, %d, %d | %d %d\n",
3962
+		  "tb info en:%d comp:%d cnt:%d w:%d h:%d cam:%d idx:%d\n",
3878
3963
 		  head->enable,
3879
3964
 		  head->complete,
3880
3965
 		  head->frm_total,
3881
-		  head->hdr_mode,
3882
3966
 		  head->width,
3883
3967
 		  head->height,
3884
3968
 		  head->camera_num,
..
..
@@ -4005,7 +4089,7 @@
4005
4089
 		   struct rkisp_device *dev)
4006
4090
 {
4007
4091
 	struct rkisp_hw_dev *hw = dev->hw_dev;
4008
-	void __iomem *base = !hw->is_unite ?
4092
+	void __iomem *base = hw->unite != ISP_UNITE_TWO ?
4009
4093
 		hw->base_addr : hw->base_next_addr;
4010
4094
 	unsigned int isp_mis_tmp = 0;
4011
4095
 	unsigned int isp_err = 0;
..
..
@@ -4026,7 +4110,7 @@
4026
4110
 	if (isp3a_mis & ISP2X_3A_RAWAE_BIG && dev->params_vdev.rdbk_times > 0)
4027
4111
 		writel(BIT(31), base + RAWAE_BIG1_BASE + RAWAE_BIG_CTRL);
4028
4112
 
4029
-	if (hw->is_unite) {
4113
+	if (hw->unite == ISP_UNITE_TWO) {
4030
4114
 		u32 val = rkisp_read(dev, ISP3X_ISP_RIS, true);
4031
4115
 
4032
4116
 		if (val) {
..
..
@@ -4057,9 +4141,14 @@
4057
4141
 		}
4058
4142
 
4059
4143
 		if (IS_HDR_RDBK(dev->hdr.op_mode)) {
4060
-			/* read 3d lut at isp readback */
4061
-			if (!dev->hw_dev->is_single)
4062
-				rkisp_write(dev, ISP_3DLUT_UPDATE, 0, true);
4144
+			/* disabled frame end to read 3dlut for multi sensor
4145
+			 * 3dlut will update at isp readback
4146
+			 */
4147
+			if (!dev->hw_dev->is_single) {
4148
+				writel(0, hw->base_addr + ISP_3DLUT_UPDATE);
4149
+				if (hw->unite == ISP_UNITE_TWO)
4150
+					writel(0, hw->base_next_addr + ISP_3DLUT_UPDATE);
4151
+			}
4063
4152
 			rkisp_stats_rdbk_enable(&dev->stats_vdev, true);
4064
4153
 			goto vs_skip;
4065
4154
 		}
..
..
@@ -4087,7 +4176,7 @@
4087
4176
 		if (isp_mis & CIF_ISP_FRAME)
4088
4177
 			sof_event_later = true;
4089
4178
 		if (dev->vs_irq < 0 && !sof_event_later) {
4090
-			dev->isp_sdev.frm_timestamp = ktime_get_ns();
4179
+			dev->isp_sdev.frm_timestamp = rkisp_time_get_ns(dev);
4091
4180
 			rkisp_isp_queue_event_sof(&dev->isp_sdev);
4092
4181
 			rkisp_stream_frame_start(dev, isp_mis);
4093
4182
 		}
..
..
@@ -4155,7 +4244,7 @@
4155
4244
 	/* sampled input frame is complete */
4156
4245
 	if (isp_mis & CIF_ISP_FRAME_IN) {
4157
4246
 		dev->isp_sdev.dbg.interval =
4158
-			ktime_get_ns() - dev->isp_sdev.dbg.timestamp;
4247
+			rkisp_time_get_ns(dev) - dev->isp_sdev.dbg.timestamp;
4159
4248
 		rkisp_set_state(&dev->isp_state, ISP_FRAME_IN);
4160
4249
 		writel(CIF_ISP_FRAME_IN, base + CIF_ISP_ICR);
4161
4250
 		isp_mis_tmp = readl(base + CIF_ISP_MIS);
..
..
@@ -4169,7 +4258,7 @@
4169
4258
 		dev->rawaf_irq_cnt = 0;
4170
4259
 		if (!dev->is_pre_on || !IS_HDR_RDBK(dev->rd_mode))
4171
4260
 			dev->isp_sdev.dbg.interval =
4172
-				ktime_get_ns() - dev->isp_sdev.dbg.timestamp;
4261
+				rkisp_time_get_ns(dev) - dev->isp_sdev.dbg.timestamp;
4173
4262
 		/* Clear Frame In (ISP) */
4174
4263
 		rkisp_set_state(&dev->isp_state, ISP_FRAME_END);
4175
4264
 		writel(CIF_ISP_FRAME, base + CIF_ISP_ICR);
..
..
@@ -4189,7 +4278,7 @@
4189
4278
 			u64 tmp = dev->isp_sdev.dbg.interval +
4190
4279
 					dev->isp_sdev.dbg.timestamp;
4191
4280
 
4192
-			dev->isp_sdev.dbg.timestamp = ktime_get_ns();
4281
+			dev->isp_sdev.dbg.timestamp = rkisp_time_get_ns(dev);
4193
4282
 			/* v-blank: frame(N)start - frame(N-1)end */
4194
4283
 			dev->isp_sdev.dbg.delay = dev->isp_sdev.dbg.timestamp - tmp;
4195
4284
 		}
..
..
@@ -4241,7 +4330,7 @@
4241
4330
 
4242
4331
 	/* cur frame end and next frame start irq togeter */
4243
4332
 	if (dev->vs_irq < 0 && sof_event_later) {
4244
-		dev->isp_sdev.frm_timestamp = ktime_get_ns();
4333
+		dev->isp_sdev.frm_timestamp = rkisp_time_get_ns(dev);
4245
4334
 		rkisp_isp_queue_event_sof(&dev->isp_sdev);
4246
4335
 		rkisp_stream_frame_start(dev, isp_mis);
4247
4336
 	}