~hc/RK356X_SDK_RELEASE.git

..	..	@@ -15,9 +15,348 @@
15	15
16	16	#define CIF_ISP_REQ_BUFS_MIN 0
17	17
18		-static int mi_frame_end(struct rkisp_stream *stream);
	18	+static int mi_frame_end(struct rkisp_stream *stream, u32 state);
19	19	static void rkisp_buf_queue(struct vb2_buffer *vb);
20	20
	21	+static const struct capture_fmt mp_fmts[] = {
	22	+ /* yuv422 */
	23	+ {
	24	+ .fourcc = V4L2_PIX_FMT_UYVY,
	25	+ .fmt_type = FMT_YUV,
	26	+ .bpp = { 16 },
	27	+ .cplanes = 1,
	28	+ .mplanes = 1,
	29	+ .uv_swap = 0,
	30	+ .write_format = MI_CTRL_MP_WRITE_YUVINT,
	31	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	32	+ }, {
	33	+ .fourcc = V4L2_PIX_FMT_YUV422P,
	34	+ .fmt_type = FMT_YUV,
	35	+ .bpp = { 8, 4, 4 },
	36	+ .cplanes = 3,
	37	+ .mplanes = 1,
	38	+ .uv_swap = 0,
	39	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	40	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	41	+ }, {
	42	+ .fourcc = V4L2_PIX_FMT_NV16,
	43	+ .fmt_type = FMT_YUV,
	44	+ .bpp = { 8, 16 },
	45	+ .cplanes = 2,
	46	+ .mplanes = 1,
	47	+ .uv_swap = 0,
	48	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	49	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	50	+ }, {
	51	+ .fourcc = V4L2_PIX_FMT_NV61,
	52	+ .fmt_type = FMT_YUV,
	53	+ .bpp = { 8, 16 },
	54	+ .cplanes = 2,
	55	+ .mplanes = 1,
	56	+ .uv_swap = 1,
	57	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	58	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	59	+ }, {
	60	+ .fourcc = V4L2_PIX_FMT_YUV422M,
	61	+ .fmt_type = FMT_YUV,
	62	+ .bpp = { 8, 8, 8 },
	63	+ .cplanes = 3,
	64	+ .mplanes = 3,
	65	+ .uv_swap = 0,
	66	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	67	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	68	+ },
	69	+ /* yuv420 */
	70	+ {
	71	+ .fourcc = V4L2_PIX_FMT_NV21,
	72	+ .fmt_type = FMT_YUV,
	73	+ .bpp = { 8, 16 },
	74	+ .cplanes = 2,
	75	+ .mplanes = 1,
	76	+ .uv_swap = 1,
	77	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	78	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	79	+ }, {
	80	+ .fourcc = V4L2_PIX_FMT_NV12,
	81	+ .fmt_type = FMT_YUV,
	82	+ .bpp = { 8, 16 },
	83	+ .cplanes = 2,
	84	+ .mplanes = 1,
	85	+ .uv_swap = 0,
	86	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	87	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	88	+ }, {
	89	+ .fourcc = V4L2_PIX_FMT_NV21M,
	90	+ .fmt_type = FMT_YUV,
	91	+ .bpp = { 8, 16 },
	92	+ .cplanes = 2,
	93	+ .mplanes = 2,
	94	+ .uv_swap = 1,
	95	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	96	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	97	+ }, {
	98	+ .fourcc = V4L2_PIX_FMT_NV12M,
	99	+ .fmt_type = FMT_YUV,
	100	+ .bpp = { 8, 16 },
	101	+ .cplanes = 2,
	102	+ .mplanes = 2,
	103	+ .uv_swap = 0,
	104	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	105	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	106	+ }, {
	107	+ .fourcc = V4L2_PIX_FMT_YUV420,
	108	+ .fmt_type = FMT_YUV,
	109	+ .bpp = { 8, 8, 8 },
	110	+ .cplanes = 3,
	111	+ .mplanes = 1,
	112	+ .uv_swap = 0,
	113	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	114	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	115	+ },
	116	+ /* yuv444 */
	117	+ {
	118	+ .fourcc = V4L2_PIX_FMT_YUV444M,
	119	+ .fmt_type = FMT_YUV,
	120	+ .bpp = { 8, 8, 8 },
	121	+ .cplanes = 3,
	122	+ .mplanes = 3,
	123	+ .uv_swap = 0,
	124	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	125	+ .output_format = 0,
	126	+ },
	127	+ /* raw */
	128	+ {
	129	+ .fourcc = V4L2_PIX_FMT_SRGGB8,
	130	+ .fmt_type = FMT_BAYER,
	131	+ .bpp = { 8 },
	132	+ .mplanes = 1,
	133	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	134	+ .output_format = 0,
	135	+ }, {
	136	+ .fourcc = V4L2_PIX_FMT_SGRBG8,
	137	+ .fmt_type = FMT_BAYER,
	138	+ .bpp = { 8 },
	139	+ .mplanes = 1,
	140	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	141	+ .output_format = 0,
	142	+ }, {
	143	+ .fourcc = V4L2_PIX_FMT_SGBRG8,
	144	+ .fmt_type = FMT_BAYER,
	145	+ .bpp = { 8 },
	146	+ .mplanes = 1,
	147	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	148	+ .output_format = 0,
	149	+ }, {
	150	+ .fourcc = V4L2_PIX_FMT_SBGGR8,
	151	+ .fmt_type = FMT_BAYER,
	152	+ .bpp = { 8 },
	153	+ .mplanes = 1,
	154	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	155	+ .output_format = 0,
	156	+ }, {
	157	+ .fourcc = V4L2_PIX_FMT_SRGGB10,
	158	+ .fmt_type = FMT_BAYER,
	159	+ .bpp = { 10 },
	160	+ .mplanes = 1,
	161	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	162	+ .output_format = 0,
	163	+ }, {
	164	+ .fourcc = V4L2_PIX_FMT_SGRBG10,
	165	+ .fmt_type = FMT_BAYER,
	166	+ .bpp = { 10 },
	167	+ .mplanes = 1,
	168	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	169	+ .output_format = 0,
	170	+ }, {
	171	+ .fourcc = V4L2_PIX_FMT_SGBRG10,
	172	+ .fmt_type = FMT_BAYER,
	173	+ .bpp = { 10 },
	174	+ .mplanes = 1,
	175	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	176	+ .output_format = 0,
	177	+ }, {
	178	+ .fourcc = V4L2_PIX_FMT_SBGGR10,
	179	+ .fmt_type = FMT_BAYER,
	180	+ .bpp = { 10 },
	181	+ .mplanes = 1,
	182	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	183	+ .output_format = 0,
	184	+ }, {
	185	+ .fourcc = V4L2_PIX_FMT_SRGGB12,
	186	+ .fmt_type = FMT_BAYER,
	187	+ .bpp = { 12 },
	188	+ .mplanes = 1,
	189	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	190	+ .output_format = 0,
	191	+ }, {
	192	+ .fourcc = V4L2_PIX_FMT_SGRBG12,
	193	+ .fmt_type = FMT_BAYER,
	194	+ .bpp = { 12 },
	195	+ .mplanes = 1,
	196	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	197	+ .output_format = 0,
	198	+ }, {
	199	+ .fourcc = V4L2_PIX_FMT_SGBRG12,
	200	+ .fmt_type = FMT_BAYER,
	201	+ .bpp = { 12 },
	202	+ .mplanes = 1,
	203	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	204	+ .output_format = 0,
	205	+ }, {
	206	+ .fourcc = V4L2_PIX_FMT_SBGGR12,
	207	+ .fmt_type = FMT_BAYER,
	208	+ .bpp = { 12 },
	209	+ .mplanes = 1,
	210	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	211	+ .output_format = 0,
	212	+ },
	213	+};
	214	+
	215	+static const struct capture_fmt sp_fmts[] = {
	216	+ /* yuv422 */
	217	+ {
	218	+ .fourcc = V4L2_PIX_FMT_UYVY,
	219	+ .fmt_type = FMT_YUV,
	220	+ .bpp = { 16 },
	221	+ .cplanes = 1,
	222	+ .mplanes = 1,
	223	+ .uv_swap = 0,
	224	+ .write_format = MI_CTRL_SP_WRITE_INT,
	225	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	226	+ }, {
	227	+ .fourcc = V4L2_PIX_FMT_YUV422P,
	228	+ .fmt_type = FMT_YUV,
	229	+ .bpp = { 8, 8, 8 },
	230	+ .cplanes = 3,
	231	+ .mplanes = 1,
	232	+ .uv_swap = 0,
	233	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	234	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	235	+ }, {
	236	+ .fourcc = V4L2_PIX_FMT_NV16,
	237	+ .fmt_type = FMT_YUV,
	238	+ .bpp = { 8, 16 },
	239	+ .cplanes = 2,
	240	+ .mplanes = 1,
	241	+ .uv_swap = 0,
	242	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	243	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	244	+ }, {
	245	+ .fourcc = V4L2_PIX_FMT_NV61,
	246	+ .fmt_type = FMT_YUV,
	247	+ .bpp = { 8, 16 },
	248	+ .cplanes = 2,
	249	+ .mplanes = 1,
	250	+ .uv_swap = 1,
	251	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	252	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	253	+ }, {
	254	+ .fourcc = V4L2_PIX_FMT_YUV422M,
	255	+ .fmt_type = FMT_YUV,
	256	+ .bpp = { 8, 8, 8 },
	257	+ .cplanes = 3,
	258	+ .mplanes = 3,
	259	+ .uv_swap = 0,
	260	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	261	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	262	+ },
	263	+ /* yuv420 */
	264	+ {
	265	+ .fourcc = V4L2_PIX_FMT_NV21,
	266	+ .fmt_type = FMT_YUV,
	267	+ .bpp = { 8, 16 },
	268	+ .cplanes = 2,
	269	+ .mplanes = 1,
	270	+ .uv_swap = 1,
	271	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	272	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	273	+ }, {
	274	+ .fourcc = V4L2_PIX_FMT_NV12,
	275	+ .fmt_type = FMT_YUV,
	276	+ .bpp = { 8, 16 },
	277	+ .cplanes = 2,
	278	+ .mplanes = 1,
	279	+ .uv_swap = 0,
	280	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	281	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	282	+ }, {
	283	+ .fourcc = V4L2_PIX_FMT_NV21M,
	284	+ .fmt_type = FMT_YUV,
	285	+ .bpp = { 8, 16 },
	286	+ .cplanes = 2,
	287	+ .mplanes = 2,
	288	+ .uv_swap = 1,
	289	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	290	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	291	+ }, {
	292	+ .fourcc = V4L2_PIX_FMT_NV12M,
	293	+ .fmt_type = FMT_YUV,
	294	+ .bpp = { 8, 16 },
	295	+ .cplanes = 2,
	296	+ .mplanes = 2,
	297	+ .uv_swap = 0,
	298	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	299	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	300	+ }, {
	301	+ .fourcc = V4L2_PIX_FMT_YUV420,
	302	+ .fmt_type = FMT_YUV,
	303	+ .bpp = { 8, 8, 8 },
	304	+ .cplanes = 3,
	305	+ .mplanes = 1,
	306	+ .uv_swap = 0,
	307	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	308	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	309	+ },
	310	+ /* yuv444 */
	311	+ {
	312	+ .fourcc = V4L2_PIX_FMT_YUV444M,
	313	+ .fmt_type = FMT_YUV,
	314	+ .bpp = { 8, 8, 8 },
	315	+ .cplanes = 3,
	316	+ .mplanes = 3,
	317	+ .uv_swap = 0,
	318	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	319	+ .output_format = MI_CTRL_SP_OUTPUT_YUV444,
	320	+ },
	321	+ /* yuv400 */
	322	+ {
	323	+ .fourcc = V4L2_PIX_FMT_GREY,
	324	+ .fmt_type = FMT_YUV,
	325	+ .bpp = { 8 },
	326	+ .cplanes = 1,
	327	+ .mplanes = 1,
	328	+ .uv_swap = 0,
	329	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	330	+ .output_format = MI_CTRL_SP_OUTPUT_YUV400,
	331	+ },
	332	+ /* rgb */
	333	+ {
	334	+ .fourcc = V4L2_PIX_FMT_XBGR32,
	335	+ .fmt_type = FMT_RGB,
	336	+ .bpp = { 32 },
	337	+ .mplanes = 1,
	338	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	339	+ .output_format = MI_CTRL_SP_OUTPUT_RGB888,
	340	+ }, {
	341	+ .fourcc = V4L2_PIX_FMT_RGB565,
	342	+ .fmt_type = FMT_RGB,
	343	+ .bpp = { 16 },
	344	+ .mplanes = 1,
	345	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	346	+ .output_format = MI_CTRL_SP_OUTPUT_RGB565,
	347	+ },
	348	+ /* fbcg */
	349	+ {
	350	+ .fourcc = V4L2_PIX_FMT_FBCG,
	351	+ .fmt_type = FMT_FBCGAIN,
	352	+ .bpp = { 8, 16 },
	353	+ .cplanes = 2,
	354	+ .mplanes = 2,
	355	+ .uv_swap = 0,
	356	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	357	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	358	+ }
	359	+};
21	360	static const struct capture_fmt dmatx_fmts[] = {
22	361	/* raw */
23	362	{
..	..	@@ -422,7 +761,7 @@
422	761	mp_mi_ctrl_autoupdate_en(base);
423	762
424	763	/* set up first buffer */
425		- mi_frame_end(stream);
	764	+ mi_frame_end(stream, FRAME_INIT);
426	765	return 0;
427	766	}
428	767
..	..	@@ -509,7 +848,7 @@
509	848	sp_mi_ctrl_autoupdate_en(base);
510	849
511	850	/* set up first buffer */
512		- mi_frame_end(stream);
	851	+ mi_frame_end(stream, FRAME_INIT);
513	852	return 0;
514	853	}
515	854
..	..	@@ -527,7 +866,7 @@
527	866
528	867	if (!dev->active_sensor \|\|
529	868	(dev->active_sensor &&
530		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	869	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
531	870	v4l2_err(&dev->v4l2_dev,
532	871	"only mipi sensor support rawwr3\n");
533	872	return -EINVAL;
..	..	@@ -545,7 +884,7 @@
545	884	stream->memory \|
546	885	SW_CSI_RAW_WR_EN_ORG);
547	886	mi_set_y_size(stream, in_size);
548		- mi_frame_end(stream);
	887	+ mi_frame_end(stream, FRAME_INIT);
549	888	mi_frame_end_int_enable(stream);
550	889	mi_wr_ctrl2(base, SW_RAW3_WR_AUTOUPD);
551	890	mi_raw_length(stream);
..	..	@@ -571,7 +910,7 @@
571	910
572	911	if (!dev->active_sensor \|\|
573	912	(dev->active_sensor &&
574		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	913	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
575	914	v4l2_err(&dev->v4l2_dev,
576	915	"only mipi sensor support rawwr2 path\n");
577	916	return -EINVAL;
..	..	@@ -591,7 +930,7 @@
591	930	val \|= SW_CSI_RAW_WR_EN_ORG;
592	931	raw_wr_ctrl(stream, val);
593	932	mi_set_y_size(stream, in_size);
594		- mi_frame_end(stream);
	933	+ mi_frame_end(stream, FRAME_INIT);
595	934	mi_frame_end_int_enable(stream);
596	935	mi_wr_ctrl2(base, SW_RAW2_WR_AUTOUPD);
597	936	mi_raw_length(stream);
..	..	@@ -614,7 +953,7 @@
614	953
615	954	if (!dev->active_sensor \|\|
616	955	(dev->active_sensor &&
617		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	956	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
618	957	if (stream->id == RKISP_STREAM_DMATX1)
619	958	v4l2_err(&dev->v4l2_dev,
620	959	"only mipi sensor support dmatx1 path\n");
..	..	@@ -635,7 +974,7 @@
635	974	val \|= SW_CSI_RAW_WR_EN_ORG;
636	975	raw_wr_ctrl(stream, val);
637	976	mi_set_y_size(stream, in_size);
638		- mi_frame_end(stream);
	977	+ mi_frame_end(stream, FRAME_INIT);
639	978	mi_frame_end_int_enable(stream);
640	979	mi_wr_ctrl2(base, SW_RAW1_WR_AUTOUPD);
641	980	mi_raw_length(stream);
..	..	@@ -660,7 +999,7 @@
660	999
661	1000	if (!dev->active_sensor \|\|
662	1001	(dev->active_sensor &&
663		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	1002	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
664	1003	if (stream->id == RKISP_STREAM_DMATX0)
665	1004	v4l2_err(&dev->v4l2_dev,
666	1005	"only mipi sensor support rawwr0 path\n");
..	..	@@ -683,7 +1022,7 @@
683	1022	val \|= SW_CSI_RAW_WR_EN_ORG;
684	1023	raw_wr_ctrl(dmatx, val);
685	1024	mi_set_y_size(dmatx, in_size);
686		- mi_frame_end(dmatx);
	1025	+ mi_frame_end(dmatx, FRAME_INIT);
687	1026	mi_frame_end_int_enable(dmatx);
688	1027	mi_wr_ctrl2(base, SW_RAW0_WR_AUTOUPD);
689	1028	mi_raw_length(stream);
..	..	@@ -840,7 +1179,7 @@
840	1179	.enable_mi = mp_enable_mi,
841	1180	.disable_mi = mp_disable_mi,
842	1181	.stop_mi = mp_stop_mi,
843		- .set_data_path = mp_set_data_path,
	1182	+ .set_data_path = stream_data_path,
844	1183	.is_stream_stopped = mp_is_stream_stopped,
845	1184	.update_mi = update_mi,
846	1185	.frame_end = mi_frame_end,
..	..	@@ -851,7 +1190,7 @@
851	1190	.enable_mi = sp_enable_mi,
852	1191	.disable_mi = sp_disable_mi,
853	1192	.stop_mi = sp_stop_mi,
854		- .set_data_path = sp_set_data_path,
	1193	+ .set_data_path = stream_data_path,
855	1194	.is_stream_stopped = sp_is_stream_stopped,
856	1195	.update_mi = update_mi,
857	1196	.frame_end = mi_frame_end,
..	..	@@ -941,16 +1280,11 @@
941	1280	goto RDBK_FRM_UNMATCH;
942	1281	}
943	1282
944		- cap->rdbk_buf[RDBK_S]->vb.sequence =
945		- cap->rdbk_buf[RDBK_L]->vb.sequence;
946		- cap->rdbk_buf[RDBK_M]->vb.sequence =
947		- cap->rdbk_buf[RDBK_L]->vb.sequence;
948		- vb2_buffer_done(&cap->rdbk_buf[RDBK_L]->vb.vb2_buf,
949		- VB2_BUF_STATE_DONE);
950		- vb2_buffer_done(&cap->rdbk_buf[RDBK_M]->vb.vb2_buf,
951		- VB2_BUF_STATE_DONE);
952		- vb2_buffer_done(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf,
953		- VB2_BUF_STATE_DONE);
	1283	+ cap->rdbk_buf[RDBK_S]->vb.sequence = cap->rdbk_buf[RDBK_L]->vb.sequence;
	1284	+ cap->rdbk_buf[RDBK_M]->vb.sequence = cap->rdbk_buf[RDBK_L]->vb.sequence;
	1285	+ rkisp_stream_buf_done(&cap->stream[RKISP_STREAM_DMATX0], cap->rdbk_buf[RDBK_L]);
	1286	+ rkisp_stream_buf_done(&cap->stream[RKISP_STREAM_DMATX1], cap->rdbk_buf[RDBK_M]);
	1287	+ rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
954	1288	} else {
955	1289	v4l2_err(&isp_dev->v4l2_dev, "lost long or middle frames\n");
956	1290	goto RDBK_FRM_UNMATCH;
..	..	@@ -985,18 +1319,15 @@
985	1319	goto RDBK_FRM_UNMATCH;
986	1320	}
987	1321
988		- cap->rdbk_buf[RDBK_S]->vb.sequence =
989		- cap->rdbk_buf[RDBK_L]->vb.sequence;
990		- vb2_buffer_done(&cap->rdbk_buf[RDBK_L]->vb.vb2_buf,
991		- VB2_BUF_STATE_DONE);
992		- vb2_buffer_done(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf,
993		- VB2_BUF_STATE_DONE);
	1322	+ cap->rdbk_buf[RDBK_S]->vb.sequence = cap->rdbk_buf[RDBK_L]->vb.sequence;
	1323	+ rkisp_stream_buf_done(&cap->stream[RKISP_STREAM_DMATX0], cap->rdbk_buf[RDBK_L]);
	1324	+ rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
994	1325	} else {
995	1326	v4l2_err(&isp_dev->v4l2_dev, "lost long frames\n");
996	1327	goto RDBK_FRM_UNMATCH;
997	1328	}
998	1329	} else {
999		- vb2_buffer_done(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf, VB2_BUF_STATE_DONE);
	1330	+ rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
1000	1331	}
1001	1332
1002	1333	cap->rdbk_buf[RDBK_L] = NULL;
..	..	@@ -1022,7 +1353,7 @@
1022	1353	* is processing and we should set up buffer for next-next frame,
1023	1354	* otherwise it will overflow.
1024	1355	*/
1025		-static int mi_frame_end(struct rkisp_stream *stream)
	1356	+static int mi_frame_end(struct rkisp_stream *stream, u32 state)
1026	1357	{
1027	1358	struct rkisp_device *dev = stream->ispdev;
1028	1359	struct rkisp_capture_device *cap = &dev->cap_dev;
..	..	@@ -1061,10 +1392,10 @@
1061	1392	stream->curr_buf->vb.sequence =
1062	1393	atomic_read(&stream->sequence) - 1;
1063	1394	if (!ns)
1064		- ns = ktime_get_ns();
	1395	+ ns = rkisp_time_get_ns(dev);
1065	1396	vb2_buf->timestamp = ns;
1066	1397
1067		- ns = ktime_get_ns();
	1398	+ ns = rkisp_time_get_ns(dev);
1068	1399	stream->dbg.interval = ns - stream->dbg.timestamp;
1069	1400	stream->dbg.timestamp = ns;
1070	1401	stream->dbg.id = stream->curr_buf->vb.sequence;
..	..	@@ -1101,18 +1432,18 @@
1101	1432	cap->rdbk_buf[RDBK_S] = stream->curr_buf;
1102	1433	rdbk_frame_end(stream);
1103	1434	} else {
1104		- vb2_buffer_done(vb2_buf, VB2_BUF_STATE_DONE);
	1435	+ rkisp_stream_buf_done(stream, stream->curr_buf);
1105	1436	}
1106	1437	} else {
1107	1438	if (stream->id == RKISP_STREAM_SP && isp_fmt->fmt_type == FMT_FBCGAIN) {
1108	1439	u32 sizeimage = vb2_plane_size(&stream->curr_buf->vb.vb2_buf, 0);
1109	1440	u32 buf = (u32 )vb2_plane_vaddr(&stream->curr_buf->vb.vb2_buf, 0);
1110	1441
1111		- (u64 )(buf + sizeimage / 4 - 2) = ktime_get_ns();
	1442	+ (u64 )(buf + sizeimage / 4 - 2) = rkisp_time_get_ns(dev);
1112	1443	stream->curr_buf->dev_id = dev->dev_id;
1113	1444	rkisp_bridge_save_spbuf(dev, stream->curr_buf);
1114	1445	} else {
1115		- vb2_buffer_done(vb2_buf, VB2_BUF_STATE_DONE);
	1446	+ rkisp_stream_buf_done(stream, stream->curr_buf);
1116	1447	}
1117	1448	}
1118	1449
..	..	@@ -1187,7 +1518,8 @@
1187	1518	stream->stopping = true;
1188	1519	stream->ops->stop_mi(stream);
1189	1520	if ((dev->isp_state & ISP_START) &&
1190		- dev->isp_inp != INP_DMARX_ISP) {
	1521	+ dev->isp_inp != INP_DMARX_ISP &&
	1522	+ !dev->hw_dev->is_shutdown) {
1191	1523	ret = wait_event_timeout(stream->done,
1192	1524	!stream->streaming,
1193	1525	msecs_to_jiffies(1000));
..	..	@@ -1219,7 +1551,6 @@
1219	1551	*/
1220	1552	static int rkisp_start(struct rkisp_stream *stream)
1221	1553	{
1222		- void __iomem *base = stream->ispdev->base_addr;
1223	1554	struct rkisp_device *dev = stream->ispdev;
1224	1555	int ret;
1225	1556
..	..	@@ -1230,7 +1561,7 @@
1230	1561	hdr_config_dmatx(dev);
1231	1562
1232	1563	if (stream->ops->set_data_path)
1233		- stream->ops->set_data_path(base);
	1564	+ stream->ops->set_data_path(stream);
1234	1565	ret = stream->ops->config_mi(stream);
1235	1566	if (ret)
1236	1567	return ret;
..	..	@@ -1408,6 +1739,12 @@
1408	1739	list_del(&buf->queue);
1409	1740	vb2_buffer_done(&buf->vb.vb2_buf, state);
1410	1741	}
	1742	+ while (!list_empty(&stream->buf_done_list)) {
	1743	+ buf = list_first_entry(&stream->buf_done_list,
	1744	+ struct rkisp_buffer, queue);
	1745	+ list_del(&buf->queue);
	1746	+ vb2_buffer_done(&buf->vb.vb2_buf, state);
	1747	+ }
1411	1748	spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1412	1749	}
1413	1750
..	..	@@ -1451,6 +1788,7 @@
1451	1788	rkisp_destroy_dummy_buf(stream);
1452	1789	atomic_dec(&dev->cap_dev.refcnt);
1453	1790	stream->start_stream = false;
	1791	+ tasklet_disable(&stream->buf_done_tasklet);
1454	1792	end:
1455	1793	mutex_unlock(&dev->hw_dev->dev_lock);
1456	1794	}
..	..	@@ -1584,7 +1922,7 @@
1584	1922	}
1585	1923
1586	1924	stream->start_stream = true;
1587		-
	1925	+ tasklet_enable(&stream->buf_done_tasklet);
1588	1926	mutex_unlock(&dev->hw_dev->dev_lock);
1589	1927	return 0;
1590	1928
..	..	@@ -1652,7 +1990,7 @@
1652	1990	init_waitqueue_head(&stream->done);
1653	1991	spin_lock_init(&stream->vbq_lock);
1654	1992
1655		- stream->linked = MEDIA_LNK_FL_ENABLED;
	1993	+ stream->linked = true;
1656	1994	/* isp2 disable MP/SP, enable BRIDGE default */
1657	1995	if (id == RKISP_STREAM_MP)
1658	1996	stream->linked = false;
..	..	@@ -1663,6 +2001,8 @@
1663	2001	sizeof(vdev->name));
1664	2002	stream->ops = &rkisp_sp_streams_ops;
1665	2003	stream->config = &rkisp_sp_stream_config;
	2004	+ stream->config->fmts = sp_fmts;
	2005	+ stream->config->fmt_size = ARRAY_SIZE(sp_fmts);
1666	2006	break;
1667	2007	case RKISP_STREAM_DMATX0:
1668	2008	strlcpy(vdev->name, DMATX0_VDEV_NAME,
..	..	@@ -1693,6 +2033,8 @@
1693	2033	sizeof(vdev->name));
1694	2034	stream->ops = &rkisp_mp_streams_ops;
1695	2035	stream->config = &rkisp_mp_stream_config;
	2036	+ stream->config->fmts = mp_fmts;
	2037	+ stream->config->fmt_size = ARRAY_SIZE(mp_fmts);
1696	2038	}
1697	2039
1698	2040	node = vdev_to_node(vdev);
..	..	@@ -1826,7 +2168,7 @@
1826	2168	void rkisp_update_spstream_buf(struct rkisp_stream *stream)
1827	2169	{
1828	2170	if (stream->id == RKISP_STREAM_SP && stream->out_isp_fmt.fmt_type == FMT_FBCGAIN)
1829		- mi_frame_end(stream);
	2171	+ mi_frame_end(stream, FRAME_INIT);
1830	2172	}
1831	2173
1832	2174	/************** Interrupter Handler **************/
..	..	@@ -1869,7 +2211,7 @@
1869	2211	* frame end that sync the configurations to shadow
1870	2212	* regs.
1871	2213	*/
1872		- if (stream->ops->is_stream_stopped(dev->base_addr)) {
	2214	+ if (stream->ops->is_stream_stopped(stream)) {
1873	2215	stream->stopping = false;
1874	2216	stream->streaming = false;
1875	2217	wake_up(&stream->done);
..	..	@@ -1880,7 +2222,7 @@
1880	2222	end_tx2 = false;
1881	2223	}
1882	2224	} else {
1883		- mi_frame_end(stream);
	2225	+ mi_frame_end(stream, FRAME_IRQ);
1884	2226	if (dev->dmarx_dev.trigger == T_AUTO &&
1885	2227	((dev->hdr.op_mode == HDR_RDBK_FRAME1 && end_tx2) \|\|
1886	2228	(dev->hdr.op_mode == HDR_RDBK_FRAME2 && end_tx2 && end_tx0) \|\|