| .. | .. |
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| 626 | 626 | |
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| 627 | 627 | max_rsz->width = ALIGN(DIV_ROUND_UP(input_win->width, div), 4); |
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| 628 | 628 | max_rsz->height = DIV_ROUND_UP(input_win->height, div); |
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| 629 | | - } else if (dev->hw_dev->is_unite) { |
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| 629 | + } else if (dev->hw_dev->unite) { |
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| 630 | 630 | /* scale down only for unite mode */ |
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| 631 | 631 | max_rsz->width = min_t(int, input_win->width, cfg->max_rsz_width); |
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| 632 | 632 | max_rsz->height = min_t(int, input_win->height, cfg->max_rsz_height); |
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| .. | .. |
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| 1140 | 1140 | |
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| 1141 | 1141 | if (dev->isp_ver != ISP_V32 || |
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| 1142 | 1142 | dev->hw_dev->dev_link_num > 1 || |
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| 1143 | | - !stream->ops->set_wrap) { |
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| 1143 | + !stream->ops->set_wrap || |
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| 1144 | + dev->hw_dev->unite) { |
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| 1144 | 1145 | v4l2_err(&dev->v4l2_dev, |
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| 1145 | 1146 | "wrap only support for single sensor and mainpath\n"); |
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| 1146 | 1147 | return -EINVAL; |
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| .. | .. |
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| 1465 | 1466 | const struct v4l2_rect *in) |
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| 1466 | 1467 | { |
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| 1467 | 1468 | struct rkisp_device *dev = stream->ispdev; |
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| 1468 | | - bool is_unite = dev->hw_dev->is_unite; |
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| 1469 | + bool is_unite = !!dev->hw_dev->unite; |
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| 1469 | 1470 | u32 align = is_unite ? 4 : 2; |
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| 1470 | 1471 | |
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| 1471 | 1472 | /* Not crop for MP bayer raw data and dmatx path */ |
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| .. | .. |
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| 1616 | 1617 | if (ispdev->isp_ver != ISP_V32) |
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| 1617 | 1618 | return; |
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| 1618 | 1619 | |
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| 1620 | + mutex_lock(&ispdev->hw_dev->dev_lock); |
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| 1619 | 1621 | rkisp_chk_tb_over(ispdev); |
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| 1622 | + mutex_unlock(&ispdev->hw_dev->dev_lock); |
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| 1620 | 1623 | if (ispdev->tb_head.complete != RKISP_TB_OK) |
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| 1621 | 1624 | return; |
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| 1622 | 1625 | ret = v4l2_pipeline_pm_get(&stream->vnode.vdev.entity); |
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| .. | .. |
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| 1733 | 1736 | st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V21; |
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| 1734 | 1737 | ret = rkisp_register_stream_v21(dev); |
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| 1735 | 1738 | } else if (dev->isp_ver == ISP_V30) { |
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| 1736 | | - st_cfg->max_rsz_width = dev->hw_dev->is_unite ? |
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| 1739 | + st_cfg->max_rsz_width = dev->hw_dev->unite ? |
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| 1737 | 1740 | CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30; |
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| 1738 | | - st_cfg->max_rsz_height = dev->hw_dev->is_unite ? |
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| 1741 | + st_cfg->max_rsz_height = dev->hw_dev->unite ? |
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| 1739 | 1742 | CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30; |
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| 1740 | 1743 | ret = rkisp_register_stream_v30(dev); |
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| 1741 | 1744 | } else if (dev->isp_ver == ISP_V32) { |
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| 1742 | | - st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32; |
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| 1743 | | - st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32; |
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| 1745 | + st_cfg->max_rsz_width = dev->hw_dev->unite ? |
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| 1746 | + CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32; |
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| 1747 | + st_cfg->max_rsz_height = dev->hw_dev->unite ? |
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| 1748 | + CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32; |
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| 1744 | 1749 | st_cfg = &rkisp_sp_stream_config; |
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| 1745 | | - st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32; |
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| 1746 | | - st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32; |
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| 1750 | + st_cfg->max_rsz_width = dev->hw_dev->unite ? |
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| 1751 | + CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32; |
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| 1752 | + st_cfg->max_rsz_height = dev->hw_dev->unite ? |
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| 1753 | + CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32; |
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| 1747 | 1754 | ret = rkisp_register_stream_v32(dev); |
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| 1748 | 1755 | } else if (dev->isp_ver == ISP_V32_L) { |
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| 1749 | 1756 | st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L; |
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