~hc/RK356X_SDK_RELEASE.git

..	..	@@ -61,6 +61,9 @@
61	61	CIF_REG_DVP_FRM0_ADDR_UV_ID3,
62	62	CIF_REG_DVP_FRM1_ADDR_Y_ID3,
63	63	CIF_REG_DVP_FRM1_ADDR_UV_ID3,
	64	+ CIF_REG_DVP_SAV_EAV,
	65	+ CIF_REG_DVP_LINE_CNT1,
	66	+ CIF_REG_DVP_LINE_INT_NUM1,
64	67	/* mipi & lvds registers index */
65	68	CIF_REG_MIPI_LVDS_ID0_CTRL0,
66	69	CIF_REG_MIPI_LVDS_ID0_CTRL1,
..	..	@@ -134,6 +137,20 @@
134	137	CIF_REG_LVDS_SAV_EAV_BLK0_ID3,
135	138	CIF_REG_LVDS_SAV_EAV_ACT1_ID3,
136	139	CIF_REG_LVDS_SAV_EAV_BLK1_ID3,
	140	+ CIF_REG_MIPI_EFFECT_CODE_ID0,
	141	+ CIF_REG_MIPI_EFFECT_CODE_ID1,
	142	+ CIF_REG_MIPI_EFFECT_CODE_ID2,
	143	+ CIF_REG_MIPI_EFFECT_CODE_ID3,
	144	+ CIF_REG_LVDS_ID0_CTRL0,
	145	+ CIF_REG_LVDS_ID1_CTRL0,
	146	+ CIF_REG_LVDS_ID2_CTRL0,
	147	+ CIF_REG_LVDS_ID3_CTRL0,
	148	+ CIF_REG_MIPI_FRAME_SIZE_ID0,
	149	+ CIF_REG_MIPI_FRAME_SIZE_ID1,
	150	+ CIF_REG_MIPI_FRAME_SIZE_ID2,
	151	+ CIF_REG_MIPI_FRAME_SIZE_ID3,
	152	+ CIF_REG_MIPI_ON_PAD,
	153	+
137	154	CIF_REG_Y_STAT_CONTROL,
138	155	CIF_REG_Y_STAT_VALUE,
139	156	CIF_REG_MMU_DTE_ADDR,
..	..	@@ -149,6 +166,35 @@
149	166	/* reg belowed is in grf */
150	167	CIF_REG_GRF_CIFIO_CON,
151	168	CIF_REG_GRF_CIFIO_CON1,
	169	+ CIF_REG_GRF_CIFIO_VENC,
	170	+ /* reg global control */
	171	+ CIF_REG_GLB_CTRL,
	172	+ CIF_REG_GLB_INTEN,
	173	+ CIF_REG_GLB_INTST,
	174	+ CIF_REG_SCL_CH_CTRL,
	175	+ CIF_REG_SCL_CTRL,
	176	+ CIF_REG_SCL_FRM0_ADDR_CH0,
	177	+ CIF_REG_SCL_FRM1_ADDR_CH0,
	178	+ CIF_REG_SCL_VLW_CH0,
	179	+ CIF_REG_SCL_FRM0_ADDR_CH1,
	180	+ CIF_REG_SCL_FRM1_ADDR_CH1,
	181	+ CIF_REG_SCL_VLW_CH1,
	182	+ CIF_REG_SCL_FRM0_ADDR_CH2,
	183	+ CIF_REG_SCL_FRM1_ADDR_CH2,
	184	+ CIF_REG_SCL_VLW_CH2,
	185	+ CIF_REG_SCL_FRM0_ADDR_CH3,
	186	+ CIF_REG_SCL_FRM1_ADDR_CH3,
	187	+ CIF_REG_SCL_VLW_CH3,
	188	+ CIF_REG_SCL_BLC_CH0,
	189	+ CIF_REG_SCL_BLC_CH1,
	190	+ CIF_REG_SCL_BLC_CH2,
	191	+ CIF_REG_SCL_BLC_CH3,
	192	+ CIF_REG_TOISP0_CTRL,
	193	+ CIF_REG_TOISP0_SIZE,
	194	+ CIF_REG_TOISP0_CROP,
	195	+ CIF_REG_TOISP1_CTRL,
	196	+ CIF_REG_TOISP1_SIZE,
	197	+ CIF_REG_TOISP1_CROP,
152	198	CIF_REG_INDEX_MAX
153	199	};
154	200
..	..	@@ -298,6 +344,143 @@
298	344	#define CIF_MMU_INT_STATUS 0x820
299	345	#define CIF_MMU_AUTO_GATING 0x824
300	346
	347	+/* RK3588 DVP Registers Offset */
	348	+#define DVP_CTRL 0x10
	349	+#define DVP_INTEN 0x14
	350	+#define DVP_INTSTAT 0x18
	351	+#define DVP_FOR 0x1C
	352	+#define DVP_MULTI_ID 0x20
	353	+#define DVP_SAV_EAV 0x24
	354	+#define DVP_CROP_SIZE 0x28
	355	+#define DVP_CROP 0x2C
	356	+#define DVP_FRM0_ADDR_Y_ID0 0x30
	357	+#define DVP_FRM0_ADDR_UV_ID0 0x34
	358	+#define DVP_FRM1_ADDR_Y_ID0 0x38
	359	+#define DVP_FRM1_ADDR_UV_ID0 0x3C
	360	+#define DVP_FRM0_ADDR_Y_ID1 0x40
	361	+#define DVP_FRM0_ADDR_UV_ID1 0x44
	362	+#define DVP_FRM1_ADDR_Y_ID1 0x48
	363	+#define DVP_FRM1_ADDR_UV_ID1 0x4C
	364	+#define DVP_FRM0_ADDR_Y_ID2 0x50
	365	+#define DVP_FRM0_ADDR_UV_ID2 0x54
	366	+#define DVP_FRM1_ADDR_Y_ID2 0x58
	367	+#define DVP_FRM1_ADDR_UV_ID2 0x5C
	368	+#define DVP_FRM0_ADDR_Y_ID3 0x60
	369	+#define DVP_FRM0_ADDR_UV_ID3 0x64
	370	+#define DVP_FRM1_ADDR_Y_ID3 0x68
	371	+#define DVP_FRM1_ADDR_UV_ID3 0x6C
	372	+#define DVP_VIR_LINE_WIDTH 0x70
	373	+#define DVP_LINE_INT_NUM_01 0x74
	374	+#define DVP_LINE_INT_NUM_23 0x78
	375	+#define DVP_LINE_CNT_01 0x7C
	376	+#define DVP_LINE_CNT_23 0x80
	377	+
	378	+/* RK3588 CSI Registers Offset */
	379	+#define CSI_MIPI0_ID0_CTRL0 0x100
	380	+#define CSI_MIPI0_ID0_CTRL1 0x104
	381	+#define CSI_MIPI0_ID1_CTRL0 0x108
	382	+#define CSI_MIPI0_ID1_CTRL1 0x10C
	383	+#define CSI_MIPI0_ID2_CTRL0 0x110
	384	+#define CSI_MIPI0_ID2_CTRL1 0x114
	385	+#define CSI_MIPI0_ID3_CTRL0 0x118
	386	+#define CSI_MIPI0_ID3_CTRL1 0x11C
	387	+#define CSI_MIPI0_CTRL 0x120
	388	+#define CSI_MIPI0_FRM0_ADDR_Y_ID0 0x124
	389	+#define CSI_MIPI0_FRM1_ADDR_Y_ID0 0x128
	390	+#define CSI_MIPI0_FRM0_ADDR_UV_ID0 0x12C
	391	+#define CSI_MIPI0_FRM1_ADDR_UV_ID0 0x130
	392	+#define CSI_MIPI0_VLW_ID0 0x134
	393	+#define CSI_MIPI0_FRM0_ADDR_Y_ID1 0x138
	394	+#define CSI_MIPI0_FRM1_ADDR_Y_ID1 0x13C
	395	+#define CSI_MIPI0_FRM0_ADDR_UV_ID1 0x140
	396	+#define CSI_MIPI0_FRM1_ADDR_UV_ID1 0x144
	397	+#define CSI_MIPI0_VLW_ID1 0x148
	398	+#define CSI_MIPI0_FRM0_ADDR_Y_ID2 0x14C
	399	+#define CSI_MIPI0_FRM1_ADDR_Y_ID2 0x150
	400	+#define CSI_MIPI0_FRM0_ADDR_UV_ID2 0x154
	401	+#define CSI_MIPI0_FRM1_ADDR_UV_ID2 0x158
	402	+#define CSI_MIPI0_VLW_ID2 0x15C
	403	+#define CSI_MIPI0_FRM0_ADDR_Y_ID3 0x160
	404	+#define CSI_MIPI0_FRM1_ADDR_Y_ID3 0x164
	405	+#define CSI_MIPI0_FRM0_ADDR_UV_ID3 0x168
	406	+#define CSI_MIPI0_FRM1_ADDR_UV_ID3 0x16C
	407	+#define CSI_MIPI0_VLW_ID3 0x170
	408	+#define CSI_MIPI0_INTEN 0x174
	409	+#define CSI_MIPI0_INTSTAT 0x178
	410	+#define CSI_MIPI0_LINE_INT_NUM_ID0_1 0x17C
	411	+#define CSI_MIPI0_LINE_INT_NUM_ID2_3 0x180
	412	+#define CSI_MIPI0_LINE_CNT_ID0_1 0x184
	413	+#define CSI_MIPI0_LINE_CNT_ID2_3 0x188
	414	+#define CSI_MIPI0_ID0_CROP_START 0x18C
	415	+#define CSI_MIPI0_ID1_CROP_START 0x190
	416	+#define CSI_MIPI0_ID2_CROP_START 0x194
	417	+#define CSI_MIPI0_ID3_CROP_START 0x198
	418	+#define CSI_MIPI0_FRAME_NUM_VC0 0x19C
	419	+#define CSI_MIPI0_FRAME_NUM_VC1 0x1A0
	420	+#define CSI_MIPI0_FRAME_NUM_VC2 0x1A4
	421	+#define CSI_MIPI0_FRAME_NUM_VC3 0x1A8
	422	+#define CSI_MIPI0_EFFECT_CODE_ID0 0x1AC
	423	+#define CSI_MIPI0_EFFECT_CODE_ID1 0x1B0
	424	+#define CSI_MIPI0_EFFECT_CODE_ID2 0x1B4
	425	+#define CSI_MIPI0_EFFECT_CODE_ID3 0x1B8
	426	+#define CSI_MIPI0_ON_PAD 0x1BC
	427	+
	428	+#define CSI_MIPI0_FRAME_SIZE_ID0 0x1C0
	429	+#define CSI_MIPI0_FRAME_SIZE_ID1 0x1C4
	430	+#define CSI_MIPI0_FRAME_SIZE_ID2 0x1C8
	431	+#define CSI_MIPI0_FRAME_SIZE_ID3 0x1CC
	432	+
	433	+/* RV1106 CONTROL Registers Offset */
	434	+#define CIF_LVDS0_ID0_CTRL0 0x1D0
	435	+#define CIF_LVDS0_ID1_CTRL0 0x1D4
	436	+#define CIF_LVDS0_ID2_CTRL0 0x1D8
	437	+#define CIF_LVDS0_ID3_CTRL0 0x1DC
	438	+#define CIF_LVDS_SAV_EAV_ACT0_ID0_RV1106 0x1E0
	439	+#define CIF_LVDS_SAV_EAV_BLK0_ID0_RV1106 0x1E4
	440	+#define CIF_LVDS_SAV_EAV_ACT1_ID0_RV1106 0x1E8
	441	+#define CIF_LVDS_SAV_EAV_BLK1_ID0_RV1106 0x1EC
	442	+#define CIF_LVDS_SAV_EAV_ACT0_ID1_RV1106 0x1F0
	443	+#define CIF_LVDS_SAV_EAV_BLK0_ID1_RV1106 0x1F4
	444	+#define CIF_LVDS_SAV_EAV_ACT1_ID1_RV1106 0x1F8
	445	+#define CIF_LVDS_SAV_EAV_BLK1_ID1_RV1106 0x1FC
	446	+#define CIF_LVDS_SAV_EAV_ACT0_ID2_RV1106 0x200
	447	+#define CIF_LVDS_SAV_EAV_BLK0_ID2_RV1106 0x204
	448	+#define CIF_LVDS_SAV_EAV_ACT1_ID2_RV1106 0x208
	449	+#define CIF_LVDS_SAV_EAV_BLK1_ID2_RV1106 0x20C
	450	+#define CIF_LVDS_SAV_EAV_ACT0_ID3_RV1106 0x210
	451	+#define CIF_LVDS_SAV_EAV_BLK0_ID3_RV1106 0x214
	452	+#define CIF_LVDS_SAV_EAV_ACT1_ID3_RV1106 0x218
	453	+#define CIF_LVDS_SAV_EAV_BLK1_ID3_RV1106 0x21C
	454	+
	455	+/* RK3588 CONTROL Registers Offset */
	456	+#define GLB_CTRL 0X000
	457	+#define GLB_INTEN 0X004
	458	+#define GLB_INTST 0X008
	459	+#define SCL_CH_CTRL 0x700
	460	+#define SCL_CTRL 0x704
	461	+#define SCL_FRM0_ADDR_CH0 0x708
	462	+#define SCL_FRM1_ADDR_CH0 0x70C
	463	+#define SCL_VLW_CH0 0x710
	464	+#define SCL_FRM0_ADDR_CH1 0x714
	465	+#define SCL_FRM1_ADDR_CH1 0x718
	466	+#define SCL_VLW_CH1 0x71C
	467	+#define SCL_FRM0_ADDR_CH2 0x720
	468	+#define SCL_FRM1_ADDR_CH2 0x724
	469	+#define SCL_VLW_CH2 0x728
	470	+#define SCL_FRM0_ADDR_CH3 0x72C
	471	+#define SCL_FRM1_ADDR_CH3 0x730
	472	+#define SCL_VLW_CH3 0x734
	473	+#define SCL_BLC_CH0 0x738
	474	+#define SCL_BLC_CH1 0x73C
	475	+#define SCL_BLC_CH2 0x740
	476	+#define SCL_BLC_CH3 0x744
	477	+#define TOISP0_CH_CTRL 0x780
	478	+#define TOISP0_CROP_SIZE 0x784
	479	+#define TOISP0_CROP 0x788
	480	+#define TOISP1_CH_CTRL 0x78C
	481	+#define TOISP1_CROP_SIZE 0x790
	482	+#define TOISP1_CROP 0x794
	483	+
301	484	/* The key register bit description */
302	485
303	486	/* CIF_CTRL Reg */
..	..	@@ -307,6 +490,13 @@
307	490	#define MODE_PINGPONG (0x1 << 1)
308	491	#define MODE_LINELOOP (0x2 << 1)
309	492	#define AXI_BURST_16 (0xF << 12)
	493	+#define DVP_PRESS_EN (0x1 << 12)
	494	+#define DVP_HURRY_EN (0x1 << 8)
	495	+#define DVP_DMA_EN (0x1 << 1)
	496	+#define DVP_SW_WATER_LINE_75 (0x0 << 5)
	497	+#define DVP_SW_WATER_LINE_50 (0x1 << 5)
	498	+#define DVP_SW_WATER_LINE_25 (0x2 << 5)
	499	+#define DVP_SW_WATER_LINE_00 (0x3 << 5)
310	500
311	501	/* CIF_INTEN */
312	502	#define INTEN_DISABLE (0x0 << 0)
..	..	@@ -335,7 +525,30 @@
335	525	#define PRE_INF_FRAME_END_CLR (0x01 << 8)
336	526	#define PST_INF_FRAME_END_CLR (0x01 << 9)
337	527	#define INTSTAT_ERR (0xFC)
	528	+#define INTSTAT_ERR_RK3588 (DVP_SIZE_ERR \|\
	529	+ DVP_FIFO_OVERFLOW \|\
	530	+ DVP_BANDWIDTH_LACK)
	531	+
338	532	#define DVP_ALL_OVERFLOW (IFIFO_OVERFLOW \| DFIFO_OVERFLOW)
	533	+
	534	+#define DVP_FIFO_OVERFLOW (0x01 << 16)
	535	+#define DVP_BANDWIDTH_LACK (0x01 << 17)
	536	+
	537	+#define DVP_SIZE_ERR_ID0 (0x1 << 22)
	538	+#define DVP_SIZE_ERR_ID1 (0x1 << 23)
	539	+#define DVP_SIZE_ERR_ID2 (0x1 << 24)
	540	+#define DVP_SIZE_ERR_ID3 (0x1 << 25)
	541	+
	542	+#define DVP_SIZE_ERR (DVP_SIZE_ERR_ID0 \|\
	543	+ DVP_SIZE_ERR_ID1 \|\
	544	+ DVP_SIZE_ERR_ID2 \|\
	545	+ DVP_SIZE_ERR_ID3)
	546	+
	547	+#define DVP_SW_PRESS_VALUE(val) (((val) & 0x7) << 13)
	548	+#define DVP_SW_HURRY_VALUE(val) (((val) & 0x7) << 9)
	549	+#define DVP_SW_CAP_EN(ID) (2 << ID)
	550	+#define DVP_SW_DMA_EN(ID) (0x100000 << ID)
	551	+#define DVP_START_INTSTAT(ID) (0x3 << ((ID) * 2))
339	552
340	553	#define DVP_DMA_END_INTEN(id) \
341	554	({ \
..	..	@@ -351,7 +564,7 @@
351	564	mask; \
352	565	})
353	566
354		-#define DVP_LINE_INTEN (0x01 << 10)
	567	+#define DVP_LINE_INTEN (0x01 << 10)
355	568
356	569	#define DVP_DMA_END_INTSTAT(id) \
357	570	({ \
..	..	@@ -367,8 +580,8 @@
367	580	mask; \
368	581	})
369	582
370		-#define DVP_PST_INTSTAT PST_INF_FRAME_END
371		-#define DVP_LINE_INTSTAT (0x01 << 10)
	583	+#define DVP_PST_INTSTAT PST_INF_FRAME_END
	584	+#define DVP_LINE_INTSTAT (0x01 << 10)
372	585
373	586	/* FRAME STATUS */
374	587	#define FRAME_STAT_CLS 0x00
..	..	@@ -433,6 +646,20 @@
433	646	#define BT656_1120_MULTI_ID_2_MASK ~(0x03 << 20)
434	647	#define BT656_1120_MULTI_ID_3_MASK ~(0x03 << 28)
435	648	#define CIF_HIGH_ALIGN (0x01 << 18)
	649	+#define CIF_HIGH_ALIGN_RK3588 (0x01 << 21)
	650	+#define BT656_DETECT_SAV (0X01 << 13)
	651	+#define BT656_DETECT_SAV_EAV (0X00 << 13)
	652	+
	653	+#define BT1120_CLOCK_SINGLE_EDGES_RK3588 (0x00 << 11)
	654	+#define BT1120_CLOCK_DOUBLE_EDGES_RK3588 (0x01 << 11)
	655	+#define TRANSMIT_INTERFACE_RK3588 (0x01 << 9)
	656	+#define TRANSMIT_PROGRESS_RK3588 (0x00 << 9)
	657	+#define BT1120_YC_SWAP_RK3588 (0x01 << 12)
	658	+#define INPUT_BT601_YUV422 (0x00 << 2)
	659	+#define INPUT_BT601_RAW (0x01 << 2)
	660	+#define INPUT_BT656_YUV422 (0x02 << 2)
	661	+#define INPUT_BT1120_YUV422 (0x03 << 2)
	662	+#define INPUT_SONY_RAW (0x04 << 2)
436	663
437	664	/* CIF_SCL_CTRL */
438	665	#define ENABLE_SCL_DOWN (0x01 << 0)
..	..	@@ -460,10 +687,32 @@
460	687	#define DVP_CHANNEL3_F1_READY (0x01 << 13)
461	688	#define DVP_CHANNEL3_FRM_READ (DVP_CHANNEL3_F0_READY \| DVP_CHANNEL3_F1_READY)
462	689
	690	+#define DVP_FRAME0_START_ID0 (0x1 << 0)
	691	+#define DVP_FRAME1_START_ID0 (0x1 << 1)
	692	+
463	693	#define DVP_FRAME_END_ID0 (0x1 << 0)
464	694	#define DVP_FRAME_END_ID1 (0x1 << 11)
465	695	#define DVP_FRAME_END_ID2 (0x1 << 12)
466	696	#define DVP_FRAME_END_ID3 (0x1 << 13)
	697	+
	698	+#define DVP_FRAME0_END_ID0 (0x1 << 8)
	699	+#define DVP_FRAME1_END_ID0 (0x1 << 9)
	700	+#define DVP_ALL_END_ID0 (DVP_FRAME0_END_ID0 \| DVP_FRAME1_END_ID0)
	701	+
	702	+#define DVP_FRAME0_END_ID1 (0x1 << 10)
	703	+#define DVP_FRAME1_END_ID1 (0x1 << 11)
	704	+#define DVP_ALL_END_ID1 (DVP_FRAME0_END_ID1 \| DVP_FRAME1_END_ID1)
	705	+
	706	+#define DVP_FRAME0_END_ID2 (0x1 << 12)
	707	+#define DVP_FRAME1_END_ID2 (0x1 << 13)
	708	+#define DVP_ALL_END_ID2 (DVP_FRAME0_END_ID2 \| DVP_FRAME1_END_ID2)
	709	+
	710	+#define DVP_FRAME0_END_ID3 (0x1 << 14)
	711	+#define DVP_FRAME1_END_ID3 (0x1 << 15)
	712	+#define DVP_ALL_END_ID3 (DVP_FRAME0_END_ID3 \| DVP_FRAME1_END_ID3)
	713	+
	714	+#define DVP_ALIGN_MSB (0x01 << 21)
	715	+#define DVP_ALIGN_LSB (0x00 << 21)
467	716
468	717	#define DVP_FRM_STS_ID0(x) (((x) & (0x3 << 0)) >> 0)
469	718	#define DVP_FRM_STS_ID1(x) (((x) & (0x3 << 4)) >> 4)
..	..	@@ -497,6 +746,28 @@
497	746	#define CIF_CROP_Y_SHIFT 16
498	747	#define CIF_CROP_X_SHIFT 0
499	748
	749	+/* CIF SCALE*/
	750	+#define SCALE_END_INTSTAT(ch) (0x3 << ((ch + 1) * 2))
	751	+#define SCALE_FIFO_OVERFLOW(ch) (1 << (10 + ch))
	752	+#define SCALE_TOISP_AXI0_ERR (1 << 0)
	753	+#define SCALE_TOISP_AXI1_ERR (1 << 1)
	754	+#define CIF_SCALE_SW_PRESS_VALUE(val) (((val) & 0x7) << 13)
	755	+#define CIF_SCALE_SW_PRESS_ENABLE (0x1 << 12)
	756	+#define CIF_SCALE_SW_HURRY_VALUE(val) (((val) & 0x7) << 5)
	757	+#define CIF_SCALE_SW_HURRY_ENABLE (0x1 << 4)
	758	+#define CIF_SCALE_SW_WATER_LINE(val) (val << 1)
	759	+#define CIF_SCALE_SW_SRC_CH(val, ch) ((val & 0x1f) << (3 + ch * 8))
	760	+#define CIF_SCALE_SW_MODE(val, ch) ((val & 0x3) << (1 + ch * 8))
	761	+#define CIF_SCALE_EN(ch) (1 << (ch * 8))
	762	+#define SW_SCALE_END(intstat, ch) ((intstat >> ((ch + 1) * 2)) & 0x3)
	763	+#define SCALE_SOFT_RESET(ch) (0x1 << (ch + 16))
	764	+
	765	+/* CIF TOISP*/
	766	+#define CIF_TOISP0_FS(ch) (BIT(14) << ch)
	767	+#define CIF_TOISP1_FS(ch) (BIT(17) << ch)
	768	+#define CIF_TOISP0_FE(ch) (BIT(20) << ch)
	769	+#define CIF_TOISP1_FE(ch) (BIT(23) << ch)
	770	+
500	771	/* CIF_CSI_ID_CTRL0 */
501	772	#define CSI_DISABLE_CAPTURE (0x0 << 0)
502	773	#define CSI_ENABLE_CAPTURE (0x1 << 0)
..	..	@@ -507,16 +778,43 @@
507	778	#define CSI_WRDDR_TYPE_YUV422 (0x4 << 1)
508	779	#define CSI_WRDDR_TYPE_YUV420SP (0x5 << 1)
509	780	#define CSI_WRDDR_TYPE_YUV400 (0x6 << 1)
	781	+#define CSI_WRDDR_TYPE_RGB565 (0x7 << 1)
510	782	#define CSI_DISABLE_COMMAND_MODE (0x0 << 4)
511	783	#define CSI_ENABLE_COMMAND_MODE (0x1 << 4)
512	784	#define CSI_DISABLE_CROP (0x0 << 5)
513	785	#define CSI_ENABLE_CROP (0x1 << 5)
	786	+#define CSI_DISABLE_CROP_V1 (0x0 << 4)
	787	+#define CSI_ENABLE_CROP_V1 (0x1 << 4)
514	788	#define CSI_ENABLE_MIPI_COMPACT (0x1 << 6)
515	789	#define CSI_YUV_INPUT_ORDER_UYVY (0x0 << 16)
516	790	#define CSI_YUV_INPUT_ORDER_VYUY (0x1 << 16)
517	791	#define CSI_YUV_INPUT_ORDER_YUYV (0x2 << 16)
518	792	#define CSI_YUV_INPUT_ORDER_YVYU (0x3 << 16)
519		-#define CSI_ENABLE_MIPI_HIGH_ALIGN (0x1 << 31)
	793	+#define CSI_HIGH_ALIGN (0x1 << 31)
	794	+#define CSI_HIGH_ALIGN_RK3588 (0x1 << 27)
	795	+
	796	+#define CSI_YUV_OUTPUT_ORDER_UYVY (0x0 << 18)
	797	+#define CSI_YUV_OUTPUT_ORDER_VYUY (0x1 << 18)
	798	+#define CSI_YUV_OUTPUT_ORDER_YUYV (0x2 << 18)
	799	+#define CSI_YUV_OUTPUT_ORDER_YVYU (0x3 << 18)
	800	+#define CSI_WRDDR_TYPE_RAW_COMPACT (0x0 << 5)
	801	+#define CSI_WRDDR_TYPE_RAW_UNCOMPACT (0x1 << 5)
	802	+#define CSI_WRDDR_TYPE_YUV_PACKET (0x2 << 5)
	803	+#define CSI_WRDDR_TYPE_YUV400_RK3588 (0x3 << 5)
	804	+#define CSI_WRDDR_TYPE_YUV422SP_RK3588 (0x4 << 5)
	805	+#define CSI_WRDDR_TYPE_YUV420SP_RK3588 (0x5 << 5)
	806	+#define CSI_ALIGN_MSB (0x01 << 27)
	807	+#define CSI_ALIGN_LSB (0x0 << 27)
	808	+#define CSI_DMA_ENABLE (0x1 << 28)
	809	+
	810	+#define CSI_NO_HDR (0X0 << 22)
	811	+#define CSI_HDR2 (0X1 << 22)
	812	+#define CSI_HDR3 (0X2 << 22)
	813	+
	814	+#define CSI_HDR_MODE_VC (0x0 << 20)
	815	+#define CSI_HDR_MODE_LINE_CNT (0x1 << 20)
	816	+#define CSI_HDR_MODE_LINE_INFO (0x2 << 20)
	817	+#define CSI_HDR_VC_MODE_PROTECT (0x1 << 29)
520	818
521	819	#define LVDS_ENABLE_CAPTURE (0x1 << 16)
522	820	#define LVDS_MODE(mode) (((mode) & 0x7) << 17)
..	..	@@ -549,6 +847,37 @@
549	847	#define LVDS_HDR_FRAME_X3 (0x1 << 28)
550	848	#define LVDS_COMPACT (0x1 << 29)
551	849
	850	+#define LVDS_ENABLE_CAPTURE_RV1106 (0x1 << 0)
	851	+#define LVDS_MODE_RV1106(mode) (((mode) & 0x7) << 1)
	852	+#define LVDS_LANES_ENABLED_RV1106(lanes) \
	853	+ ({ \
	854	+ unsigned int mask; \
	855	+ switch (lanes) { \
	856	+ case 1: \
	857	+ mask = 0x1 << 4; \
	858	+ break; \
	859	+ case 2: \
	860	+ mask = 0x3 << 4; \
	861	+ break; \
	862	+ case 3: \
	863	+ mask = 0x7 << 4; \
	864	+ break; \
	865	+ case 4: \
	866	+ mask = 0xf << 4; \
	867	+ break; \
	868	+ default: \
	869	+ mask = 0x1 << 4; \
	870	+ break; \
	871	+ } \
	872	+ mask; \
	873	+ })
	874	+
	875	+#define LVDS_MAIN_LANE_RV1106(index) (((index) & 0x3) << 8)
	876	+#define LVDS_FID_RV1106(id) (((id) & 0x3) << 10)
	877	+#define LVDS_HDR_FRAME_X2_RV1106 (0x0 << 12)
	878	+#define LVDS_HDR_FRAME_X3_RV1106 (0x1 << 12)
	879	+#define LVDS_DMAEN_RV1106 (0x1 << 15)
	880	+
552	881	/* CIF_CSI_INTEN */
553	882	#define CSI_FRAME1_START_INTEN(id) (0x1 << ((id) * 2 + 1))
554	883	#define CSI_FRAME0_END_INTEN(id) (0x1 << ((id) * 2 + 8))
..	..	@@ -561,14 +890,17 @@
561	890	#define CSI_ALL_FRAME_START_INTEN (0xff << 0)
562	891	#define CSI_ALL_FRAME_END_INTEN (0xff << 8)
563	892	#define CSI_ALL_ERROR_INTEN (0x1f << 16)
	893	+#define CSI_ALL_ERROR_INTEN_V1 (0xf0f << 16)
564	894
565	895	#define CSI_START_INTEN(id) (0x3 << ((id) * 2))
566	896	#define CSI_DMA_END_INTEN(id) (0x3 << ((id) * 2 + 8))
567	897	#define CSI_LINE_INTEN(id) (0x1 << ((id) + 21))
	898	+#define CSI_LINE_INTEN_RK3588(id) (0x1 << ((id) + 20))
568	899
569	900	#define CSI_START_INTSTAT(id) (0x3 << ((id) * 2))
570	901	#define CSI_DMA_END_INTSTAT(id) (0x3 << ((id) * 2 + 8))
571	902	#define CSI_LINE_INTSTAT(id) (0x1 << ((id) + 21))
	903	+#define CSI_LINE_INTSTAT_V1(id) (0x1 << ((id) + 20))
572	904
573	905	/* CIF_CSI_INTSTAT */
574	906	#define CSI_FRAME0_START_ID0 (0x1 << 0)
..	..	@@ -598,51 +930,73 @@
598	930	#define CSI_LINE_ID3_INTST (0x1 << 24)
599	931	#define CSI_DMA_LVDS_ID2_FIFO_OVERFLOW (0x1 << 25)
600	932	#define CSI_DMA_LVDS_ID3_FIFO_OVERFLOW (0x1 << 26)
	933	+#define CSI_SIZE_ERR_ID0 (0x1 << 24)
	934	+#define CSI_SIZE_ERR_ID1 (0x1 << 25)
	935	+#define CSI_SIZE_ERR_ID2 (0x1 << 26)
	936	+#define CSI_SIZE_ERR_ID3 (0x1 << 27)
601	937
602		-#define CSI_FRAME_START_ID0 (CSI_FRAME0_START_ID0 \|\
603		- CSI_FRAME1_START_ID0)
604		-#define CSI_FRAME_START_ID1 (CSI_FRAME0_START_ID1 \|\
605		- CSI_FRAME1_START_ID1)
606		-#define CSI_FRAME_START_ID2 (CSI_FRAME0_START_ID2 \|\
607		- CSI_FRAME1_START_ID2)
608		-#define CSI_FRAME_START_ID3 (CSI_FRAME0_START_ID3 \|\
609		- CSI_FRAME1_START_ID3)
610		-#define CSI_FRAME_END_ID0 (CSI_FRAME0_END_ID0 \|\
611		- CSI_FRAME1_END_ID0)
612		-#define CSI_FRAME_END_ID1 (CSI_FRAME0_END_ID1 \|\
613		- CSI_FRAME1_END_ID1)
614		-#define CSI_FRAME_END_ID2 (CSI_FRAME0_END_ID2 \|\
615		- CSI_FRAME1_END_ID2)
616		-#define CSI_FRAME_END_ID3 (CSI_FRAME0_END_ID3 \|\
617		- CSI_FRAME1_END_ID3)
618		-#define CSI_FIFO_OVERFLOW (CSI_DMA_Y_FIFO_OVERFLOW \| \
619		- CSI_DMA_UV_FIFO_OVERFLOW \| \
620		- CSI_CONFIG_FIFO_OVERFLOW \| \
621		- CSI_RX_FIFO_OVERFLOW \| \
622		- CSI_DMA_LVDS_ID2_FIFO_OVERFLOW \| \
623		- CSI_DMA_LVDS_ID3_FIFO_OVERFLOW)
	938	+#define CSI_FRAME_START_ID0 (CSI_FRAME0_START_ID0 \|\
	939	+ CSI_FRAME1_START_ID0)
	940	+#define CSI_FRAME_START_ID1 (CSI_FRAME0_START_ID1 \|\
	941	+ CSI_FRAME1_START_ID1)
	942	+#define CSI_FRAME_START_ID2 (CSI_FRAME0_START_ID2 \|\
	943	+ CSI_FRAME1_START_ID2)
	944	+#define CSI_FRAME_START_ID3 (CSI_FRAME0_START_ID3 \|\
	945	+ CSI_FRAME1_START_ID3)
	946	+#define CSI_FRAME_END_ID0 (CSI_FRAME0_END_ID0 \|\
	947	+ CSI_FRAME1_END_ID0)
	948	+#define CSI_FRAME_END_ID1 (CSI_FRAME0_END_ID1 \|\
	949	+ CSI_FRAME1_END_ID1)
	950	+#define CSI_FRAME_END_ID2 (CSI_FRAME0_END_ID2 \|\
	951	+ CSI_FRAME1_END_ID2)
	952	+#define CSI_FRAME_END_ID3 (CSI_FRAME0_END_ID3 \|\
	953	+ CSI_FRAME1_END_ID3)
	954	+#define CSI_FIFO_OVERFLOW (CSI_DMA_Y_FIFO_OVERFLOW \|\
	955	+ CSI_DMA_UV_FIFO_OVERFLOW \|\
	956	+ CSI_CONFIG_FIFO_OVERFLOW \|\
	957	+ CSI_RX_FIFO_OVERFLOW \|\
	958	+ CSI_DMA_LVDS_ID2_FIFO_OVERFLOW \|\
	959	+ CSI_DMA_LVDS_ID3_FIFO_OVERFLOW)
	960	+
	961	+/mask for rk3588/
	962	+#define CSI_RX_FIFO_OVERFLOW_V1 (0x1 << 19)
	963	+#define CSI_BANDWIDTH_LACK_V1 (0x1 << 18)
	964	+#define CSI_ALL_ERROR_INTEN_V1 (0xf0f << 16)
	965	+
	966	+
	967	+#define CSI_FIFO_OVERFLOW_V1 (CSI_DMA_Y_FIFO_OVERFLOW \|\
	968	+ CSI_DMA_UV_FIFO_OVERFLOW \|\
	969	+ CSI_RX_FIFO_OVERFLOW_V1)
	970	+#define CSI_SIZE_ERR (CSI_SIZE_ERR_ID0 \|\
	971	+ CSI_SIZE_ERR_ID1 \|\
	972	+ CSI_SIZE_ERR_ID2 \|\
	973	+ CSI_SIZE_ERR_ID3)
	974	+
624	975	/* CIF_MIPI_LVDS_CTRL */
625		-#define CIF_MIPI_LVDS_SW_DMA_IDLE (0x1 << 16)
626		-#define CIF_MIPI_LVDS_SW_PRESS_VALUE(val) (((val) & 0x3) << 13)
627		-#define CIF_MIPI_LVDS_SW_PRESS_ENABLE (0x1 << 12)
628		-#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_8BITS (0x0 << 9)
629		-#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_10BITS (0x1 << 9)
630		-#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS (0x2 << 9)
631		-#define CIF_MIPI_LVDS_SW_SEL_LVDS (0x1 << 8)
632		-#define CIF_MIPI_LVDS_SW_HURRY_VALUE(val) (((val) & 0x3) << 5)
633		-#define CIF_MIPI_LVDS_SW_HURRY_ENABLE (0x1 << 4)
634		-#define CIF_MIPI_LVDS_SW_WATER_LINE_75 (0x0 << 1)
635		-#define CIF_MIPI_LVDS_SW_WATER_LINE_50 (0x1 << 1)
636		-#define CIF_MIPI_LVDS_SW_WATER_LINE_25 (0x2 << 1)
637		-#define CIF_MIPI_LVDS_SW_WATER_LINE_00 (0x3 << 1)
638		-#define CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE (0x1 << 0)
639		-#define CIF_MIPI_LVDS_SW_DMA_IDLE_RK1808 (0x1 << 24)
	976	+#define CIF_MIPI_LVDS_SW_DMA_IDLE (0x1 << 16)
	977	+#define CIF_MIPI_LVDS_SW_PRESS_VALUE(val) (((val) & 0x3) << 13)
	978	+#define CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(val) (((val) & 0x7) << 13)
	979	+#define CIF_MIPI_LVDS_SW_PRESS_ENABLE (0x1 << 12)
	980	+#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_8BITS (0x0 << 9)
	981	+#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_10BITS (0x1 << 9)
	982	+#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS (0x2 << 9)
	983	+#define CIF_MIPI_LVDS_SW_SEL_LVDS (0x1 << 8)
	984	+#define CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106 (0x1 << 3)
	985	+#define CIF_MIPI_LVDS_SW_HURRY_VALUE(val) (((val) & 0x3) << 5)
	986	+#define CIF_MIPI_LVDS_SW_HURRY_VALUE_RK3588(val) (((val) & 0x7) << 5)
	987	+#define CIF_MIPI_LVDS_SW_HURRY_ENABLE (0x1 << 4)
	988	+#define CIF_MIPI_LVDS_SW_WATER_LINE_75 (0x0 << 1)
	989	+#define CIF_MIPI_LVDS_SW_WATER_LINE_50 (0x1 << 1)
	990	+#define CIF_MIPI_LVDS_SW_WATER_LINE_25 (0x2 << 1)
	991	+#define CIF_MIPI_LVDS_SW_WATER_LINE_00 (0x3 << 1)
	992	+#define CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE (0x1 << 0)
	993	+#define CIF_MIPI_LVDS_SW_DMA_IDLE_RK1808 (0x1 << 24)
640	994	#define CIF_MIPI_LVDS_SW_HURRY_VALUE_RK1808(val) (((val) & 0x3) << 17)
641		-#define CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808 (0x1 << 16)
642		-#define CIF_MIPI_LVDS_SW_WATER_LINE_75_RK1808 (0x0 << 0)
643		-#define CIF_MIPI_LVDS_SW_WATER_LINE_50_RK1808 (0x1 << 0)
644		-#define CIF_MIPI_LVDS_SW_WATER_LINE_25_RK1808 (0x2 << 0)
645		-#define CIF_MIPI_LVDS_SW_WATER_LINE_00_RK1808 (0x3 << 0)
	995	+#define CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808 (0x1 << 16)
	996	+#define CIF_MIPI_LVDS_SW_WATER_LINE_75_RK1808 (0x0 << 0)
	997	+#define CIF_MIPI_LVDS_SW_WATER_LINE_50_RK1808 (0x1 << 0)
	998	+#define CIF_MIPI_LVDS_SW_WATER_LINE_25_RK1808 (0x2 << 0)
	999	+#define CIF_MIPI_LVDS_SW_WATER_LINE_00_RK1808 (0x3 << 0)
646	1000	#define CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE_RK1808 (0x1 << 4)
647	1001
648	1002	/* CSI Host Registers Define */
..	..	@@ -667,6 +1021,11 @@
667	1021	#define SW_FRM_END_ID2(x) (((x) & CSI_FRAME_END_ID2) >> 12)
668	1022	#define SW_FRM_END_ID3(x) (((x) & CSI_FRAME_END_ID3) >> 14)
669	1023
	1024	+/RV1106 SKIP FUNC/
	1025	+#define RKCIF_CAP_SHIFT 0x18
	1026	+#define RKCIF_SKIP_SHIFT 0X15
	1027	+#define RKCIF_SKIP_EN(x) (0x1 << (8 + x))
	1028	+
670	1029	/* CIF LVDS SAV EAV Define */
671	1030	#define SW_LVDS_EAV_ACT(code) (((code) & 0xfff) << 16)
672	1031	#define SW_LVDS_SAV_ACT(code) (((code) & 0xfff) << 0)
..	..	@@ -688,5 +1047,29 @@
688	1047	#define RK3568_CIF_PCLK_SAMPLING_EDGE_FALLING (0x10001000)
689	1048	#define RK3568_CIF_PCLK_SINGLE_EDGE (0x02000000)
690	1049	#define RK3568_CIF_PCLK_DUAL_EDGE (0x02000200)
	1050	+#define CIF_GRF_SOC_CON2 (0x308)
	1051	+#define RK3588_CIF_PCLK_SAMPLING_EDGE_RISING (0x00100000)
	1052	+#define RK3588_CIF_PCLK_SAMPLING_EDGE_FALLING (0x00100010)
	1053	+#define RK3588_CIF_PCLK_SINGLE_EDGE (0x00200000)
	1054	+#define RK3588_CIF_PCLK_DUAL_EDGE (0x00200020)
	1055	+#define RV1106_CIF_GRF_VI_CON (0x50038)
	1056	+#define RV1106_CIF_GRF_VENC_WRAPPER (0x10008)
	1057	+#define RV1106_CIF_PCLK_SINGLE_EDGE (0x00040000)
	1058	+#define RV1106_CIF_PCLK_DUAL_EDGE (0x00040004)
	1059	+#define RV1106_CIF_PCLK_EDGE_RISING_M0 (0x00020002)
	1060	+#define RV1106_CIF_PCLK_EDGE_FALLING_M0 (0x00020000)
	1061	+#define RV1106_CIF_PCLK_EDGE_RISING_M1 (0x00010001)
	1062	+#define RV1106_CIF_PCLK_EDGE_FALLING_M1 (0x00010000)
	1063	+#define RV1106_CIF_GRF_SEL_M0 (0x00010000)
	1064	+#define RV1106_CIF_GRF_SEL_M1 (0x00010001)
	1065	+
	1066	+/toisp/
	1067	+#define TOISP_FS_CH0(index) (0x1 << (14 + index * 3))
	1068	+#define TOISP_FS_CH1(index) (0x1 << (15 + index * 3))
	1069	+#define TOISP_FS_CH2(index) (0x1 << (16 + index * 3))
	1070	+
	1071	+#define TOISP_END_CH0(index) (0x1 << (20 + index * 3))
	1072	+#define TOISP_END_CH1(index) (0x1 << (21 + index * 3))
	1073	+#define TOISP_END_CH2(index) (0x1 << (22 + index * 3))
691	1074
692	1075	#endif