| .. | .. |
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| 145 | 145 | CIF_REG_LVDS_ID1_CTRL0, |
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| 146 | 146 | CIF_REG_LVDS_ID2_CTRL0, |
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| 147 | 147 | CIF_REG_LVDS_ID3_CTRL0, |
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| 148 | + CIF_REG_MIPI_FRAME_SIZE_ID0, |
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| 149 | + CIF_REG_MIPI_FRAME_SIZE_ID1, |
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| 150 | + CIF_REG_MIPI_FRAME_SIZE_ID2, |
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| 151 | + CIF_REG_MIPI_FRAME_SIZE_ID3, |
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| 148 | 152 | CIF_REG_MIPI_ON_PAD, |
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| 149 | 153 | |
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| 150 | 154 | CIF_REG_Y_STAT_CONTROL, |
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| .. | .. |
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| 421 | 425 | #define CSI_MIPI0_EFFECT_CODE_ID3 0x1B8 |
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| 422 | 426 | #define CSI_MIPI0_ON_PAD 0x1BC |
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| 423 | 427 | |
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| 428 | +#define CSI_MIPI0_FRAME_SIZE_ID0 0x1C0 |
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| 429 | +#define CSI_MIPI0_FRAME_SIZE_ID1 0x1C4 |
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| 430 | +#define CSI_MIPI0_FRAME_SIZE_ID2 0x1C8 |
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| 431 | +#define CSI_MIPI0_FRAME_SIZE_ID3 0x1CC |
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| 432 | + |
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| 424 | 433 | /* RV1106 CONTROL Registers Offset */ |
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| 425 | 434 | #define CIF_LVDS0_ID0_CTRL0 0x1D0 |
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| 426 | 435 | #define CIF_LVDS0_ID1_CTRL0 0x1D4 |
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