~hc/RK356X_SDK_RELEASE.git

..	..	@@ -18,12 +18,15 @@
18	18	#include <media/videobuf2-dma-contig.h>
19	19	#include <media/videobuf2-dma-sg.h>
20	20	#include <soc/rockchip/rockchip-system-status.h>
21		-#include <dt-bindings/soc/rockchip-system-status.h>
	21	+#include <soc/rockchip/rockchip_iommu.h>
	22	+#include <linux/rk-isp32-config.h>
22	23
23	24	#include "dev.h"
24	25	#include "mipi-csi2.h"
	26	+#include "common.h"
	27	+#include "rkcif-externel.h"
25	28
26		-#define CIF_REQ_BUFS_MIN 3
	29	+#define CIF_REQ_BUFS_MIN 1
27	30	#define CIF_MIN_WIDTH 64
28	31	#define CIF_MIN_HEIGHT 64
29	32	#define CIF_MAX_WIDTH 8192
..	..	@@ -33,6 +36,7 @@
33	36
34	37	#define RKCIF_PLANE_Y 0
35	38	#define RKCIF_PLANE_CBCR 1
	39	+#define RKCIF_MAX_PLANE 3
36	40
37	41	#define STREAM_PAD_SINK 0
38	42	#define STREAM_PAD_SOURCE 1
..	..	@@ -146,10 +150,18 @@
146	150	.csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
147	151	.fmt_type = CIF_FMT_TYPE_RAW,
148	152	}, {
	153	+ .fourcc = V4L2_PIX_FMT_BGR24,
	154	+ .cplanes = 1,
	155	+ .mplanes = 1,
	156	+ .bpp = { 24 },
	157	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
	158	+ .fmt_type = CIF_FMT_TYPE_RAW,
	159	+ }, {
149	160	.fourcc = V4L2_PIX_FMT_RGB565,
150	161	.cplanes = 1,
151	162	.mplanes = 1,
152	163	.bpp = { 16 },
	164	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB565,
153	165	.fmt_type = CIF_FMT_TYPE_RAW,
154	166	}, {
155	167	.fourcc = V4L2_PIX_FMT_BGR666,
..	..	@@ -262,6 +274,30 @@
262	274	.csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
263	275	.fmt_type = CIF_FMT_TYPE_RAW,
264	276	}, {
	277	+ .fourcc = V4L2_PIX_FMT_SGBRG16,
	278	+ .cplanes = 1,
	279	+ .mplanes = 1,
	280	+ .bpp = { 16 },
	281	+ .raw_bpp = 16,
	282	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
	283	+ .fmt_type = CIF_FMT_TYPE_RAW,
	284	+ }, {
	285	+ .fourcc = V4L2_PIX_FMT_SGRBG16,
	286	+ .cplanes = 1,
	287	+ .mplanes = 1,
	288	+ .bpp = { 16 },
	289	+ .raw_bpp = 16,
	290	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
	291	+ .fmt_type = CIF_FMT_TYPE_RAW,
	292	+ }, {
	293	+ .fourcc = V4L2_PIX_FMT_SRGGB16,
	294	+ .cplanes = 1,
	295	+ .mplanes = 1,
	296	+ .bpp = { 16 },
	297	+ .raw_bpp = 16,
	298	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
	299	+ .fmt_type = CIF_FMT_TYPE_RAW,
	300	+ }, {
265	301	.fourcc = V4L2_PIX_FMT_Y16,
266	302	.cplanes = 1,
267	303	.mplanes = 1,
..	..	@@ -293,8 +329,51 @@
293	329	.raw_bpp = 16,
294	330	.csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
295	331	.fmt_type = CIF_FMT_TYPE_RAW,
	332	+ }, {
	333	+ .fourcc = V4L2_PIX_FMT_Y12,
	334	+ .cplanes = 1,
	335	+ .mplanes = 1,
	336	+ .bpp = { 16 },
	337	+ .raw_bpp = 12,
	338	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
	339	+ .fmt_type = CIF_FMT_TYPE_RAW,
	340	+ }, {
	341	+ .fourcc = V4L2_PIX_FMT_Y10,
	342	+ .cplanes = 1,
	343	+ .mplanes = 1,
	344	+ .bpp = { 16 },
	345	+ .raw_bpp = 10,
	346	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
	347	+ .fmt_type = CIF_FMT_TYPE_RAW,
	348	+ }, {
	349	+ .fourcc = V4L2_PIX_FMT_SRGGB16,
	350	+ .cplanes = 1,
	351	+ .mplanes = 1,
	352	+ .bpp = { 16 },
	353	+ .raw_bpp = 16,
	354	+ .fmt_type = CIF_FMT_TYPE_RAW,
	355	+ }, {
	356	+ .fourcc = V4L2_PIX_FMT_SGRBG16,
	357	+ .cplanes = 1,
	358	+ .mplanes = 1,
	359	+ .bpp = { 16 },
	360	+ .raw_bpp = 16,
	361	+ .fmt_type = CIF_FMT_TYPE_RAW,
	362	+ }, {
	363	+ .fourcc = V4L2_PIX_FMT_SGBRG16,
	364	+ .cplanes = 1,
	365	+ .mplanes = 1,
	366	+ .bpp = { 16 },
	367	+ .raw_bpp = 16,
	368	+ .fmt_type = CIF_FMT_TYPE_RAW,
	369	+ }, {
	370	+ .fourcc = V4L2_PIX_FMT_SBGGR16,
	371	+ .cplanes = 1,
	372	+ .mplanes = 1,
	373	+ .bpp = { 16 },
	374	+ .raw_bpp = 16,
	375	+ .fmt_type = CIF_FMT_TYPE_RAW,
296	376	}
297		-
298	377	/* TODO: We can support NV12M/NV21M/NV16M/NV61M too */
299	378	};
300	379
..	..	@@ -432,6 +511,18 @@
432	511	.csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
433	512	.field = V4L2_FIELD_NONE,
434	513	}, {
	514	+ .mbus_code = MEDIA_BUS_FMT_BGR888_1X24,
	515	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
	516	+ .field = V4L2_FIELD_NONE,
	517	+ }, {
	518	+ .mbus_code = MEDIA_BUS_FMT_GBR888_1X24,
	519	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
	520	+ .field = V4L2_FIELD_NONE,
	521	+ }, {
	522	+ .mbus_code = MEDIA_BUS_FMT_RGB565_1X16,
	523	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB565,
	524	+ .field = V4L2_FIELD_NONE,
	525	+ }, {
435	526	.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
436	527	.dvp_fmt_val = INPUT_MODE_RAW \| RAW_DATA_WIDTH_8,
437	528	.csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
..	..	@@ -463,6 +554,144 @@
463	554	.field = V4L2_FIELD_NONE,
464	555	}
465	556	};
	557	+
	558	+static int rkcif_output_fmt_check(struct rkcif_stream *stream,
	559	+ const struct cif_output_fmt *output_fmt)
	560	+{
	561	+ const struct cif_input_fmt *input_fmt = stream->cif_fmt_in;
	562	+ struct csi_channel_info *channel = &stream->cifdev->channels[stream->id];
	563	+ int ret = -EINVAL;
	564	+
	565	+ switch (input_fmt->mbus_code) {
	566	+ case MEDIA_BUS_FMT_YUYV8_2X8:
	567	+ case MEDIA_BUS_FMT_YVYU8_2X8:
	568	+ case MEDIA_BUS_FMT_UYVY8_2X8:
	569	+ case MEDIA_BUS_FMT_VYUY8_2X8:
	570	+ if (output_fmt->fourcc == V4L2_PIX_FMT_NV16 \|\|
	571	+ output_fmt->fourcc == V4L2_PIX_FMT_NV61 \|\|
	572	+ output_fmt->fourcc == V4L2_PIX_FMT_NV12 \|\|
	573	+ output_fmt->fourcc == V4L2_PIX_FMT_NV21 \|\|
	574	+ output_fmt->fourcc == V4L2_PIX_FMT_YUYV \|\|
	575	+ output_fmt->fourcc == V4L2_PIX_FMT_YVYU \|\|
	576	+ output_fmt->fourcc == V4L2_PIX_FMT_UYVY \|\|
	577	+ output_fmt->fourcc == V4L2_PIX_FMT_VYUY)
	578	+ ret = 0;
	579	+ break;
	580	+ case MEDIA_BUS_FMT_SBGGR8_1X8:
	581	+ case MEDIA_BUS_FMT_SGBRG8_1X8:
	582	+ case MEDIA_BUS_FMT_SGRBG8_1X8:
	583	+ case MEDIA_BUS_FMT_SRGGB8_1X8:
	584	+ case MEDIA_BUS_FMT_Y8_1X8:
	585	+ if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
	586	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
	587	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
	588	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8 \|\|
	589	+ output_fmt->fourcc == V4L2_PIX_FMT_GREY)
	590	+ ret = 0;
	591	+ break;
	592	+ case MEDIA_BUS_FMT_SBGGR10_1X10:
	593	+ case MEDIA_BUS_FMT_SGBRG10_1X10:
	594	+ case MEDIA_BUS_FMT_SGRBG10_1X10:
	595	+ case MEDIA_BUS_FMT_SRGGB10_1X10:
	596	+ case MEDIA_BUS_FMT_Y10_1X10:
	597	+ if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 \|\|
	598	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 \|\|
	599	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 \|\|
	600	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10 \|\|
	601	+ output_fmt->fourcc == V4L2_PIX_FMT_Y10)
	602	+ ret = 0;
	603	+ break;
	604	+ case MEDIA_BUS_FMT_SBGGR12_1X12:
	605	+ case MEDIA_BUS_FMT_SGBRG12_1X12:
	606	+ case MEDIA_BUS_FMT_SGRBG12_1X12:
	607	+ case MEDIA_BUS_FMT_SRGGB12_1X12:
	608	+ case MEDIA_BUS_FMT_Y12_1X12:
	609	+ if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 \|\|
	610	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 \|\|
	611	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 \|\|
	612	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12 \|\|
	613	+ output_fmt->fourcc == V4L2_PIX_FMT_Y12)
	614	+ ret = 0;
	615	+ break;
	616	+ case MEDIA_BUS_FMT_RGB888_1X24:
	617	+ case MEDIA_BUS_FMT_BGR888_1X24:
	618	+ case MEDIA_BUS_FMT_GBR888_1X24:
	619	+ if (output_fmt->fourcc == V4L2_PIX_FMT_RGB24 \|\|
	620	+ output_fmt->fourcc == V4L2_PIX_FMT_BGR24)
	621	+ ret = 0;
	622	+ break;
	623	+ case MEDIA_BUS_FMT_RGB565_1X16:
	624	+ if (output_fmt->fourcc == V4L2_PIX_FMT_RGB565)
	625	+ ret = 0;
	626	+ break;
	627	+ case MEDIA_BUS_FMT_EBD_1X8:
	628	+ if (output_fmt->fourcc == V4l2_PIX_FMT_EBD8 \|\|
	629	+ (channel->data_bit == 8 &&
	630	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
	631	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
	632	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
	633	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8)) \|\|
	634	+ (channel->data_bit == 10 &&
	635	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 \|\|
	636	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 \|\|
	637	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 \|\|
	638	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10)) \|\|
	639	+ (channel->data_bit == 12 &&
	640	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 \|\|
	641	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 \|\|
	642	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 \|\|
	643	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12)) \|\|
	644	+ (channel->data_bit == 16 &&
	645	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB16 \|\|
	646	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG16 \|\|
	647	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG16 \|\|
	648	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR16)))
	649	+ ret = 0;
	650	+ break;
	651	+ case MEDIA_BUS_FMT_SPD_2X8:
	652	+ if (output_fmt->fourcc == V4l2_PIX_FMT_SPD16 \|\|
	653	+ (channel->data_bit == 8 &&
	654	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
	655	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
	656	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
	657	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8)) \|\|
	658	+ (channel->data_bit == 10 &&
	659	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 \|\|
	660	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 \|\|
	661	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 \|\|
	662	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10)) \|\|
	663	+ (channel->data_bit == 12 &&
	664	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 \|\|
	665	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 \|\|
	666	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 \|\|
	667	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12)) \|\|
	668	+ (channel->data_bit == 16 &&
	669	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB16 \|\|
	670	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG16 \|\|
	671	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG16 \|\|
	672	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR16)))
	673	+ ret = 0;
	674	+ break;
	675	+ default:
	676	+ break;
	677	+ }
	678	+ if (ret)
	679	+ v4l2_dbg(4, rkcif_debug, &stream->cifdev->v4l2_dev,
	680	+ "input mbus_code 0x%x, can't transform to %c%c%c%c\n",
	681	+ input_fmt->mbus_code,
	682	+ output_fmt->fourcc & 0xff,
	683	+ (output_fmt->fourcc >> 8) & 0xff,
	684	+ (output_fmt->fourcc >> 16) & 0xff,
	685	+ (output_fmt->fourcc >> 24) & 0xff);
	686	+ return ret;
	687	+}
	688	+
	689	+static int rkcif_stop_dma_capture(struct rkcif_stream *stream);
	690	+
	691	+struct rkcif_rx_buffer to_cif_rx_buf(struct rkisp_rx_buf dbufs)
	692	+{
	693	+ return container_of(dbufs, struct rkcif_rx_buffer, dbufs);
	694	+}
466	695
467	696	static struct v4l2_subdev get_remote_sensor(struct rkcif_stream stream, u16 *index)
468	697	{
..	..	@@ -553,18 +782,21 @@
553	782	case MEDIA_BUS_FMT_SGBRG8_1X8:
554	783	case MEDIA_BUS_FMT_SGRBG8_1X8:
555	784	case MEDIA_BUS_FMT_SRGGB8_1X8:
	785	+ case MEDIA_BUS_FMT_Y8_1X8:
556	786	return 0x2a;
557	787	/* csi raw10 */
558	788	case MEDIA_BUS_FMT_SBGGR10_1X10:
559	789	case MEDIA_BUS_FMT_SGBRG10_1X10:
560	790	case MEDIA_BUS_FMT_SGRBG10_1X10:
561	791	case MEDIA_BUS_FMT_SRGGB10_1X10:
	792	+ case MEDIA_BUS_FMT_Y10_1X10:
562	793	return 0x2b;
563	794	/* csi raw12 */
564	795	case MEDIA_BUS_FMT_SBGGR12_1X12:
565	796	case MEDIA_BUS_FMT_SGBRG12_1X12:
566	797	case MEDIA_BUS_FMT_SGRBG12_1X12:
567	798	case MEDIA_BUS_FMT_SRGGB12_1X12:
	799	+ case MEDIA_BUS_FMT_Y12_1X12:
568	800	return 0x2c;
569	801	/* csi uyvy 422 */
570	802	case MEDIA_BUS_FMT_UYVY8_2X8:
..	..	@@ -572,7 +804,9 @@
572	804	case MEDIA_BUS_FMT_YUYV8_2X8:
573	805	case MEDIA_BUS_FMT_YVYU8_2X8:
574	806	return 0x1e;
575		- case MEDIA_BUS_FMT_RGB888_1X24: {
	807	+ case MEDIA_BUS_FMT_RGB888_1X24:
	808	+ case MEDIA_BUS_FMT_BGR888_1X24:
	809	+ case MEDIA_BUS_FMT_GBR888_1X24:
576	810	if (dsi_input) {
577	811	if (cmd_mode_en) /* dsi command mode*/
578	812	return 0x39;
..	..	@@ -581,7 +815,15 @@
581	815	} else {
582	816	return 0x24;
583	817	}
584		- }
	818	+ case MEDIA_BUS_FMT_RGB565_1X16:
	819	+ if (dsi_input) {
	820	+ if (cmd_mode_en) /* dsi command mode*/
	821	+ return 0x39;
	822	+ else /* dsi video mode */
	823	+ return 0x0e;
	824	+ } else {
	825	+ return 0x22;
	826	+ }
585	827	case MEDIA_BUS_FMT_EBD_1X8:
586	828	return 0x12;
587	829	case MEDIA_BUS_FMT_SPD_2X8:
..	..	@@ -597,6 +839,8 @@
597	839	switch (fmt_in->csi_fmt_val) {
598	840	case CSI_WRDDR_TYPE_RGB888:
599	841	return 24;
	842	+ case CSI_WRDDR_TYPE_RGB565:
	843	+ return 16;
600	844	case CSI_WRDDR_TYPE_RAW10:
601	845	case CSI_WRDDR_TYPE_RAW12:
602	846	return 4;
..	..	@@ -608,51 +852,61 @@
608	852	}
609	853	}
610	854
611		-static const struct
612		-cif_input_fmt get_input_fmt(struct v4l2_subdev sd, struct v4l2_rect *rect,
613		- u32 pad, int *vc)
	855	+const struct
	856	+cif_input_fmt rkcif_get_input_fmt(struct rkcif_device dev, struct v4l2_rect *rect,
	857	+ u32 pad_id, struct csi_channel_info *csi_info)
614	858	{
615	859	struct v4l2_subdev_format fmt;
	860	+ struct v4l2_subdev *sd = dev->terminal_sensor.sd;
	861	+ struct rkmodule_channel_info ch_info = {0};
	862	+ struct rkmodule_capture_info capture_info;
616	863	int ret;
617	864	u32 i;
618		- struct rkmodule_vc_fmt_info vc_info = {0};
619	865
620		- ret = v4l2_subdev_call(sd,
621		- core, ioctl,
622		- RKMODULE_GET_VC_FMT_INFO,
623		- &vc_info);
624		- if (ret < 0)
625		- v4l2_warn(sd->v4l2_dev,
626		- "get sensor vc info failed, maybe not support\n");
627		-
628		- fmt.pad = pad;
	866	+ fmt.pad = 0;
629	867	fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
630	868	fmt.reserved[0] = 0;
	869	+ fmt.format.field = V4L2_FIELD_NONE;
631	870	ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
632	871	if (ret < 0) {
633	872	v4l2_warn(sd->v4l2_dev,
634	873	"sensor fmt invalid, set to default size\n");
635	874	goto set_default;
636	875	}
637		-
638		- /* v4l2_subdev_format reserved[0]
639		- * using as mipi virtual channel
640		- */
641		- switch (fmt.reserved[0]) {
642		- case V4L2_MBUS_CSI2_CHANNEL_3:
643		- *vc = 3;
644		- break;
645		- case V4L2_MBUS_CSI2_CHANNEL_2:
646		- *vc = 2;
647		- break;
648		- case V4L2_MBUS_CSI2_CHANNEL_1:
649		- *vc = 1;
650		- break;
651		- case V4L2_MBUS_CSI2_CHANNEL_0:
652		- *vc = 0;
653		- break;
654		- default:
655		- *vc = -1;
	876	+ ch_info.index = pad_id;
	877	+ ret = v4l2_subdev_call(sd,
	878	+ core, ioctl,
	879	+ RKMODULE_GET_CHANNEL_INFO,
	880	+ &ch_info);
	881	+ if (!ret) {
	882	+ fmt.format.width = ch_info.width;
	883	+ fmt.format.height = ch_info.height;
	884	+ fmt.format.code = ch_info.bus_fmt;
	885	+ switch (ch_info.vc) {
	886	+ case V4L2_MBUS_CSI2_CHANNEL_3:
	887	+ csi_info->vc = 3;
	888	+ break;
	889	+ case V4L2_MBUS_CSI2_CHANNEL_2:
	890	+ csi_info->vc = 2;
	891	+ break;
	892	+ case V4L2_MBUS_CSI2_CHANNEL_1:
	893	+ csi_info->vc = 1;
	894	+ break;
	895	+ case V4L2_MBUS_CSI2_CHANNEL_0:
	896	+ csi_info->vc = 0;
	897	+ break;
	898	+ default:
	899	+ csi_info->vc = 0xff;
	900	+ }
	901	+ if (ch_info.bus_fmt == MEDIA_BUS_FMT_SPD_2X8 \|\|
	902	+ ch_info.bus_fmt == MEDIA_BUS_FMT_EBD_1X8) {
	903	+ if (ch_info.data_type > 0)
	904	+ csi_info->data_type = ch_info.data_type;
	905	+ if (ch_info.data_bit > 0)
	906	+ csi_info->data_bit = ch_info.data_bit;
	907	+ }
	908	+ } else {
	909	+ csi_info->vc = 0xff;
656	910	}
657	911
658	912	v4l2_dbg(1, rkcif_debug, sd->v4l2_dev,
..	..	@@ -663,7 +917,26 @@
663	917	rect->top = 0;
664	918	rect->width = fmt.format.width;
665	919	rect->height = fmt.format.height;
666		-
	920	+ ret = v4l2_subdev_call(sd,
	921	+ core, ioctl,
	922	+ RKMODULE_GET_CAPTURE_MODE,
	923	+ &capture_info);
	924	+ if (!ret) {
	925	+ if (capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	926	+ dev->hw_dev->is_rk3588s2) {
	927	+ for (i = 0; i < capture_info.multi_dev.dev_num; i++) {
	928	+ if (capture_info.multi_dev.dev_idx[i] == 0)
	929	+ capture_info.multi_dev.dev_idx[i] = 2;
	930	+ else if (capture_info.multi_dev.dev_idx[i] == 2)
	931	+ capture_info.multi_dev.dev_idx[i] = 4;
	932	+ else if (capture_info.multi_dev.dev_idx[i] == 3)
	933	+ capture_info.multi_dev.dev_idx[i] = 5;
	934	+ }
	935	+ }
	936	+ csi_info->capture_info = capture_info;
	937	+ } else {
	938	+ csi_info->capture_info.mode = RKMODULE_CAPTURE_MODE_NONE;
	939	+ }
667	940	for (i = 0; i < ARRAY_SIZE(in_fmts); i++)
668	941	if (fmt.format.code == in_fmts[i].mbus_code &&
669	942	fmt.format.field == in_fmts[i].field)
..	..	@@ -680,8 +953,8 @@
680	953	return NULL;
681	954	}
682	955
683		-static const struct
684		-cif_output_fmt find_output_fmt(struct rkcif_stream stream, u32 pixelfmt)
	956	+const struct
	957	+cif_output_fmt rkcif_find_output_fmt(struct rkcif_stream stream, u32 pixelfmt)
685	958	{
686	959	const struct cif_output_fmt *fmt;
687	960	u32 i;
..	..	@@ -714,6 +987,31 @@
714	987	break;
715	988	default:
716	989	index = CIF_REG_MIPI_LVDS_ID0_CTRL0;
	990	+ break;
	991	+ }
	992	+
	993	+ return index;
	994	+}
	995	+
	996	+static enum cif_reg_index get_reg_index_of_lvds_id_ctrl0(int channel_id)
	997	+{
	998	+ enum cif_reg_index index;
	999	+
	1000	+ switch (channel_id) {
	1001	+ case 0:
	1002	+ index = CIF_REG_LVDS_ID0_CTRL0;
	1003	+ break;
	1004	+ case 1:
	1005	+ index = CIF_REG_LVDS_ID1_CTRL0;
	1006	+ break;
	1007	+ case 2:
	1008	+ index = CIF_REG_LVDS_ID2_CTRL0;
	1009	+ break;
	1010	+ case 3:
	1011	+ index = CIF_REG_LVDS_ID3_CTRL0;
	1012	+ break;
	1013	+ default:
	1014	+ index = CIF_REG_LVDS_ID0_CTRL0;
717	1015	break;
718	1016	}
719	1017
..	..	@@ -1170,12 +1468,50 @@
1170	1468	return index;
1171	1469	}
1172	1470
	1471	+int rkcif_get_linetime(struct rkcif_stream *stream)
	1472	+{
	1473	+ struct rkcif_device *cif_dev = stream->cifdev;
	1474	+ struct rkcif_sensor_info *sensor = &cif_dev->terminal_sensor;
	1475	+ u32 numerator, denominator;
	1476	+ u32 def_fps = 0;
	1477	+ int line_time = 0;
	1478	+ int vblank_def = 0;
	1479	+ int vblank_curr = 0;
	1480	+
	1481	+ numerator = sensor->fi.interval.numerator;
	1482	+ denominator = sensor->fi.interval.denominator;
	1483	+ if (!numerator \|\| !denominator) {
	1484	+ v4l2_err(&cif_dev->v4l2_dev,
	1485	+ "get frame interval fail, numerator %d, denominator %d\n",
	1486	+ numerator, denominator);
	1487	+ return -EINVAL;
	1488	+ }
	1489	+ def_fps = denominator / numerator;
	1490	+ if (!def_fps) {
	1491	+ v4l2_err(&cif_dev->v4l2_dev,
	1492	+ "get fps fail, numerator %d, denominator %d\n",
	1493	+ numerator, denominator);
	1494	+ return -EINVAL;
	1495	+ }
	1496	+ vblank_def = rkcif_get_sensor_vblank_def(cif_dev);
	1497	+ vblank_curr = rkcif_get_sensor_vblank(cif_dev);
	1498	+ if (!vblank_def \|\| !vblank_curr) {
	1499	+ v4l2_err(&cif_dev->v4l2_dev,
	1500	+ "get vblank fail, vblank_def %d, vblank_curr %d\n",
	1501	+ vblank_def, vblank_curr);
	1502	+ return -EINVAL;
	1503	+ }
	1504	+ line_time = div_u64(1000000000, def_fps);
	1505	+ line_time = div_u64(line_time, vblank_def + sensor->raw_rect.height);
	1506	+ return line_time;
	1507	+}
	1508	+
1173	1509	/*************************** stream operations ****************************/
1174	1510	static int rkcif_assign_new_buffer_oneframe(struct rkcif_stream *stream,
1175		- enum rkcif_yuvaddr_state stat)
	1511	+ enum rkcif_yuvaddr_state stat)
1176	1512	{
1177	1513	struct rkcif_device *dev = stream->cifdev;
1178		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	1514	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1179	1515	struct rkcif_buffer *buffer = NULL;
1180	1516	u32 frm_addr_y = CIF_REG_DVP_FRM0_ADDR_Y;
1181	1517	u32 frm_addr_uv = CIF_REG_DVP_FRM0_ADDR_UV;
..	..	@@ -1270,12 +1606,738 @@
1270	1606	} else {
1271	1607	ret = -EINVAL;
1272	1608	}
1273		- v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
1274		- "not active buffer, frame Drop\n");
	1609	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	1610	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
1275	1611	}
1276	1612	}
1277	1613	spin_unlock_irqrestore(&stream->vbq_lock, flags);
1278	1614	return ret;
	1615	+}
	1616	+
	1617	+static struct v4l2_subdev get_rkisp_sd(struct sditf_priv priv)
	1618	+{
	1619	+ struct media_pad *pad = NULL;
	1620	+
	1621	+ if (priv && priv->pads[0].entity->num_links) {
	1622	+ if (priv->is_combine_mode)
	1623	+ pad = media_entity_remote_pad(&priv->pads[1]);
	1624	+ else
	1625	+ pad = media_entity_remote_pad(&priv->pads[0]);
	1626	+ if (pad)
	1627	+ return media_entity_to_v4l2_subdev(pad->entity);
	1628	+ }
	1629	+ return NULL;
	1630	+}
	1631	+
	1632	+static void rkcif_rx_buffer_free(struct rkcif_stream *stream)
	1633	+{
	1634	+ struct v4l2_subdev *sd;
	1635	+ struct rkisp_rx_buf *dbufs;
	1636	+ struct rkcif_device *dev = stream->cifdev;
	1637	+
	1638	+ sd = get_rkisp_sd(dev->sditf[0]);
	1639	+ if (!sd)
	1640	+ return;
	1641	+
	1642	+ while (!list_empty(&stream->rx_buf_head_vicap)) {
	1643	+ dbufs = list_first_entry(&stream->rx_buf_head_vicap, struct rkisp_rx_buf, list);
	1644	+ if (dbufs->is_init)
	1645	+ v4l2_subdev_call(sd, core, ioctl,
	1646	+ RKISP_VICAP_CMD_RX_BUFFER_FREE, dbufs);
	1647	+ dma_buf_put(dbufs->dbuf);
	1648	+ list_del(&dbufs->list);
	1649	+ kfree(dbufs);
	1650	+ }
	1651	+}
	1652	+
	1653	+static void rkcif_s_rx_buffer(struct rkcif_stream stream, struct rkisp_rx_buf dbufs)
	1654	+{
	1655	+ struct rkcif_device *dev = stream->cifdev;
	1656	+ struct v4l2_subdev *sd;
	1657	+ struct rkcif_rx_buffer *rx_buf = NULL;
	1658	+
	1659	+ sd = get_rkisp_sd(dev->sditf[0]);
	1660	+ if (!sd)
	1661	+ return;
	1662	+ if ((dev->rdbk_debug &&
	1663	+ dbufs->sequence < 15) \|\|
	1664	+ rkcif_debug == 3) {
	1665	+ rx_buf = to_cif_rx_buf(dbufs);
	1666	+ v4l2_info(&dev->v4l2_dev,
	1667	+ "s_buf seq %d type %d, dma addr %x, %lld\n",
	1668	+ dbufs->sequence, dbufs->type, (u32)rx_buf->dummy.dma_addr,
	1669	+ rkcif_time_get_ns(dev));
	1670	+ }
	1671	+ v4l2_subdev_call(sd, video, s_rx_buffer, dbufs, NULL);
	1672	+}
	1673	+
	1674	+static void rkcif_enable_skip_frame(struct rkcif_stream *stream, int cap_m, int skip_n)
	1675	+{
	1676	+ struct rkcif_device *dev = stream->cifdev;
	1677	+ u32 val = 0;
	1678	+
	1679	+ val = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_CTRL);
	1680	+ val &= 0xc00fffff;
	1681	+ val \|= cap_m << RKCIF_CAP_SHIFT \| skip_n << RKCIF_SKIP_SHIFT \| RKCIF_SKIP_EN(stream->id);
	1682	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
	1683	+ stream->skip_info.skip_en = true;
	1684	+}
	1685	+
	1686	+static void rkcif_disable_skip_frame(struct rkcif_stream *stream)
	1687	+{ struct rkcif_device *dev = stream->cifdev;
	1688	+ u32 val = 0;
	1689	+
	1690	+ val = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_CTRL);
	1691	+ val &= ~(RKCIF_SKIP_EN(stream->id));
	1692	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
	1693	+ stream->skip_info.skip_en = false;
	1694	+}
	1695	+
	1696	+static void rkcif_rdbk_with_tools(struct rkcif_stream *stream,
	1697	+ struct rkcif_rx_buffer *active_buf)
	1698	+{
	1699	+ unsigned long flags;
	1700	+
	1701	+ spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
	1702	+ if (stream->tools_vdev->state == RKCIF_STATE_STREAMING) {
	1703	+ list_add_tail(&active_buf->list, &stream->tools_vdev->buf_done_head);
	1704	+ if (!work_busy(&stream->tools_vdev->work))
	1705	+ schedule_work(&stream->tools_vdev->work);
	1706	+ }
	1707	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	1708	+}
	1709	+
	1710	+static void rkcif_rdbk_frame_end_toisp(struct rkcif_stream *stream,
	1711	+ struct rkcif_rx_buffer *buffer)
	1712	+{
	1713	+ struct rkcif_device *dev = stream->cifdev;
	1714	+ struct rkcif_sensor_info *sensor = &stream->cifdev->terminal_sensor;
	1715	+ u32 denominator, numerator;
	1716	+ u64 l_ts, m_ts, s_ts, time = 30000000LL;
	1717	+ int ret, fps = -1;
	1718	+ unsigned long flags;
	1719	+
	1720	+ spin_lock_irqsave(&dev->hdr_lock, flags);
	1721	+ if (dev->rdbk_rx_buf[stream->id]) {
	1722	+ list_add_tail(&dev->rdbk_rx_buf[stream->id]->list, &stream->rx_buf_head);
	1723	+ dev->rdbk_rx_buf[stream->id] = buffer;
	1724	+ } else {
	1725	+ dev->rdbk_rx_buf[stream->id] = buffer;
	1726	+ }
	1727	+
	1728	+ numerator = sensor->fi.interval.numerator;
	1729	+ denominator = sensor->fi.interval.denominator;
	1730	+ if (denominator && numerator)
	1731	+ time = numerator * 1000 / denominator * 1000 * 1000;
	1732	+
	1733	+ if (dev->hdr.hdr_mode == HDR_X3 &&
	1734	+ dev->rdbk_rx_buf[RDBK_L] &&
	1735	+ dev->rdbk_rx_buf[RDBK_M] &&
	1736	+ dev->rdbk_rx_buf[RDBK_S]) {
	1737	+ l_ts = dev->rdbk_rx_buf[RDBK_L]->fe_timestamp;
	1738	+ m_ts = dev->rdbk_rx_buf[RDBK_M]->fe_timestamp;
	1739	+ s_ts = dev->rdbk_rx_buf[RDBK_S]->fe_timestamp;
	1740	+
	1741	+ if (m_ts < l_ts \|\| s_ts < m_ts) {
	1742	+ v4l2_err(&dev->v4l2_dev,
	1743	+ "s/m/l frame err, timestamp s:%lld m:%lld l:%lld\n",
	1744	+ s_ts, m_ts, l_ts);
	1745	+ goto RDBK_TOISP_UNMATCH;
	1746	+ }
	1747	+
	1748	+ if ((m_ts - l_ts) > time \|\| (s_ts - m_ts) > time) {
	1749	+ ret = v4l2_subdev_call(sensor->sd,
	1750	+ video,
	1751	+ g_frame_interval,
	1752	+ &sensor->fi);
	1753	+ if (!ret) {
	1754	+ denominator = sensor->fi.interval.denominator;
	1755	+ numerator = sensor->fi.interval.numerator;
	1756	+ if (denominator && numerator) {
	1757	+ time = numerator * 1000 / denominator * 1000 * 1000;
	1758	+ fps = denominator / numerator;
	1759	+ }
	1760	+ }
	1761	+
	1762	+ if ((m_ts - l_ts) > time \|\| (s_ts - m_ts) > time) {
	1763	+ v4l2_err(&dev->v4l2_dev,
	1764	+ "timestamp no match, s:%lld m:%lld l:%lld, fps:%d\n",
	1765	+ s_ts, m_ts, l_ts, fps);
	1766	+ goto RDBK_TOISP_UNMATCH;
	1767	+ }
	1768	+ }
	1769	+ dev->rdbk_rx_buf[RDBK_M]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
	1770	+ dev->rdbk_rx_buf[RDBK_S]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
	1771	+ rkcif_s_rx_buffer(&dev->stream[RDBK_L], &dev->rdbk_rx_buf[RDBK_L]->dbufs);
	1772	+ rkcif_s_rx_buffer(&dev->stream[RDBK_M], &dev->rdbk_rx_buf[RDBK_M]->dbufs);
	1773	+ rkcif_s_rx_buffer(&dev->stream[RDBK_S], &dev->rdbk_rx_buf[RDBK_S]->dbufs);
	1774	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_L], dev->rdbk_rx_buf[RDBK_L]);
	1775	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_M], dev->rdbk_rx_buf[RDBK_M]);
	1776	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_S], dev->rdbk_rx_buf[RDBK_S]);
	1777	+ atomic_dec(&dev->stream[RDBK_L].buf_cnt);
	1778	+ atomic_dec(&dev->stream[RDBK_M].buf_cnt);
	1779	+ atomic_dec(&dev->stream[RDBK_S].buf_cnt);
	1780	+ dev->rdbk_rx_buf[RDBK_L] = NULL;
	1781	+ dev->rdbk_rx_buf[RDBK_M] = NULL;
	1782	+ dev->rdbk_rx_buf[RDBK_S] = NULL;
	1783	+ } else if (dev->hdr.hdr_mode == HDR_X2 &&
	1784	+ dev->rdbk_rx_buf[RDBK_L] && dev->rdbk_rx_buf[RDBK_M]) {
	1785	+ l_ts = dev->rdbk_rx_buf[RDBK_L]->fe_timestamp;
	1786	+ s_ts = dev->rdbk_rx_buf[RDBK_M]->fe_timestamp;
	1787	+
	1788	+ if (s_ts < l_ts) {
	1789	+ v4l2_err(&dev->v4l2_dev,
	1790	+ "s/l frame err, timestamp s:%lld l:%lld\n",
	1791	+ s_ts, l_ts);
	1792	+ goto RDBK_TOISP_UNMATCH;
	1793	+ }
	1794	+
	1795	+ if ((s_ts - l_ts) > time) {
	1796	+ ret = v4l2_subdev_call(sensor->sd,
	1797	+ video,
	1798	+ g_frame_interval,
	1799	+ &sensor->fi);
	1800	+ if (!ret) {
	1801	+ denominator = sensor->fi.interval.denominator;
	1802	+ numerator = sensor->fi.interval.numerator;
	1803	+ if (denominator && numerator) {
	1804	+ time = numerator * 1000 / denominator * 1000 * 1000;
	1805	+ fps = denominator / numerator;
	1806	+ }
	1807	+ }
	1808	+ if ((s_ts - l_ts) > time) {
	1809	+ v4l2_err(&dev->v4l2_dev,
	1810	+ "timestamp no match, s:%lld l:%lld, fps:%d\n",
	1811	+ s_ts, l_ts, fps);
	1812	+ goto RDBK_TOISP_UNMATCH;
	1813	+ }
	1814	+ }
	1815	+ dev->rdbk_rx_buf[RDBK_M]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
	1816	+ rkcif_s_rx_buffer(&dev->stream[RDBK_L], &dev->rdbk_rx_buf[RDBK_L]->dbufs);
	1817	+ rkcif_s_rx_buffer(&dev->stream[RDBK_M], &dev->rdbk_rx_buf[RDBK_M]->dbufs);
	1818	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_L], dev->rdbk_rx_buf[RDBK_L]);
	1819	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_M], dev->rdbk_rx_buf[RDBK_M]);
	1820	+ atomic_dec(&dev->stream[RDBK_L].buf_cnt);
	1821	+ atomic_dec(&dev->stream[RDBK_M].buf_cnt);
	1822	+ dev->rdbk_rx_buf[RDBK_L] = NULL;
	1823	+ dev->rdbk_rx_buf[RDBK_M] = NULL;
	1824	+ }
	1825	+
	1826	+ spin_unlock_irqrestore(&dev->hdr_lock, flags);
	1827	+ return;
	1828	+
	1829	+RDBK_TOISP_UNMATCH:
	1830	+ spin_unlock_irqrestore(&dev->hdr_lock, flags);
	1831	+}
	1832	+
	1833	+static void rkcif_write_buff_addr_multi_dev_combine(struct rkcif_stream *stream,
	1834	+ u32 frm_addr_y, u32 frm_addr_uv,
	1835	+ u32 buff_addr_y, u32 buff_addr_cbcr,
	1836	+ bool is_dummy_buf)
	1837	+{
	1838	+ struct rkcif_device *dev = stream->cifdev;
	1839	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
	1840	+ u32 addr_y, addr_cbcr;
	1841	+ int addr_offset = 0;
	1842	+ int i = 0;
	1843	+ int tmp_host_index = dev->csi_host_idx;
	1844	+
	1845	+ for (i = 0; i < capture_info->multi_dev.dev_num; i++) {
	1846	+ if (is_dummy_buf) {
	1847	+ addr_y = buff_addr_y;
	1848	+ } else {
	1849	+ addr_offset = dev->channels[stream->id].left_virtual_width;
	1850	+ addr_y = buff_addr_y + addr_offset * i;
	1851	+ }
	1852	+ dev->csi_host_idx = capture_info->multi_dev.dev_idx[i];
	1853	+ rkcif_write_register(dev, frm_addr_y, addr_y);
	1854	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW &&
	1855	+ frm_addr_uv && buff_addr_cbcr) {
	1856	+ if (is_dummy_buf) {
	1857	+ addr_cbcr = buff_addr_cbcr;
	1858	+ } else {
	1859	+ addr_offset = dev->channels[stream->id].left_virtual_width;
	1860	+ addr_cbcr = buff_addr_cbcr + addr_offset * i;
	1861	+ }
	1862	+ rkcif_write_register(dev, frm_addr_uv, addr_cbcr);
	1863	+ }
	1864	+ }
	1865	+ dev->csi_host_idx = tmp_host_index;
	1866	+}
	1867	+
	1868	+static void rkcif_assign_new_buffer_init_toisp(struct rkcif_stream *stream,
	1869	+ int channel_id)
	1870	+{
	1871	+ struct rkcif_device *dev = stream->cifdev;
	1872	+ struct rkcif_rx_buffer *rx_buf;
	1873	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	1874	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
	1875	+ u32 frm0_addr_y;
	1876	+ u32 frm1_addr_y;
	1877	+ u32 buff_addr_y;
	1878	+ unsigned long flags;
	1879	+
	1880	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	1881	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	1882	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	1883	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
	1884	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
	1885	+ } else {
	1886	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
	1887	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
	1888	+ }
	1889	+
	1890	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	1891	+
	1892	+ if (!stream->curr_buf_toisp) {
	1893	+ if (!list_empty(&stream->rx_buf_head)) {
	1894	+ rx_buf = list_first_entry(&stream->rx_buf_head,
	1895	+ struct rkcif_rx_buffer,
	1896	+ list);
	1897	+ if (rx_buf) {
	1898	+ list_del(&rx_buf->list);
	1899	+ stream->curr_buf_toisp = rx_buf;
	1900	+ }
	1901	+ }
	1902	+ }
	1903	+
	1904	+ if (stream->curr_buf_toisp) {
	1905	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	1906	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	1907	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm0_addr_y, 0,
	1908	+ buff_addr_y, 0, false);
	1909	+ } else {
	1910	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	1911	+ }
	1912	+ } else {
	1913	+ if (stream->lack_buf_cnt < 2)
	1914	+ stream->lack_buf_cnt++;
	1915	+ }
	1916	+
	1917	+ if (!stream->next_buf_toisp) {
	1918	+ if (!list_empty(&stream->rx_buf_head)) {
	1919	+ rx_buf = list_first_entry(&stream->rx_buf_head,
	1920	+ struct rkcif_rx_buffer, list);
	1921	+ if (rx_buf) {
	1922	+ list_del(&rx_buf->list);
	1923	+ stream->next_buf_toisp = rx_buf;
	1924	+ } else {
	1925	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	1926	+ }
	1927	+ } else {
	1928	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	1929	+ }
	1930	+ }
	1931	+
	1932	+ if (stream->next_buf_toisp) {
	1933	+ buff_addr_y = stream->next_buf_toisp->dummy.dma_addr;
	1934	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	1935	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm1_addr_y, 0,
	1936	+ buff_addr_y, 0, false);
	1937	+ } else {
	1938	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	1939	+ }
	1940	+ } else {
	1941	+ if (stream->lack_buf_cnt < 2)
	1942	+ stream->lack_buf_cnt++;
	1943	+ }
	1944	+
	1945	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	1946	+ stream->buf_owner = RKCIF_DMAEN_BY_ISP;
	1947	+}
	1948	+
	1949	+static void rkcif_dphy_quick_stream(struct rkcif_device *dev, int on)
	1950	+{
	1951	+ struct rkcif_pipeline *p = NULL;
	1952	+ int j = 0;
	1953	+
	1954	+ if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	1955	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	1956	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) {
	1957	+ p = &dev->pipe;
	1958	+ for (j = 0; j < p->num_subdevs; j++) {
	1959	+ if (p->subdevs[j] != dev->terminal_sensor.sd &&
	1960	+ p->subdevs[j] != dev->active_sensor->sd) {
	1961	+ v4l2_subdev_call(p->subdevs[j], core, ioctl,
	1962	+ RKMODULE_SET_QUICK_STREAM, &on);
	1963	+ break;
	1964	+ }
	1965	+ }
	1966	+ }
	1967	+}
	1968	+
	1969	+static int rkcif_assign_new_buffer_update_toisp(struct rkcif_stream *stream,
	1970	+ int channel_id)
	1971	+{
	1972	+ struct rkcif_device *dev = stream->cifdev;
	1973	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	1974	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
	1975	+ struct rkcif_rx_buffer *buffer = NULL;
	1976	+ struct rkcif_rx_buffer *active_buf = NULL;
	1977	+ struct sditf_priv *priv = dev->sditf[0];
	1978	+ u32 frm_addr_y, buff_addr_y;
	1979	+ unsigned long flags;
	1980	+
	1981	+
	1982	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	1983	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	1984	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	1985	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	1986	+ get_reg_index_of_frm0_y_addr(channel_id) :
	1987	+ get_reg_index_of_frm1_y_addr(channel_id);
	1988	+ } else {
	1989	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	1990	+ get_dvp_reg_index_of_frm0_y_addr(channel_id) :
	1991	+ get_dvp_reg_index_of_frm1_y_addr(channel_id);
	1992	+ }
	1993	+
	1994	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	1995	+ if (stream->cur_skip_frame)
	1996	+ goto out_get_buf;
	1997	+ memset(&stream->toisp_buf_state, 0, sizeof(stream->toisp_buf_state));
	1998	+ if (!list_empty(&stream->rx_buf_head)) {
	1999	+ if (stream->curr_buf_toisp && stream->next_buf_toisp &&
	2000	+ stream->curr_buf_toisp != stream->next_buf_toisp)
	2001	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_ROTATE;
	2002	+ else
	2003	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_LOSS;
	2004	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2005	+ active_buf = stream->curr_buf_toisp;
	2006	+
	2007	+ buffer = list_first_entry(&stream->rx_buf_head,
	2008	+ struct rkcif_rx_buffer, list);
	2009	+ if (buffer) {
	2010	+ list_del(&buffer->list);
	2011	+ stream->curr_buf_toisp = buffer;
	2012	+ }
	2013	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
	2014	+ if (!active_buf)
	2015	+ goto out_get_buf;
	2016	+ if (stream->frame_idx == 1)
	2017	+ active_buf->dbufs.is_first = true;
	2018	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	2019	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	2020	+ active_buf->fe_timestamp = rkcif_time_get_ns(dev);
	2021	+ stream->last_frame_idx = stream->frame_idx;
	2022	+ if (dev->hdr.hdr_mode == NO_HDR) {
	2023	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	2024	+ if (dev->is_support_tools && stream->tools_vdev)
	2025	+ rkcif_rdbk_with_tools(stream, active_buf);
	2026	+ atomic_dec(&stream->buf_cnt);
	2027	+ } else {
	2028	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	2029	+ }
	2030	+ } else {
	2031	+ if (active_buf)
	2032	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	2033	+ if (dev->is_support_tools && stream->tools_vdev)
	2034	+ rkcif_rdbk_with_tools(stream, active_buf);
	2035	+ }
	2036	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2037	+ active_buf = stream->next_buf_toisp;
	2038	+ buffer = list_first_entry(&stream->rx_buf_head,
	2039	+ struct rkcif_rx_buffer, list);
	2040	+ if (buffer) {
	2041	+ list_del(&buffer->list);
	2042	+ stream->next_buf_toisp = buffer;
	2043	+ }
	2044	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
	2045	+ if (!active_buf)
	2046	+ goto out_get_buf;
	2047	+ if (stream->frame_idx == 1)
	2048	+ active_buf->dbufs.is_first = true;
	2049	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	2050	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	2051	+ active_buf->fe_timestamp = rkcif_time_get_ns(dev);
	2052	+ stream->last_frame_idx = stream->frame_idx;
	2053	+ if (dev->hdr.hdr_mode == NO_HDR) {
	2054	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	2055	+ if (dev->is_support_tools && stream->tools_vdev)
	2056	+ rkcif_rdbk_with_tools(stream, active_buf);
	2057	+ atomic_dec(&stream->buf_cnt);
	2058	+ } else {
	2059	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	2060	+ }
	2061	+ } else {
	2062	+ if (active_buf)
	2063	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	2064	+ if (dev->is_support_tools && stream->tools_vdev)
	2065	+ rkcif_rdbk_with_tools(stream, active_buf);
	2066	+ }
	2067	+ }
	2068	+ if (stream->lack_buf_cnt)
	2069	+ stream->lack_buf_cnt--;
	2070	+ } else {
	2071	+ if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	2072	+ goto out_get_buf;
	2073	+ if (stream->lack_buf_cnt < 2)
	2074	+ stream->lack_buf_cnt++;
	2075	+ if (dev->hw_dev->dummy_buf.vaddr) {
	2076	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2077	+ active_buf = stream->curr_buf_toisp;
	2078	+ } else {
	2079	+ active_buf = stream->next_buf_toisp;
	2080	+ }
	2081	+ } else if (stream->curr_buf_toisp && stream->next_buf_toisp &&
	2082	+ stream->curr_buf_toisp != stream->next_buf_toisp) {
	2083	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2084	+ active_buf = stream->curr_buf_toisp;
	2085	+ stream->curr_buf_toisp = stream->next_buf_toisp;
	2086	+ buffer = stream->next_buf_toisp;
	2087	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2088	+ active_buf = stream->next_buf_toisp;
	2089	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	2090	+ buffer = stream->curr_buf_toisp;
	2091	+ }
	2092	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_THESAME;
	2093	+ if (stream->cifdev->rdbk_debug)
	2094	+ v4l2_info(&stream->cifdev->v4l2_dev,
	2095	+ "stream[%d] hold buf %x\n",
	2096	+ stream->id,
	2097	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
	2098	+ } else {
	2099	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_LOSS;
	2100	+ if (stream->is_single_cap) {
	2101	+ active_buf = stream->curr_buf_toisp;
	2102	+ stream->curr_buf_toisp = NULL;
	2103	+ stream->next_buf_toisp = NULL;
	2104	+ }
	2105	+ }
	2106	+
	2107	+ if (active_buf) {
	2108	+ if (stream->frame_idx == 1)
	2109	+ active_buf->dbufs.is_first = true;
	2110	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	2111	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	2112	+ active_buf->fe_timestamp = rkcif_time_get_ns(dev);
	2113	+ stream->last_frame_idx = stream->frame_idx;
	2114	+ if (dev->hdr.hdr_mode == NO_HDR) {
	2115	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	2116	+ atomic_dec(&stream->buf_cnt);
	2117	+ } else {
	2118	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	2119	+ }
	2120	+ } else {
	2121	+ if (stream->cifdev->rdbk_debug && dev->hw_dev->dummy_buf.vaddr)
	2122	+ v4l2_info(&stream->cifdev->v4l2_dev,
	2123	+ "stream[%d] loss frame %d\n",
	2124	+ stream->id,
	2125	+ stream->frame_idx - 1);
	2126	+ }
	2127	+ if (dev->is_support_tools && stream->tools_vdev && active_buf)
	2128	+ rkcif_rdbk_with_tools(stream, active_buf);
	2129	+ }
	2130	+out_get_buf:
	2131	+ stream->frame_phase_cache = stream->frame_phase;
	2132	+ if (buffer) {
	2133	+ buff_addr_y = buffer->dummy.dma_addr;
	2134	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2135	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2136	+ buff_addr_y, 0, false);
	2137	+ } else {
	2138	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2139	+ }
	2140	+ if (dev->rdbk_debug > 1 &&
	2141	+ stream->frame_idx < 15)
	2142	+ v4l2_info(&dev->v4l2_dev,
	2143	+ "stream[%d] update, seq %d, reg %x, buf %x\n",
	2144	+ stream->id,
	2145	+ stream->frame_idx - 1,
	2146	+ frm_addr_y, (u32)buffer->dummy.dma_addr);
	2147	+ } else if (dev->hw_dev->dummy_buf.vaddr && priv &&
	2148	+ priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
	2149	+ buff_addr_y = dev->hw_dev->dummy_buf.dma_addr;
	2150	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2151	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2152	+ buff_addr_y, 0, true);
	2153	+ } else {
	2154	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2155	+ }
	2156	+ }
	2157	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	2158	+ return 0;
	2159	+}
	2160	+
	2161	+static int rkcif_assign_new_buffer_pingpong_toisp(struct rkcif_stream *stream,
	2162	+ int init, int channel_id)
	2163	+{
	2164	+ int ret = 0;
	2165	+
	2166	+ if (init)
	2167	+ rkcif_assign_new_buffer_init_toisp(stream, channel_id);
	2168	+ else
	2169	+ ret = rkcif_assign_new_buffer_update_toisp(stream, channel_id);
	2170	+ return ret;
	2171	+}
	2172	+
	2173	+void rkcif_assign_check_buffer_update_toisp(struct rkcif_stream *stream)
	2174	+{
	2175	+ struct rkcif_device *dev = stream->cifdev;
	2176	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2177	+ struct rkcif_rx_buffer *buffer = NULL;
	2178	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
	2179	+ struct rkcif_rx_buffer *active_buf = NULL;
	2180	+ u32 frm_addr_y, buff_addr_y;
	2181	+ u32 vblank = 0;
	2182	+ u32 vblank_ns = 0;
	2183	+ u64 cur_time = 0;
	2184	+ int frame_phase = 0;
	2185	+ int frame_phase_next = 0;
	2186	+
	2187	+ if (stream->toisp_buf_state.state == RKCIF_TOISP_BUF_ROTATE \|\|
	2188	+ (stream->toisp_buf_state.state == RKCIF_TOISP_BUF_THESAME &&
	2189	+ stream->toisp_buf_state.check_cnt >= 1) \|\|
	2190	+ (stream->toisp_buf_state.state == RKCIF_TOISP_BUF_LOSS &&
	2191	+ stream->toisp_buf_state.check_cnt >= 2)) {
	2192	+ if (dev->rdbk_debug > 2 &&
	2193	+ stream->frame_idx < 15)
	2194	+ v4l2_info(&dev->v4l2_dev,
	2195	+ "stream[%d] addr check not equal 0x%x 0x%x\n",
	2196	+ stream->id,
	2197	+ (u32)stream->curr_buf_toisp->dummy.dma_addr,
	2198	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
	2199	+ return;
	2200	+ }
	2201	+ if (!dev->sensor_linetime)
	2202	+ dev->sensor_linetime = rkcif_get_linetime(stream);
	2203	+ vblank = rkcif_get_sensor_vblank(dev);
	2204	+ vblank_ns = vblank * dev->sensor_linetime;
	2205	+ cur_time = rkcif_time_get_ns(dev);
	2206	+
	2207	+ if (stream->toisp_buf_state.state == RKCIF_TOISP_BUF_THESAME) {
	2208	+ frame_phase = stream->frame_phase;
	2209	+ } else {
	2210	+ if (stream->toisp_buf_state.state == RKCIF_TOISP_BUF_LOSS &&
	2211	+ stream->toisp_buf_state.check_cnt == 0 &&
	2212	+ cur_time - stream->readout.fe_timestamp < (vblank_ns - 500000)) {
	2213	+ stream->toisp_buf_state.is_early_update = true;
	2214	+ frame_phase = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2215	+ CIF_CSI_FRAME1_READY : CIF_CSI_FRAME0_READY;
	2216	+ frame_phase_next = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2217	+ CIF_CSI_FRAME0_READY : CIF_CSI_FRAME1_READY;
	2218	+ } else {
	2219	+ if (stream->toisp_buf_state.check_cnt == 1 &&
	2220	+ (!stream->toisp_buf_state.is_early_update))
	2221	+ return;
	2222	+ frame_phase = stream->frame_phase;
	2223	+ stream->toisp_buf_state.is_early_update = false;
	2224	+ }
	2225	+ }
	2226	+ if (dev->rdbk_debug > 2 &&
	2227	+ stream->frame_idx < 15)
	2228	+ v4l2_info(&dev->v4l2_dev,
	2229	+ "stream[%d] check update, cur %lld, fe %lld, vb %u lack_buf %d\n",
	2230	+ stream->id,
	2231	+ cur_time, stream->readout.fe_timestamp,
	2232	+ vblank_ns, stream->lack_buf_cnt);
	2233	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2234	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	2235	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	2236	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2237	+ get_reg_index_of_frm0_y_addr(stream->id) :
	2238	+ get_reg_index_of_frm1_y_addr(stream->id);
	2239	+ } else {
	2240	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2241	+ get_dvp_reg_index_of_frm0_y_addr(stream->id) :
	2242	+ get_dvp_reg_index_of_frm1_y_addr(stream->id);
	2243	+ }
	2244	+ if (!list_empty(&stream->rx_buf_head)) {
	2245	+ if (frame_phase == CIF_CSI_FRAME0_READY) {
	2246	+ active_buf = stream->curr_buf_toisp;
	2247	+ buffer = list_first_entry(&stream->rx_buf_head,
	2248	+ struct rkcif_rx_buffer, list);
	2249	+ if (buffer) {
	2250	+ list_del(&buffer->list);
	2251	+ stream->curr_buf_toisp = buffer;
	2252	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2253	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2254	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2255	+ frm_addr_y, 0,
	2256	+ buff_addr_y, 0,
	2257	+ false);
	2258	+ } else {
	2259	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2260	+ }
	2261	+ if (dev->rdbk_debug > 1 &&
	2262	+ stream->frame_idx < 15)
	2263	+ v4l2_info(&dev->v4l2_dev,
	2264	+ "stream[%d] check update, seq %d, addr 0x%x, buf 0x%x\n",
	2265	+ stream->id,
	2266	+ stream->frame_idx - 1, frm_addr_y,
	2267	+ (u32)stream->curr_buf_toisp->dummy.dma_addr);
	2268	+ }
	2269	+ } else if (frame_phase == CIF_CSI_FRAME1_READY) {
	2270	+ active_buf = stream->next_buf_toisp;
	2271	+ buffer = list_first_entry(&stream->rx_buf_head,
	2272	+ struct rkcif_rx_buffer, list);
	2273	+ if (buffer) {
	2274	+ list_del(&buffer->list);
	2275	+ stream->next_buf_toisp = buffer;
	2276	+ buff_addr_y = stream->next_buf_toisp->dummy.dma_addr;
	2277	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2278	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2279	+ frm_addr_y, 0,
	2280	+ buff_addr_y, 0,
	2281	+ false);
	2282	+ } else {
	2283	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2284	+ }
	2285	+ if (dev->rdbk_debug > 1 &&
	2286	+ stream->frame_idx < 15)
	2287	+ v4l2_info(&dev->v4l2_dev,
	2288	+ "stream[%d] check update, seq %d, addr 0x%x, buf 0x%x\n",
	2289	+ stream->id,
	2290	+ stream->frame_idx - 1, frm_addr_y,
	2291	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
	2292	+ }
	2293	+ }
	2294	+ if (stream->lack_buf_cnt)
	2295	+ stream->lack_buf_cnt--;
	2296	+ }
	2297	+ if (stream->toisp_buf_state.is_early_update) {
	2298	+ if (dev->rdbk_debug > 1 &&
	2299	+ stream->frame_idx < 15)
	2300	+ v4l2_info(&dev->v4l2_dev,
	2301	+ "stream[%d] early update, seq %d\n",
	2302	+ stream->id,
	2303	+ stream->frame_idx - 1);
	2304	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2305	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
	2306	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_CTRL, 0x00010000);
	2307	+ else
	2308	+ rkcif_write_register_or(dev, CIF_REG_DVP_CTRL, 0x00010000);
	2309	+ if (active_buf) {
	2310	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	2311	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	2312	+ stream->last_frame_idx = stream->frame_idx;
	2313	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	2314	+ }
	2315	+ if (dev->hw_dev->dummy_buf.vaddr)
	2316	+ return;
	2317	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2318	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	2319	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	2320	+ frm_addr_y = frame_phase_next & CIF_CSI_FRAME0_READY ?
	2321	+ get_reg_index_of_frm0_y_addr(stream->id) :
	2322	+ get_reg_index_of_frm1_y_addr(stream->id);
	2323	+ } else {
	2324	+ frm_addr_y = frame_phase_next & CIF_CSI_FRAME0_READY ?
	2325	+ get_dvp_reg_index_of_frm0_y_addr(stream->id) :
	2326	+ get_dvp_reg_index_of_frm1_y_addr(stream->id);
	2327	+ }
	2328	+ if (frame_phase == CIF_CSI_FRAME0_READY)
	2329	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	2330	+ else
	2331	+ stream->curr_buf_toisp = stream->next_buf_toisp;
	2332	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2333	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2334	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2335	+ buff_addr_y, 0, false);
	2336	+ } else {
	2337	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2338	+ }
	2339	+ }
	2340	+ stream->toisp_buf_state.check_cnt++;
1279	2341	}
1280	2342
1281	2343	static void rkcif_assign_new_buffer_init(struct rkcif_stream *stream,
..	..	@@ -1285,11 +2347,14 @@
1285	2347	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1286	2348	u32 frm0_addr_y, frm0_addr_uv;
1287	2349	u32 frm1_addr_y, frm1_addr_uv;
	2350	+ u32 buff_addr_y, buff_addr_cbcr;
1288	2351	unsigned long flags;
1289		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2352	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1290	2353	struct csi_channel_info *channel = &dev->channels[channel_id];
1291	2354
1292		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	2355	+ stream->lack_buf_cnt = 0;
	2356	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2357	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
1293	2358	mbus_cfg->type == V4L2_MBUS_CCP2) {
1294	2359	frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
1295	2360	frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
..	..	@@ -1309,53 +2374,119 @@
1309	2374	stream->curr_buf = list_first_entry(&stream->buf_head,
1310	2375	struct rkcif_buffer,
1311	2376	queue);
	2377	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev, "%s %d, stream[%d] buf idx %d\n",
	2378	+ __func__, __LINE__, stream->id, stream->curr_buf->vb.vb2_buf.index);
1312	2379	list_del(&stream->curr_buf->queue);
1313	2380	}
1314	2381	}
1315	2382
1316	2383	if (stream->curr_buf) {
1317		- rkcif_write_register(dev, frm0_addr_y,
1318		- stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
1319		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1320		- rkcif_write_register(dev, frm0_addr_uv,
1321		- stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
	2384	+ buff_addr_y = stream->curr_buf->buff_addr[RKCIF_PLANE_Y];
	2385	+ buff_addr_cbcr = stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR];
	2386	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2387	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2388	+ frm0_addr_y,
	2389	+ frm0_addr_uv,
	2390	+ buff_addr_y,
	2391	+ buff_addr_cbcr,
	2392	+ false);
	2393	+ } else {
	2394	+ rkcif_write_register(dev, frm0_addr_y,
	2395	+ stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
	2396	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2397	+ rkcif_write_register(dev, frm0_addr_uv,
	2398	+ stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
	2399	+ }
1322	2400	} else {
1323	2401	if (dummy_buf->vaddr) {
1324		- rkcif_write_register(dev, frm0_addr_y, dummy_buf->dma_addr);
1325		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1326		- rkcif_write_register(dev, frm0_addr_uv, dummy_buf->dma_addr);
	2402	+ buff_addr_y = dummy_buf->dma_addr;
	2403	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2404	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2405	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2406	+ frm0_addr_y,
	2407	+ frm0_addr_uv,
	2408	+ buff_addr_y,
	2409	+ buff_addr_cbcr,
	2410	+ true);
	2411	+ } else {
	2412	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	2413	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2414	+ rkcif_write_register(dev, frm0_addr_uv, buff_addr_cbcr);
	2415	+ }
	2416	+ } else {
	2417	+ if (stream->lack_buf_cnt < 2)
	2418	+ stream->lack_buf_cnt++;
1327	2419	}
1328	2420	}
1329	2421
1330	2422	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1331	2423	stream->next_buf = stream->curr_buf;
1332	2424	if (stream->next_buf) {
1333		- rkcif_write_register(dev, frm1_addr_y,
1334		- stream->next_buf->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
1335		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1336		- rkcif_write_register(dev, frm1_addr_uv,
1337		- stream->next_buf->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	2425	+ buff_addr_y = stream->next_buf->buff_addr[RKCIF_PLANE_Y];
	2426	+ buff_addr_cbcr = stream->next_buf->buff_addr[RKCIF_PLANE_CBCR];
	2427	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2428	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2429	+ frm1_addr_y,
	2430	+ frm1_addr_uv,
	2431	+ buff_addr_y,
	2432	+ buff_addr_cbcr,
	2433	+ false);
	2434	+ } else {
	2435	+ rkcif_write_register(dev, frm1_addr_y,
	2436	+ buff_addr_y + (channel->virtual_width / 2));
	2437	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2438	+ rkcif_write_register(dev, frm1_addr_uv,
	2439	+ buff_addr_cbcr + (channel->virtual_width / 2));
	2440	+ }
1338	2441	}
1339	2442	} else {
1340	2443	if (!stream->next_buf) {
1341	2444	if (!list_empty(&stream->buf_head)) {
1342	2445	stream->next_buf = list_first_entry(&stream->buf_head,
1343	2446	struct rkcif_buffer, queue);
	2447	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev, "%s %d, stream[%d] buf idx %d\n",
	2448	+ __func__, __LINE__, stream->id, stream->next_buf->vb.vb2_buf.index);
1344	2449	list_del(&stream->next_buf->queue);
	2450	+ } else if (stream->curr_buf) {
	2451	+ stream->next_buf = stream->curr_buf;
1345	2452	}
1346	2453	}
1347	2454
1348		- if (stream->next_buf) {
1349		- rkcif_write_register(dev, frm1_addr_y,
1350		- stream->next_buf->buff_addr[RKCIF_PLANE_Y]);
1351		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1352		- rkcif_write_register(dev, frm1_addr_uv,
1353		- stream->next_buf->buff_addr[RKCIF_PLANE_CBCR]);
1354		- } else {
1355		- if (dummy_buf->vaddr) {
	2455	+ if (!stream->next_buf && dummy_buf->vaddr) {
	2456	+ buff_addr_y = dummy_buf->dma_addr;
	2457	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2458	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2459	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2460	+ frm1_addr_y,
	2461	+ frm1_addr_uv,
	2462	+ buff_addr_y,
	2463	+ buff_addr_cbcr,
	2464	+ true);
	2465	+ } else {
1356	2466	rkcif_write_register(dev, frm1_addr_y, dummy_buf->dma_addr);
1357	2467	if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1358	2468	rkcif_write_register(dev, frm1_addr_uv, dummy_buf->dma_addr);
	2469	+ }
	2470	+
	2471	+ } else if (!stream->next_buf && stream->curr_buf) {
	2472	+ stream->next_buf = stream->curr_buf;
	2473	+ if (stream->lack_buf_cnt < 2)
	2474	+ stream->lack_buf_cnt++;
	2475	+ }
	2476	+ if (stream->next_buf) {
	2477	+ buff_addr_y = stream->next_buf->buff_addr[RKCIF_PLANE_Y];
	2478	+ buff_addr_cbcr = stream->next_buf->buff_addr[RKCIF_PLANE_CBCR];
	2479	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2480	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2481	+ frm1_addr_y,
	2482	+ frm1_addr_uv,
	2483	+ buff_addr_y,
	2484	+ buff_addr_cbcr,
	2485	+ false);
	2486	+ } else {
	2487	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	2488	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2489	+ rkcif_write_register(dev, frm1_addr_uv, buff_addr_cbcr);
1359	2490	}
1360	2491	}
1361	2492	}
..	..	@@ -1388,22 +2519,26 @@
1388	2519	}
1389	2520	}
1390	2521	}
1391		-
	2522	+ stream->buf_owner = RKCIF_DMAEN_BY_VICAP;
1392	2523	}
1393	2524
1394	2525	static int rkcif_assign_new_buffer_update(struct rkcif_stream *stream,
1395		- int channel_id)
	2526	+ int channel_id)
1396	2527	{
1397	2528	struct rkcif_device *dev = stream->cifdev;
1398		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2529	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1399	2530	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1400	2531	struct rkcif_buffer *buffer = NULL;
1401	2532	u32 frm_addr_y, frm_addr_uv;
1402	2533	struct csi_channel_info *channel = &dev->channels[channel_id];
	2534	+ struct rkisp_rx_buf *dbufs = NULL;
	2535	+ struct dma_buf *dbuf = NULL;
1403	2536	int ret = 0;
	2537	+ u32 buff_addr_y, buff_addr_cbcr;
1404	2538	unsigned long flags;
1405	2539
1406		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	2540	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2541	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
1407	2542	mbus_cfg->type == V4L2_MBUS_CCP2) {
1408	2543	frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1409	2544	get_reg_index_of_frm0_y_addr(channel_id) :
..	..	@@ -1420,20 +2555,34 @@
1420	2555	get_dvp_reg_index_of_frm1_uv_addr(channel_id);
1421	2556	}
1422	2557
	2558	+ if (stream->to_stop_dma && (stream->dma_en & RKCIF_DMAEN_BY_ISP)) {
	2559	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
	2560	+ goto stop_dma;
	2561	+ }
	2562	+
1423	2563	spin_lock_irqsave(&stream->vbq_lock, flags);
1424	2564	if (!list_empty(&stream->buf_head)) {
	2565	+
1425	2566	if (!dummy_buf->vaddr &&
1426	2567	stream->curr_buf == stream->next_buf &&
1427	2568	stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED)
1428	2569	ret = -EINVAL;
	2570	+
1429	2571	if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2572	+ if (!stream->curr_buf)
	2573	+ ret = -EINVAL;
1430	2574	stream->curr_buf = list_first_entry(&stream->buf_head,
1431	2575	struct rkcif_buffer, queue);
1432	2576	if (stream->curr_buf) {
1433	2577	list_del(&stream->curr_buf->queue);
1434	2578	buffer = stream->curr_buf;
	2579	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	2580	+ "stream[%d] update curr_buf 0x%x, buf idx %d\n",
	2581	+ stream->id, buffer->buff_addr[0], stream->curr_buf->vb.vb2_buf.index);
1435	2582	}
1436	2583	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2584	+ if (!stream->next_buf)
	2585	+ ret = -EINVAL;
1437	2586	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1438	2587	if (stream->next_buf != stream->curr_buf) {
1439	2588	stream->next_buf = stream->curr_buf;
..	..	@@ -1448,14 +2597,17 @@
1448	2597	if (stream->next_buf) {
1449	2598	list_del(&stream->next_buf->queue);
1450	2599	buffer = stream->next_buf;
	2600	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	2601	+ "stream[%d] update next_buf 0x%x, buf idx %d\n",
	2602	+ stream->id, buffer->buff_addr[0], stream->next_buf->vb.vb2_buf.index);
1451	2603	}
1452	2604	}
1453	2605	}
1454	2606	} else {
1455	2607	buffer = NULL;
1456		- if (dummy_buf->vaddr) {
	2608	+ if (!(stream->cur_stream_mode & RKCIF_STREAM_MODE_TOISP) && dummy_buf->vaddr) {
1457	2609	if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1458		- stream->curr_buf = NULL;
	2610	+ stream->curr_buf = NULL;
1459	2611	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1460	2612	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1461	2613	stream->next_buf = stream->curr_buf;
..	..	@@ -1465,56 +2617,123 @@
1465	2617	}
1466	2618	}
1467	2619	} else if (stream->curr_buf != stream->next_buf) {
1468		- if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2620	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY && stream->next_buf) {
1469	2621	stream->curr_buf = stream->next_buf;
1470	2622	buffer = stream->next_buf;
1471		- } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2623	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY && stream->curr_buf) {
1472	2624	stream->next_buf = stream->curr_buf;
1473	2625	buffer = stream->curr_buf;
1474	2626	}
1475		-
	2627	+ if (stream->lack_buf_cnt < 2)
	2628	+ stream->lack_buf_cnt++;
	2629	+ } else {
	2630	+ stream->curr_buf = NULL;
	2631	+ stream->next_buf = NULL;
	2632	+ if (stream->lack_buf_cnt < 2)
	2633	+ stream->lack_buf_cnt++;
1476	2634	}
1477		-
1478	2635	}
1479	2636	stream->frame_phase_cache = stream->frame_phase;
1480		- spin_unlock_irqrestore(&stream->vbq_lock, flags);
1481	2637
1482	2638	if (buffer) {
	2639	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	2640	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
1483	2641	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED &&
1484	2642	stream->frame_phase == CIF_CSI_FRAME1_READY) {
1485		- rkcif_write_register(dev, frm_addr_y,
1486		- buffer->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
1487		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1488		- rkcif_write_register(dev, frm_addr_uv,
1489		- buffer->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	2643	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2644	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2645	+ frm_addr_y,
	2646	+ frm_addr_uv,
	2647	+ buff_addr_y,
	2648	+ buff_addr_cbcr,
	2649	+ false);
	2650	+ } else {
	2651	+ rkcif_write_register(dev, frm_addr_y,
	2652	+ buff_addr_y + (channel->virtual_width / 2));
	2653	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2654	+ rkcif_write_register(dev, frm_addr_uv,
	2655	+ buff_addr_cbcr + (channel->virtual_width / 2));
	2656	+ }
1490	2657	} else {
1491		- rkcif_write_register(dev, frm_addr_y,
1492		- buffer->buff_addr[RKCIF_PLANE_Y]);
1493		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1494		- rkcif_write_register(dev, frm_addr_uv,
1495		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	2658	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2659	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2660	+ frm_addr_y,
	2661	+ frm_addr_uv,
	2662	+ buff_addr_y,
	2663	+ buff_addr_cbcr,
	2664	+ false);
	2665	+ } else {
	2666	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2667	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2668	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2669	+ }
1496	2670	}
1497		- } else {
1498		- if (dummy_buf->vaddr) {
1499		- rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
1500		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1501		- rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
1502		- } else {
1503		- ret = -EINVAL;
	2671	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	2672	+ if (stream->buf_replace_cnt < 2)
	2673	+ stream->buf_replace_cnt++;
	2674	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
	2675	+ stream->next_buf)
	2676	+ dbuf = stream->next_buf->dbuf;
	2677	+ else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
	2678	+ stream->curr_buf)
	2679	+ dbuf = stream->curr_buf->dbuf;
	2680	+
	2681	+ if (dbuf) {
	2682	+ list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list) {
	2683	+ if (dbufs->dbuf == dbuf)
	2684	+ break;
	2685	+ }
	2686	+ }
	2687	+ if (dbufs)
	2688	+ rkcif_s_rx_buffer(stream, dbufs);
1504	2689	}
1505		- v4l2_info(&dev->v4l2_dev,
1506		- "not active buffer, skip current frame, %s stream[%d]\n",
1507		- (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
1508		- mbus_cfg->type == V4L2_MBUS_CCP2) ? "mipi/lvds" : "dvp",
1509		- stream->id);
1510	2690	}
	2691	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
1511	2692	return ret;
	2693	+stop_dma:
	2694	+ if (stream->buf_replace_cnt) {
	2695	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	2696	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2697	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	2698	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2699	+ frm_addr_y, 0,
	2700	+ buff_addr_y, 0, false);
	2701	+ else
	2702	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2703	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
	2704	+ stream->next_buf)
	2705	+ dbuf = stream->next_buf->dbuf;
	2706	+ else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
	2707	+ stream->curr_buf)
	2708	+ dbuf = stream->curr_buf->dbuf;
	2709	+
	2710	+ if (dbuf) {
	2711	+ list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list)
	2712	+ if (dbufs->dbuf == dbuf)
	2713	+ break;
	2714	+ } else {
	2715	+ dbufs = &stream->curr_buf_toisp->dbufs;
	2716	+ }
	2717	+ if (dbufs)
	2718	+ rkcif_s_rx_buffer(stream, dbufs);
	2719	+
	2720	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
	2721	+ stream->curr_buf) {
	2722	+ stream->curr_buf = NULL;
	2723	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
	2724	+ stream->next_buf) {
	2725	+ stream->next_buf = NULL;
	2726	+ }
	2727	+ stream->buf_replace_cnt--;
	2728	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	2729	+ }
	2730	+ return -EINVAL;
1512	2731	}
1513	2732
1514	2733	static int rkcif_get_new_buffer_wake_up_mode(struct rkcif_stream *stream)
1515	2734	{
1516	2735	struct rkcif_device *dev = stream->cifdev;
1517		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2736	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1518	2737	int ret = 0;
1519	2738	unsigned long flags;
1520	2739
..	..	@@ -1535,6 +2754,8 @@
1535	2754	list_del(&stream->next_buf->queue);
1536	2755	}
1537	2756	stream->is_buf_active = true;
	2757	+ if (stream->lack_buf_cnt)
	2758	+ stream->lack_buf_cnt--;
1538	2759	} else {
1539	2760	stream->is_buf_active = false;
1540	2761	if (dummy_buf->vaddr) {
..	..	@@ -1551,8 +2772,15 @@
1551	2772	stream->frame_phase_cache = CIF_CSI_FRAME1_READY;
1552	2773	}
1553	2774	stream->is_buf_active = true;
	2775	+ if (stream->lack_buf_cnt < 2)
	2776	+ stream->lack_buf_cnt++;
1554	2777	} else {
1555		- ret = -EINVAL;
	2778	+ if (dev->chip_id < CHIP_RK3588_CIF)
	2779	+ ret = -EINVAL;
	2780	+ else
	2781	+ ret = 0;
	2782	+ if (stream->lack_buf_cnt < 2)
	2783	+ stream->lack_buf_cnt++;
1556	2784	}
1557	2785	}
1558	2786	spin_unlock_irqrestore(&stream->vbq_lock, flags);
..	..	@@ -1563,15 +2791,18 @@
1563	2791	static int rkcif_update_new_buffer_wake_up_mode(struct rkcif_stream *stream)
1564	2792	{
1565	2793	struct rkcif_device *dev = stream->cifdev;
1566		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2794	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1567	2795	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2796	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
1568	2797	struct rkcif_buffer *buffer = NULL;
1569	2798	u32 frm_addr_y, frm_addr_uv;
	2799	+ u32 buff_addr_y, buff_addr_cbcr;
1570	2800	int channel_id = stream->id;
1571	2801	int ret = 0;
1572	2802	unsigned long flags;
1573	2803
1574		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	2804	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2805	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
1575	2806	mbus_cfg->type == V4L2_MBUS_CCP2) {
1576	2807	frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1577	2808	get_reg_index_of_frm0_y_addr(channel_id) :
..	..	@@ -1596,25 +2827,130 @@
1596	2827	}
1597	2828	spin_unlock_irqrestore(&stream->vbq_lock, flags);
1598	2829	if (buffer) {
1599		- rkcif_write_register(dev, frm_addr_y,
1600		- buffer->buff_addr[RKCIF_PLANE_Y]);
1601		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1602		- rkcif_write_register(dev, frm_addr_uv,
1603		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	2830	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	2831	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	2832	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2833	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y,
	2834	+ frm_addr_uv,
	2835	+ buff_addr_y,
	2836	+ buff_addr_cbcr,
	2837	+ false);
	2838	+ } else {
	2839	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2840	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2841	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2842	+ }
1604	2843	} else {
1605	2844	if (dummy_buf->vaddr) {
1606		- rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
1607		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1608		- rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	2845	+ buff_addr_y = dummy_buf->dma_addr;
	2846	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2847	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2848	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2849	+ frm_addr_y,
	2850	+ frm_addr_uv,
	2851	+ buff_addr_y,
	2852	+ buff_addr_cbcr,
	2853	+ true);
	2854	+ } else {
	2855	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2856	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2857	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2858	+ }
	2859	+ } else {
	2860	+ if (dev->chip_id < CHIP_RK3588_CIF)
	2861	+ ret = -EINVAL;
	2862	+ else
	2863	+ ret = 0;
	2864	+ }
	2865	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	2866	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
	2867	+ }
	2868	+
	2869	+ return ret;
	2870	+}
	2871	+
	2872	+static int rkcif_get_new_buffer_wake_up_mode_rdbk(struct rkcif_stream *stream)
	2873	+{
	2874	+ struct rkcif_rx_buffer *buffer = NULL;
	2875	+ struct rkcif_device *dev = stream->cifdev;
	2876	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2877	+ int ret = 0;
	2878	+ unsigned long flags;
	2879	+ u32 frm_addr_y;
	2880	+ int frame_phase = 0;
	2881	+
	2882	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	2883	+ memset(&stream->toisp_buf_state, 0, sizeof(stream->toisp_buf_state));
	2884	+ if (!list_empty(&stream->rx_buf_head)) {
	2885	+ if (stream->curr_buf_toisp && stream->next_buf_toisp &&
	2886	+ stream->curr_buf_toisp != stream->next_buf_toisp)
	2887	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_ROTATE;
	2888	+ else
	2889	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_LOSS;
	2890	+ if (stream->line_int_cnt % 2) {
	2891	+ buffer = list_first_entry(&stream->rx_buf_head,
	2892	+ struct rkcif_rx_buffer, list);
	2893	+ if (buffer) {
	2894	+ list_del(&buffer->list);
	2895	+ stream->curr_buf_toisp = buffer;
	2896	+ }
	2897	+ frame_phase = CIF_CSI_FRAME0_READY;
	2898	+ } else {
	2899	+ buffer = list_first_entry(&stream->rx_buf_head,
	2900	+ struct rkcif_rx_buffer, list);
	2901	+ if (buffer) {
	2902	+ list_del(&buffer->list);
	2903	+ stream->next_buf_toisp = buffer;
	2904	+ }
	2905	+ frame_phase = CIF_CSI_FRAME1_READY;
	2906	+ }
	2907	+ if (stream->lack_buf_cnt)
	2908	+ stream->lack_buf_cnt--;
	2909	+ } else {
	2910	+ if (stream->lack_buf_cnt < 2)
	2911	+ stream->lack_buf_cnt++;
	2912	+ if (stream->curr_buf_toisp && stream->next_buf_toisp &&
	2913	+ stream->curr_buf_toisp != stream->next_buf_toisp) {
	2914	+ if (stream->line_int_cnt % 2)
	2915	+ stream->curr_buf_toisp = stream->next_buf_toisp;
	2916	+ else
	2917	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	2918	+ buffer = stream->curr_buf_toisp;
	2919	+ ret = 0;
	2920	+ if (stream->cifdev->rdbk_debug)
	2921	+ v4l2_info(&stream->cifdev->v4l2_dev,
	2922	+ "stream[%d] hold buf %x\n",
	2923	+ stream->id,
	2924	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
	2925	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_THESAME;
1609	2926	} else {
1610	2927	ret = -EINVAL;
	2928	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_LOSS;
1611	2929	}
1612		- v4l2_info(&dev->v4l2_dev,
1613		- "not active buffer, skip current frame, %s stream[%d]\n",
1614		- (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
1615		- mbus_cfg->type == V4L2_MBUS_CCP2) ? "mipi/lvds" : "dvp",
1616		- stream->id);
1617	2930	}
	2931	+ if (buffer) {
	2932	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2933	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	2934	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	2935	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2936	+ get_reg_index_of_frm0_y_addr(stream->id) :
	2937	+ get_reg_index_of_frm1_y_addr(stream->id);
	2938	+ } else {
	2939	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2940	+ get_dvp_reg_index_of_frm0_y_addr(stream->id) :
	2941	+ get_dvp_reg_index_of_frm1_y_addr(stream->id);
	2942	+ }
	2943	+ rkcif_write_register(dev, frm_addr_y,
	2944	+ buffer->dummy.dma_addr);
	2945	+ if (dev->rdbk_debug > 1 &&
	2946	+ stream->frame_idx < 15)
	2947	+ v4l2_info(&dev->v4l2_dev,
	2948	+ "stream[%d] rdbk update, seq %d, reg %x, buf %x\n",
	2949	+ stream->id,
	2950	+ stream->frame_idx - 1,
	2951	+ frm_addr_y, (u32)buffer->dummy.dma_addr);
	2952	+ }
	2953	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
1618	2954
1619	2955	return ret;
1620	2956	}
..	..	@@ -1623,7 +2959,7 @@
1623	2959	{
1624	2960	struct rkcif_device *dev = stream->cifdev;
1625	2961	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1626		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2962	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1627	2963	unsigned long flags;
1628	2964
1629	2965	spin_lock_irqsave(&stream->vbq_lock, flags);
..	..	@@ -1658,6 +2994,276 @@
1658	2994	rkcif_assign_new_buffer_init(stream, channel_id);
1659	2995	else
1660	2996	ret = rkcif_assign_new_buffer_update(stream, channel_id);
	2997	+ return ret;
	2998	+}
	2999	+
	3000	+static void rkcif_assign_new_buffer_init_rockit(struct rkcif_stream *stream,
	3001	+ int channel_id)
	3002	+{
	3003	+ struct rkcif_device *dev = stream->cifdev;
	3004	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	3005	+ u32 frm0_addr_y, frm0_addr_uv;
	3006	+ u32 frm1_addr_y, frm1_addr_uv;
	3007	+ unsigned long flags;
	3008	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
	3009	+ struct csi_channel_info *channel = &dev->channels[channel_id];
	3010	+
	3011	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	3012	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	3013	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	3014	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
	3015	+ frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
	3016	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
	3017	+ frm1_addr_uv = get_reg_index_of_frm1_uv_addr(channel_id);
	3018	+ } else {
	3019	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
	3020	+ frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(channel_id);
	3021	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
	3022	+ frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(channel_id);
	3023	+ }
	3024	+
	3025	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	3026	+
	3027	+ if (!stream->curr_buf_rockit) {
	3028	+ if (!list_empty(&stream->rockit_buf_head)) {
	3029	+ stream->curr_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	3030	+ struct rkcif_buffer,
	3031	+ queue);
	3032	+ list_del(&stream->curr_buf_rockit->queue);
	3033	+ }
	3034	+ }
	3035	+
	3036	+ if (stream->curr_buf_rockit) {
	3037	+ rkcif_write_register(dev, frm0_addr_y,
	3038	+ stream->curr_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
	3039	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3040	+ rkcif_write_register(dev, frm0_addr_uv,
	3041	+ stream->curr_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
	3042	+ } else {
	3043	+ if (dummy_buf->vaddr) {
	3044	+ rkcif_write_register(dev, frm0_addr_y, dummy_buf->dma_addr);
	3045	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3046	+ rkcif_write_register(dev, frm0_addr_uv, dummy_buf->dma_addr);
	3047	+ } else {
	3048	+ if (stream->lack_buf_cnt < 2)
	3049	+ stream->lack_buf_cnt++;
	3050	+ }
	3051	+ }
	3052	+
	3053	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	3054	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	3055	+ if (stream->next_buf_rockit) {
	3056	+ rkcif_write_register(dev, frm1_addr_y,
	3057	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
	3058	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3059	+ rkcif_write_register(dev, frm1_addr_uv,
	3060	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	3061	+ }
	3062	+ } else {
	3063	+ if (!stream->next_buf_rockit) {
	3064	+ if (!list_empty(&stream->rockit_buf_head)) {
	3065	+ stream->next_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	3066	+ struct rkcif_buffer, queue);
	3067	+ list_del(&stream->next_buf_rockit->queue);
	3068	+ }
	3069	+ }
	3070	+
	3071	+ if (stream->next_buf_rockit) {
	3072	+ rkcif_write_register(dev, frm1_addr_y,
	3073	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
	3074	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3075	+ rkcif_write_register(dev, frm1_addr_uv,
	3076	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
	3077	+ } else {
	3078	+ if (dummy_buf->vaddr) {
	3079	+ rkcif_write_register(dev, frm1_addr_y, dummy_buf->dma_addr);
	3080	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3081	+ rkcif_write_register(dev, frm1_addr_uv, dummy_buf->dma_addr);
	3082	+ } else {
	3083	+ if (stream->curr_buf_rockit) {
	3084	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	3085	+ rkcif_write_register(dev, frm1_addr_y,
	3086	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
	3087	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3088	+ rkcif_write_register(dev, frm1_addr_uv,
	3089	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
	3090	+ }
	3091	+ if (stream->lack_buf_cnt < 2)
	3092	+ stream->lack_buf_cnt++;
	3093	+ }
	3094	+ }
	3095	+ }
	3096	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	3097	+
	3098	+ stream->is_dvp_yuv_addr_init = true;
	3099	+
	3100	+ /* for BT.656/BT.1120 multi channels function,
	3101	+ * yuv addr of unused channel must be set
	3102	+ */
	3103	+ if (mbus_cfg->type == V4L2_MBUS_BT656) {
	3104	+ int ch_id;
	3105	+
	3106	+ for (ch_id = 0; ch_id < RKCIF_MAX_STREAM_DVP; ch_id++) {
	3107	+ if (dev->stream[ch_id].is_dvp_yuv_addr_init)
	3108	+ continue;
	3109	+ if (dummy_buf->dma_addr) {
	3110	+ rkcif_write_register(dev,
	3111	+ get_dvp_reg_index_of_frm0_y_addr(ch_id),
	3112	+ dummy_buf->dma_addr);
	3113	+ rkcif_write_register(dev,
	3114	+ get_dvp_reg_index_of_frm0_uv_addr(ch_id),
	3115	+ dummy_buf->dma_addr);
	3116	+ rkcif_write_register(dev,
	3117	+ get_dvp_reg_index_of_frm1_y_addr(ch_id),
	3118	+ dummy_buf->dma_addr);
	3119	+ rkcif_write_register(dev,
	3120	+ get_dvp_reg_index_of_frm1_uv_addr(ch_id),
	3121	+ dummy_buf->dma_addr);
	3122	+ }
	3123	+ }
	3124	+ }
	3125	+ stream->buf_owner = RKCIF_DMAEN_BY_ROCKIT;
	3126	+}
	3127	+
	3128	+static int rkcif_assign_new_buffer_update_rockit(struct rkcif_stream *stream,
	3129	+ int channel_id)
	3130	+{
	3131	+ struct rkcif_device *dev = stream->cifdev;
	3132	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
	3133	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	3134	+ struct rkcif_buffer *buffer = NULL;
	3135	+ u32 frm_addr_y, frm_addr_uv;
	3136	+ struct csi_channel_info *channel = &dev->channels[channel_id];
	3137	+ int ret = 0;
	3138	+ unsigned long flags;
	3139	+
	3140	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	3141	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	3142	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	3143	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	3144	+ get_reg_index_of_frm0_y_addr(channel_id) :
	3145	+ get_reg_index_of_frm1_y_addr(channel_id);
	3146	+ frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	3147	+ get_reg_index_of_frm0_uv_addr(channel_id) :
	3148	+ get_reg_index_of_frm1_uv_addr(channel_id);
	3149	+ } else {
	3150	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	3151	+ get_dvp_reg_index_of_frm0_y_addr(channel_id) :
	3152	+ get_dvp_reg_index_of_frm1_y_addr(channel_id);
	3153	+ frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	3154	+ get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
	3155	+ get_dvp_reg_index_of_frm1_uv_addr(channel_id);
	3156	+ }
	3157	+
	3158	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	3159	+ if (!list_empty(&stream->rockit_buf_head)) {
	3160	+
	3161	+ if (!dummy_buf->vaddr &&
	3162	+ stream->curr_buf_rockit == stream->next_buf_rockit &&
	3163	+ stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED)
	3164	+ ret = -EINVAL;
	3165	+
	3166	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	3167	+ if (!stream->curr_buf_rockit)
	3168	+ ret = -EINVAL;
	3169	+ stream->curr_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	3170	+ struct rkcif_buffer, queue);
	3171	+ if (stream->curr_buf_rockit) {
	3172	+ list_del(&stream->curr_buf_rockit->queue);
	3173	+ buffer = stream->curr_buf_rockit;
	3174	+ }
	3175	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	3176	+ if (!stream->next_buf_rockit)
	3177	+ ret = -EINVAL;
	3178	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	3179	+ if (stream->next_buf_rockit != stream->curr_buf_rockit) {
	3180	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	3181	+ buffer = stream->next_buf_rockit;
	3182	+ } else {
	3183	+ buffer = NULL;
	3184	+ }
	3185	+
	3186	+ } else {
	3187	+ stream->next_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	3188	+ struct rkcif_buffer, queue);
	3189	+ if (stream->next_buf_rockit) {
	3190	+ list_del(&stream->next_buf_rockit->queue);
	3191	+ buffer = stream->next_buf_rockit;
	3192	+ }
	3193	+ }
	3194	+ }
	3195	+ } else {
	3196	+ buffer = NULL;
	3197	+ if (dummy_buf->vaddr) {
	3198	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	3199	+ stream->curr_buf_rockit = NULL;
	3200	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	3201	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	3202	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	3203	+ buffer = stream->next_buf_rockit;
	3204	+ } else {
	3205	+ stream->next_buf_rockit = NULL;
	3206	+ }
	3207	+ }
	3208	+ } else if (stream->curr_buf_rockit && stream->next_buf_rockit &&
	3209	+ stream->curr_buf_rockit != stream->next_buf_rockit) {
	3210	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	3211	+ stream->curr_buf_rockit = stream->next_buf_rockit;
	3212	+ buffer = stream->next_buf_rockit;
	3213	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	3214	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	3215	+ buffer = stream->curr_buf_rockit;
	3216	+ }
	3217	+ if (stream->lack_buf_cnt < 2)
	3218	+ stream->lack_buf_cnt++;
	3219	+ } else {
	3220	+ if (stream->lack_buf_cnt < 2)
	3221	+ stream->lack_buf_cnt++;
	3222	+ }
	3223	+ }
	3224	+ stream->frame_phase_cache = stream->frame_phase;
	3225	+
	3226	+ if (buffer) {
	3227	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED &&
	3228	+ stream->frame_phase == CIF_CSI_FRAME1_READY) {
	3229	+ rkcif_write_register(dev, frm_addr_y,
	3230	+ buffer->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
	3231	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3232	+ rkcif_write_register(dev, frm_addr_uv,
	3233	+ buffer->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	3234	+ } else {
	3235	+ rkcif_write_register(dev, frm_addr_y,
	3236	+ buffer->buff_addr[RKCIF_PLANE_Y]);
	3237	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3238	+ rkcif_write_register(dev, frm_addr_uv,
	3239	+ buffer->buff_addr[RKCIF_PLANE_CBCR]);
	3240	+ }
	3241	+ } else {
	3242	+ if (dummy_buf->vaddr) {
	3243	+ rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
	3244	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3245	+ rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	3246	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	3247	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
	3248	+ } else {
	3249	+ ret = -EINVAL;
	3250	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	3251	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
	3252	+ }
	3253	+ }
	3254	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	3255	+ return ret;
	3256	+}
	3257	+
	3258	+static int rkcif_assign_new_buffer_pingpong_rockit(struct rkcif_stream *stream,
	3259	+ int init, int channel_id)
	3260	+{
	3261	+ int ret = 0;
	3262	+
	3263	+ if (init)
	3264	+ rkcif_assign_new_buffer_init_rockit(stream, channel_id);
	3265	+ else
	3266	+ ret = rkcif_assign_new_buffer_update_rockit(stream, channel_id);
1661	3267	return ret;
1662	3268	}
1663	3269
..	..	@@ -1709,7 +3315,7 @@
1709	3315	struct rkmodule_lvds_frm_sync_code *odd_sync_code = NULL;
1710	3316	struct rkmodule_lvds_frm_sync_code *even_sync_code = NULL;
1711	3317
1712		- if (dev->hdr.mode == NO_HDR) {
	3318	+ if (dev->hdr.hdr_mode == NO_HDR \|\| dev->hdr.hdr_mode == HDR_COMPR) {
1713	3319	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LINEAR];
1714	3320	odd_sync_code = &frm_sync_code->odd_sync_code;
1715	3321	even_sync_code = odd_sync_code;
..	..	@@ -1717,12 +3323,12 @@
1717	3323	if (channel->id == RKCIF_STREAM_MIPI_ID0)
1718	3324	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
1719	3325
1720		- if (dev->hdr.mode == HDR_X2) {
	3326	+ if (dev->hdr.hdr_mode == HDR_X2) {
1721	3327	if (channel->id == RKCIF_STREAM_MIPI_ID1)
1722	3328	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_SHORT];
1723	3329	else
1724	3330	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
1725		- } else if (dev->hdr.mode == HDR_X3) {
	3331	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
1726	3332	if (channel->id == RKCIF_STREAM_MIPI_ID1)
1727	3333	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_MEDIUM];
1728	3334	else if (channel->id == RKCIF_STREAM_MIPI_ID2)
..	..	@@ -1758,12 +3364,44 @@
1758	3364	}
1759	3365	}
1760	3366
	3367	+static unsigned char get_csi_fmt_val(const struct cif_input_fmt *cif_fmt_in,
	3368	+ struct csi_channel_info *csi_info)
	3369	+{
	3370	+ unsigned char csi_fmt_val = 0;
	3371	+
	3372	+ if (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 \|\|
	3373	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8) {
	3374	+ switch (csi_info->data_bit) {
	3375	+ case 8:
	3376	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW8;
	3377	+ break;
	3378	+ case 10:
	3379	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW10;
	3380	+ break;
	3381	+ case 12:
	3382	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW12;
	3383	+ break;
	3384	+ default:
	3385	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW12;
	3386	+ break;
	3387	+ }
	3388	+ } else if (cif_fmt_in->csi_fmt_val == CSI_WRDDR_TYPE_RGB888 \|\|
	3389	+ cif_fmt_in->csi_fmt_val == CSI_WRDDR_TYPE_RGB565) {
	3390	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW8;
	3391	+ } else {
	3392	+ csi_fmt_val = cif_fmt_in->csi_fmt_val;
	3393	+ }
	3394	+ return csi_fmt_val;
	3395	+}
	3396	+
1761	3397	static int rkcif_csi_channel_init(struct rkcif_stream *stream,
1762	3398	struct csi_channel_info *channel)
1763	3399	{
1764	3400	struct rkcif_device *dev = stream->cifdev;
	3401	+ struct sditf_priv *priv = dev->sditf[0];
1765	3402	const struct cif_output_fmt *fmt;
1766	3403	u32 fourcc;
	3404	+ int vc = dev->channels[stream->id].vc;
1767	3405
1768	3406	channel->enable = 1;
1769	3407	channel->width = stream->pixm.width;
..	..	@@ -1779,10 +3417,14 @@
1779	3417
1780	3418	if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
1781	3419	channel->crop_st_x = 3 * stream->crop[CROP_SRC_ACT].left;
	3420	+ else if (channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
	3421	+ channel->crop_st_x = 2 * stream->crop[CROP_SRC_ACT].left;
1782	3422	else
1783	3423	channel->crop_st_x = stream->crop[CROP_SRC_ACT].left;
1784	3424
1785	3425	channel->crop_st_y = stream->crop[CROP_SRC_ACT].top;
	3426	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	3427	+ channel->crop_st_y *= dev->sditf_cnt;
1786	3428	channel->width = stream->crop[CROP_SRC_ACT].width;
1787	3429	channel->height = stream->crop[CROP_SRC_ACT].height;
1788	3430	} else {
..	..	@@ -1791,13 +3433,18 @@
1791	3433	channel->crop_en = 0;
1792	3434	}
1793	3435
1794		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
	3436	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	3437	+ channel->height *= dev->sditf_cnt;
	3438	+
	3439	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
1795	3440	if (!fmt) {
1796	3441	v4l2_err(&dev->v4l2_dev, "can not find output format: 0x%x",
1797	3442	stream->pixm.pixelformat);
1798	3443	return -EINVAL;
1799	3444	}
1800	3445
	3446	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	3447	+ channel->width /= channel->capture_info.multi_dev.dev_num;
1801	3448	/*
1802	3449	* for mipi or lvds, when enable compact, the virtual width of raw10/raw12
1803	3450	* needs aligned with :ALIGN(bits_per_pixel * width / 8, 8), if enable 16bit mode
..	..	@@ -1805,13 +3452,24 @@
1805	3452	* writing of ddr, aliged with 256
1806	3453	*/
1807	3454	if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
1808		- fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888) {
1809		- channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
	3455	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	3456	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
	3457	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	3458	+ channel->virtual_width = ALIGN(channel->width * 2 * fmt->raw_bpp / 8, 256);
	3459	+ channel->left_virtual_width = channel->width * fmt->raw_bpp / 8;
	3460	+ } else {
	3461	+ channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
	3462	+ }
1810	3463	} else {
1811		- channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3464	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	3465	+ channel->virtual_width = ALIGN(channel->width * 2 * fmt->bpp[0] / 8, 8);
	3466	+ channel->left_virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3467	+ } else {
	3468	+ channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3469	+ }
1812	3470	}
1813	3471
1814		- if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
	3472	+ if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 \|\| channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
1815	3473	channel->width = channel->width * fmt->bpp[0] / 8;
1816	3474	/*
1817	3475	* rk cif don't support output yuyv fmt data
..	..	@@ -1819,36 +3477,53 @@
1819	3477	* and the width is double Because the real input fmt is
1820	3478	* yuyv
1821	3479	*/
1822		- fourcc = stream->cif_fmt_out->fourcc;
	3480	+ fourcc = stream->cif_fmt_out->fourcc;
1823	3481	if (fourcc == V4L2_PIX_FMT_YUYV \|\| fourcc == V4L2_PIX_FMT_YVYU \|\|
1824	3482	fourcc == V4L2_PIX_FMT_UYVY \|\| fourcc == V4L2_PIX_FMT_VYUY) {
1825		- channel->fmt_val = CSI_WRDDR_TYPE_RAW8;
1826		- channel->width *= 2;
	3483	+ if (dev->chip_id < CHIP_RK3588_CIF) {
	3484	+ channel->fmt_val = CSI_WRDDR_TYPE_RAW8;
	3485	+ channel->width *= 2;
	3486	+ }
1827	3487	channel->virtual_width *= 2;
	3488	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	3489	+ channel->left_virtual_width *= 2;
1828	3490	}
1829	3491	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1830	3492	channel->virtual_width *= 2;
1831	3493	channel->height /= 2;
1832	3494	}
	3495	+ if (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
	3496	+ stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8) {
	3497	+ if (dev->channels[stream->id].data_type)
	3498	+ channel->data_type = dev->channels[stream->id].data_type;
	3499	+ else
	3500	+ channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
	3501	+ channel->cmd_mode_en,
	3502	+ channel->dsi_input);
	3503	+ } else {
	3504	+ channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
	3505	+ channel->cmd_mode_en,
	3506	+ channel->dsi_input);
	3507	+ }
	3508	+ channel->csi_fmt_val = get_csi_fmt_val(stream->cif_fmt_in,
	3509	+ &dev->channels[stream->id]);
1833	3510
1834		- channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
1835		- channel->cmd_mode_en, channel->dsi_input);
1836		-
1837		- if ((dev->hdr.mode == NO_HDR && stream->vc >= 0) \|\|
1838		- (dev->hdr.mode == HDR_X2 && stream->vc > 1) \|\|
1839		- (dev->hdr.mode == HDR_X3 && stream->vc > 2))
1840		- channel->vc = stream->vc;
	3511	+ if (dev->hdr.hdr_mode == NO_HDR \|\|
	3512	+ dev->hdr.hdr_mode == HDR_COMPR \|\|
	3513	+ (dev->hdr.hdr_mode == HDR_X2 && stream->id > 1) \|\|
	3514	+ (dev->hdr.hdr_mode == HDR_X3 && stream->id > 2))
	3515	+ channel->vc = vc < 4 ? vc : channel->id;
1841	3516	else
1842	3517	channel->vc = channel->id;
1843		- v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	3518	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
1844	3519	"%s: channel width %d, height %d, virtual_width %d, vc %d\n", __func__,
1845	3520	channel->width, channel->height, channel->virtual_width, channel->vc);
1846	3521	return 0;
1847	3522	}
1848	3523
1849	3524	static int rkcif_csi_channel_set(struct rkcif_stream *stream,
1850		- struct csi_channel_info *channel,
1851		- enum v4l2_mbus_type mbus_type)
	3525	+ struct csi_channel_info *channel,
	3526	+ enum v4l2_mbus_type mbus_type)
1852	3527	{
1853	3528	unsigned int val = 0x0;
1854	3529	struct rkcif_device *dev = stream->cifdev;
..	..	@@ -1869,10 +3544,9 @@
1869	3544	CSI_DMA_END_INTSTAT(channel->id) \|
1870	3545	CSI_LINE_INTSTAT(channel->id)));
1871	3546
1872		- /* enable id0 frame start int for sof(long frame, for hdr) */
1873		- if (channel->id == RKCIF_STREAM_MIPI_ID0)
1874		- rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
1875		- CSI_START_INTEN(channel->id));
	3547	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3548	+ CSI_START_INTEN(channel->id));
	3549	+
1876	3550	if (detect_stream->is_line_wake_up) {
1877	3551	rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
1878	3552	CSI_LINE_INTEN(channel->id));
..	..	@@ -1891,15 +3565,15 @@
1891	3565	CIF_MIPI_LVDS_SW_HURRY_VALUE_RK1808(0x3) \|
1892	3566	CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808);
1893	3567
1894		- val = CIF_MIPI_LVDS_SW_PRESS_VALUE(0x7) \|
	3568	+ val = CIF_MIPI_LVDS_SW_PRESS_VALUE(0x3) \|
1895	3569	CIF_MIPI_LVDS_SW_PRESS_ENABLE \|
1896		- CIF_MIPI_LVDS_SW_HURRY_VALUE(0x7) \|
	3570	+ CIF_MIPI_LVDS_SW_HURRY_VALUE(0x3) \|
1897	3571	CIF_MIPI_LVDS_SW_HURRY_ENABLE \|
1898	3572	CIF_MIPI_LVDS_SW_WATER_LINE_25 \|
1899	3573	CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
1900		- if (mbus_type == V4L2_MBUS_CSI2) {
	3574	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
1901	3575	val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS;
1902		- } else if (mbus_type == V4L2_MBUS_CCP2) {
	3576	+ } else if (mbus_type == V4L2_MBUS_CCP2) {
1903	3577	if (channel->fmt_val == CSI_WRDDR_TYPE_RAW12)
1904	3578	val \|= CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS;
1905	3579	else if (channel->fmt_val == CSI_WRDDR_TYPE_RAW10)
..	..	@@ -1934,7 +3608,7 @@
1934	3608	RKCIF_YUV_ADDR_STATE_INIT,
1935	3609	channel->id);
1936	3610
1937		- if (mbus_type == V4L2_MBUS_CSI2) {
	3611	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
1938	3612	//need always enable crop
1939	3613	val = CSI_ENABLE_CAPTURE \| channel->fmt_val \|
1940	3614	channel->cmd_mode_en << 4 \| CSI_ENABLE_CROP \|
..	..	@@ -1946,7 +3620,7 @@
1946	3620
1947	3621	if (stream->cifdev->chip_id >= CHIP_RK3568_CIF)
1948	3622	val \|= stream->cif_fmt_in->csi_yuv_order;
1949		- } else if (mbus_type == V4L2_MBUS_CCP2) {
	3623	+ } else if (mbus_type == V4L2_MBUS_CCP2) {
1950	3624	rkcif_csi_set_lvds_sav_eav(stream, channel);
1951	3625	val = LVDS_ENABLE_CAPTURE \| LVDS_MODE(channel->lvds_cfg.mode) \|
1952	3626	LVDS_MAIN_LANE(0) \| LVDS_FID(0) \|
..	..	@@ -1958,15 +3632,405 @@
1958	3632	val &= ~LVDS_COMPACT;
1959	3633	}
1960	3634	if (stream->is_high_align)
1961		- val \|= CSI_ENABLE_MIPI_HIGH_ALIGN;
	3635	+ val \|= CSI_HIGH_ALIGN;
1962	3636	else
1963		- val &= ~CSI_ENABLE_MIPI_HIGH_ALIGN;
	3637	+ val &= ~CSI_HIGH_ALIGN;
1964	3638	rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
1965	3639
	3640	+ dev->intr_mask = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_INTEN);
1966	3641	return 0;
1967	3642	}
1968	3643
1969		-static int rkcif_csi_stream_start(struct rkcif_stream *stream)
	3644	+static int rkcif_dvp_get_input_yuv_order(struct rkcif_stream *stream)
	3645	+{
	3646	+ unsigned int mask;
	3647	+ const struct cif_input_fmt *fmt = stream->cif_fmt_in;
	3648	+
	3649	+ switch (fmt->mbus_code) {
	3650	+ case MEDIA_BUS_FMT_UYVY8_2X8:
	3651	+ mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
	3652	+ break;
	3653	+ case MEDIA_BUS_FMT_VYUY8_2X8:
	3654	+ mask = CSI_YUV_INPUT_ORDER_VYUY >> 11;
	3655	+ break;
	3656	+ case MEDIA_BUS_FMT_YUYV8_2X8:
	3657	+ mask = CSI_YUV_INPUT_ORDER_YUYV >> 11;
	3658	+ break;
	3659	+ case MEDIA_BUS_FMT_YVYU8_2X8:
	3660	+ mask = CSI_YUV_INPUT_ORDER_YVYU >> 11;
	3661	+ break;
	3662	+ default:
	3663	+ mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
	3664	+ break;
	3665	+ }
	3666	+ return mask;
	3667	+}
	3668	+
	3669	+static int rkcif_csi_get_output_type_mask(struct rkcif_stream *stream)
	3670	+{
	3671	+ unsigned int mask;
	3672	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	3673	+
	3674	+ switch (fmt->fourcc) {
	3675	+ case V4L2_PIX_FMT_NV16:
	3676	+ mask = CSI_WRDDR_TYPE_YUV422SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_UYVY;
	3677	+ break;
	3678	+ case V4L2_PIX_FMT_NV61:
	3679	+ mask = CSI_WRDDR_TYPE_YUV422SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_VYUY;
	3680	+ break;
	3681	+ case V4L2_PIX_FMT_NV12:
	3682	+ mask = CSI_WRDDR_TYPE_YUV420SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_UYVY;
	3683	+ break;
	3684	+ case V4L2_PIX_FMT_NV21:
	3685	+ mask = CSI_WRDDR_TYPE_YUV420SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_VYUY;
	3686	+ break;
	3687	+ case V4L2_PIX_FMT_YUYV:
	3688	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_YUYV;
	3689	+ break;
	3690	+ case V4L2_PIX_FMT_YVYU:
	3691	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_YVYU;
	3692	+ break;
	3693	+ case V4L2_PIX_FMT_UYVY:
	3694	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_UYVY;
	3695	+ break;
	3696	+ case V4L2_PIX_FMT_VYUY:
	3697	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_VYUY;
	3698	+ break;
	3699	+ case V4L2_PIX_FMT_RGB24:
	3700	+ case V4L2_PIX_FMT_BGR24:
	3701	+ case V4L2_PIX_FMT_RGB565:
	3702	+ case V4L2_PIX_FMT_BGR666:
	3703	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT;
	3704	+ break;
	3705	+ case V4L2_PIX_FMT_SRGGB8:
	3706	+ case V4L2_PIX_FMT_SGRBG8:
	3707	+ case V4L2_PIX_FMT_SGBRG8:
	3708	+ case V4L2_PIX_FMT_SBGGR8:
	3709	+ case V4L2_PIX_FMT_SRGGB10:
	3710	+ case V4L2_PIX_FMT_SGRBG10:
	3711	+ case V4L2_PIX_FMT_SGBRG10:
	3712	+ case V4L2_PIX_FMT_SBGGR10:
	3713	+ case V4L2_PIX_FMT_SRGGB12:
	3714	+ case V4L2_PIX_FMT_SGRBG12:
	3715	+ case V4L2_PIX_FMT_SGBRG12:
	3716	+ case V4L2_PIX_FMT_SBGGR12:
	3717	+ case V4L2_PIX_FMT_GREY:
	3718	+ case V4L2_PIX_FMT_Y10:
	3719	+ case V4L2_PIX_FMT_Y12:
	3720	+ if (stream->is_compact)
	3721	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT;
	3722	+ else
	3723	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	3724	+ break;
	3725	+ case V4L2_PIX_FMT_SBGGR16:
	3726	+ case V4L2_PIX_FMT_SGBRG16:
	3727	+ case V4L2_PIX_FMT_SGRBG16:
	3728	+ case V4L2_PIX_FMT_SRGGB16:
	3729	+ case V4L2_PIX_FMT_Y16:
	3730	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	3731	+ break;
	3732	+ default:
	3733	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT;
	3734	+ break;
	3735	+ }
	3736	+ return mask;
	3737	+}
	3738	+
	3739	+static int rkcif_lvds_get_output_type_mask(struct rkcif_stream *stream)
	3740	+{
	3741	+ unsigned int mask;
	3742	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	3743	+ int wr_type_offset = 0;
	3744	+ int yuvout_offset = 0;
	3745	+
	3746	+ if (stream->cifdev->chip_id == CHIP_RV1106_CIF) {
	3747	+ wr_type_offset = 17;
	3748	+ yuvout_offset = 9;
	3749	+ }
	3750	+
	3751	+ switch (fmt->fourcc) {
	3752	+ case V4L2_PIX_FMT_NV16:
	3753	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << wr_type_offset) \|
	3754	+ (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
	3755	+ break;
	3756	+ case V4L2_PIX_FMT_NV61:
	3757	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << wr_type_offset) \|
	3758	+ (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
	3759	+ break;
	3760	+ case V4L2_PIX_FMT_NV12:
	3761	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << wr_type_offset) \|
	3762	+ (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
	3763	+ break;
	3764	+ case V4L2_PIX_FMT_NV21:
	3765	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << wr_type_offset) \|
	3766	+ (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
	3767	+ break;
	3768	+ case V4L2_PIX_FMT_YUYV:
	3769	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3770	+ (CSI_YUV_OUTPUT_ORDER_YUYV << yuvout_offset);
	3771	+ break;
	3772	+ case V4L2_PIX_FMT_YVYU:
	3773	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3774	+ (CSI_YUV_OUTPUT_ORDER_YVYU << yuvout_offset);
	3775	+ break;
	3776	+ case V4L2_PIX_FMT_UYVY:
	3777	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3778	+ (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
	3779	+ break;
	3780	+ case V4L2_PIX_FMT_VYUY:
	3781	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3782	+ (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
	3783	+ break;
	3784	+ case V4L2_PIX_FMT_RGB24:
	3785	+ case V4L2_PIX_FMT_BGR24:
	3786	+ case V4L2_PIX_FMT_RGB565:
	3787	+ case V4L2_PIX_FMT_BGR666:
	3788	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
	3789	+ break;
	3790	+ case V4L2_PIX_FMT_SRGGB8:
	3791	+ case V4L2_PIX_FMT_SGRBG8:
	3792	+ case V4L2_PIX_FMT_SGBRG8:
	3793	+ case V4L2_PIX_FMT_SBGGR8:
	3794	+ case V4L2_PIX_FMT_SRGGB10:
	3795	+ case V4L2_PIX_FMT_SGRBG10:
	3796	+ case V4L2_PIX_FMT_SGBRG10:
	3797	+ case V4L2_PIX_FMT_SBGGR10:
	3798	+ case V4L2_PIX_FMT_SRGGB12:
	3799	+ case V4L2_PIX_FMT_SGRBG12:
	3800	+ case V4L2_PIX_FMT_SGBRG12:
	3801	+ case V4L2_PIX_FMT_SBGGR12:
	3802	+ case V4L2_PIX_FMT_GREY:
	3803	+ case V4L2_PIX_FMT_Y10:
	3804	+ case V4L2_PIX_FMT_Y12:
	3805	+ if (stream->is_compact)
	3806	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
	3807	+ else
	3808	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << wr_type_offset;
	3809	+ break;
	3810	+ case V4L2_PIX_FMT_SBGGR16:
	3811	+ case V4L2_PIX_FMT_SGBRG16:
	3812	+ case V4L2_PIX_FMT_SGRBG16:
	3813	+ case V4L2_PIX_FMT_SRGGB16:
	3814	+ case V4L2_PIX_FMT_Y16:
	3815	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << wr_type_offset;
	3816	+ break;
	3817	+ default:
	3818	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
	3819	+ break;
	3820	+ }
	3821	+ return mask;
	3822	+}
	3823	+
	3824	+static void rkcif_modify_frame_skip_config(struct rkcif_stream *stream)
	3825	+{
	3826	+ if (stream->skip_info.skip_to_en) {
	3827	+ rkcif_disable_skip_frame(stream);
	3828	+ rkcif_enable_skip_frame(stream,
	3829	+ stream->skip_info.cap_m,
	3830	+ stream->skip_info.skip_n);
	3831	+ stream->skip_info.skip_to_en = false;
	3832	+ } else if (stream->skip_info.skip_to_dis) {
	3833	+ rkcif_disable_skip_frame(stream);
	3834	+ }
	3835	+}
	3836	+
	3837	+/config reg for rk3588/
	3838	+static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
	3839	+ struct csi_channel_info *channel,
	3840	+ enum v4l2_mbus_type mbus_type, unsigned int mode,
	3841	+ int index)
	3842	+{
	3843	+ unsigned int val = 0x0;
	3844	+ struct rkcif_device *dev = stream->cifdev;
	3845	+ struct rkcif_stream *detect_stream = &dev->stream[0];
	3846	+ struct sditf_priv *priv = dev->sditf[0];
	3847	+ struct rkmodule_capture_info *capture_info = &channel->capture_info;
	3848	+ unsigned int wait_line = 0x3fff;
	3849	+ unsigned int dma_en = 0;
	3850	+ int offset = 0;
	3851	+
	3852	+ if (channel->id >= 4)
	3853	+ return -EINVAL;
	3854	+
	3855	+ if (!channel->enable) {
	3856	+ rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id),
	3857	+ CSI_DISABLE_CAPTURE);
	3858	+ return 0;
	3859	+ }
	3860	+
	3861	+ rkcif_write_register_and(dev, CIF_REG_MIPI_LVDS_INTSTAT,
	3862	+ ~(CSI_START_INTSTAT(channel->id) \|
	3863	+ CSI_DMA_END_INTSTAT(channel->id) \|
	3864	+ CSI_LINE_INTSTAT_V1(channel->id)));
	3865	+
	3866	+ if (!(capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3867	+ index < capture_info->multi_dev.dev_num - 1)) {
	3868	+
	3869	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3870	+ CSI_START_INTEN(channel->id));
	3871	+
	3872	+ if (priv && priv->mode.rdbk_mode && detect_stream->is_line_wake_up) {
	3873	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3874	+ CSI_LINE_INTEN_RK3588(channel->id));
	3875	+ wait_line = dev->wait_line;
	3876	+ }
	3877	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
	3878	+ wait_line << 16 \| wait_line);
	3879	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
	3880	+ wait_line << 16 \| wait_line);
	3881	+
	3882	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3883	+ CSI_DMA_END_INTEN(channel->id));
	3884	+
	3885	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3886	+ CSI_ALL_ERROR_INTEN_V1);
	3887	+ }
	3888	+ if (stream->cifdev->id_use_cnt == 0) {
	3889	+ val = CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(0x3) \|
	3890	+ CIF_MIPI_LVDS_SW_PRESS_ENABLE \|
	3891	+ CIF_MIPI_LVDS_SW_HURRY_VALUE_RK3588(0x3) \|
	3892	+ CIF_MIPI_LVDS_SW_HURRY_ENABLE \|
	3893	+ CIF_MIPI_LVDS_SW_WATER_LINE_25 \|
	3894	+ CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
	3895	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY \|\|
	3896	+ mbus_type == V4L2_MBUS_CSI2_CPHY)
	3897	+ val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
	3898	+ else
	3899	+ val \|= CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
	3900	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
	3901	+ }
	3902	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	3903	+ if (channel->id == 1)
	3904	+ rv1106_sdmmc_get_lock();
	3905	+#endif
	3906	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3907	+ priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE &&
	3908	+ (dev->hdr.hdr_mode == NO_HDR \|\|
	3909	+ (dev->hdr.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	3910	+ (dev->hdr.hdr_mode == HDR_X3 && stream->id == 2)))
	3911	+ offset = channel->capture_info.multi_dev.pixel_offset;
	3912	+
	3913	+ rkcif_write_register(dev, get_reg_index_of_id_ctrl1(channel->id),
	3914	+ (channel->width + offset) \| (channel->height << 16));
	3915	+
	3916	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	3917	+ if (channel->id == 1)
	3918	+ rv1106_sdmmc_put_lock();
	3919	+#endif
	3920	+
	3921	+ if (channel->crop_en)
	3922	+ rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
	3923	+ channel->crop_st_y << 16 \| channel->crop_st_x);
	3924	+
	3925	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	3926	+ rkcif_assign_new_buffer_pingpong(stream,
	3927	+ RKCIF_YUV_ADDR_STATE_INIT,
	3928	+ channel->id);
	3929	+ else if (mode == RKCIF_STREAM_MODE_TOISP \|\|
	3930	+ mode == RKCIF_STREAM_MODE_TOISP_RDBK)
	3931	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	3932	+ RKCIF_YUV_ADDR_STATE_INIT,
	3933	+ channel->id);
	3934	+ else if (mode == RKCIF_STREAM_MODE_ROCKIT)
	3935	+ rkcif_assign_new_buffer_pingpong_rockit(stream,
	3936	+ RKCIF_YUV_ADDR_STATE_INIT,
	3937	+ channel->id);
	3938	+
	3939	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3940	+ index == (capture_info->multi_dev.dev_num - 1) &&
	3941	+ priv && priv->mode.rdbk_mode != RKISP_VICAP_ONLINE)
	3942	+ rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
	3943	+ channel->crop_st_y << 16 \|
	3944	+ (channel->crop_st_x + capture_info->multi_dev.pixel_offset));
	3945	+
	3946	+ rkcif_write_register(dev, get_reg_index_of_frm0_y_vlw(channel->id),
	3947	+ channel->virtual_width);
	3948	+
	3949	+ if (stream->lack_buf_cnt == 2)
	3950	+ stream->dma_en = 0;
	3951	+
	3952	+ if (stream->dma_en) {
	3953	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY \|\|
	3954	+ mbus_type == V4L2_MBUS_CSI2_CPHY)
	3955	+ dma_en = CSI_DMA_ENABLE;
	3956	+ else
	3957	+ dma_en = LVDS_DMAEN_RV1106;
	3958	+ }
	3959	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY \|\|
	3960	+ mbus_type == V4L2_MBUS_CSI2_CPHY) {
	3961	+
	3962	+ if (stream->cifdev->hdr.esp.mode == HDR_LINE_CNT \|\|
	3963	+ stream->cifdev->hdr.esp.mode == HDR_ID_CODE)
	3964	+ channel->vc = 0;
	3965	+
	3966	+ val = CSI_ENABLE_CAPTURE \| dma_en \|
	3967	+ channel->cmd_mode_en << 26 \| CSI_ENABLE_CROP_V1 \|
	3968	+ channel->vc << 8 \| channel->data_type << 10 \|
	3969	+ channel->csi_fmt_val;
	3970	+
	3971	+ val \|= stream->cif_fmt_in->csi_yuv_order;
	3972	+ val \|= rkcif_csi_get_output_type_mask(stream);
	3973	+ if (stream->cifdev->hdr.hdr_mode == NO_HDR \|\|
	3974	+ stream->cifdev->hdr.hdr_mode == HDR_COMPR)
	3975	+ val \|= CSI_NO_HDR;
	3976	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X2)
	3977	+ val \|= CSI_HDR2;
	3978	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X3)
	3979	+ val \|= CSI_HDR3;
	3980	+ if (stream->cifdev->hdr.esp.mode == HDR_NORMAL_VC)
	3981	+ val \|= CSI_HDR_MODE_VC;
	3982	+ else if (stream->cifdev->hdr.esp.mode == HDR_LINE_CNT)
	3983	+ val \|= CSI_HDR_MODE_LINE_CNT;
	3984	+ else if (stream->cifdev->hdr.esp.mode == HDR_ID_CODE)
	3985	+ val \|= CSI_HDR_MODE_LINE_INFO;
	3986	+ if (stream->cifdev->hdr.hdr_mode != NO_HDR &&
	3987	+ stream->cifdev->hdr.esp.mode == HDR_NORMAL_VC)
	3988	+ val \|= CSI_HDR_VC_MODE_PROTECT;
	3989	+ if (stream->is_high_align)
	3990	+ val \|= CSI_HIGH_ALIGN_RK3588;
	3991	+ else
	3992	+ val &= ~CSI_HIGH_ALIGN_RK3588;
	3993	+ rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
	3994	+ rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID0, 0x02410251);
	3995	+ rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID1, 0x02420252);
	3996	+ } else if (mbus_type == V4L2_MBUS_CCP2) {
	3997	+ rkcif_csi_set_lvds_sav_eav(stream, channel);
	3998	+ val = LVDS_ENABLE_CAPTURE_RV1106 \| LVDS_MODE_RV1106(channel->lvds_cfg.mode) \|
	3999	+ LVDS_MAIN_LANE_RV1106(0) \| LVDS_FID_RV1106(0) \|
	4000	+ LVDS_LANES_ENABLED_RV1106(dev->active_sensor->lanes) \|
	4001	+ (channel->csi_fmt_val << 18) \|
	4002	+ rkcif_lvds_get_output_type_mask(stream) \|
	4003	+ (stream->cif_fmt_in->csi_yuv_order << 9) \|
	4004	+ dma_en;
	4005	+ if (stream->cifdev->hdr.hdr_mode == HDR_X3)
	4006	+ val \|= BIT(12);
	4007	+ rkcif_write_register(dev, get_reg_index_of_lvds_id_ctrl0(channel->id), val);
	4008	+ }
	4009	+ if (dev->chip_id >= CHIP_RV1106_CIF)
	4010	+ rkcif_modify_frame_skip_config(stream);
	4011	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4012	+ if (index == (capture_info->multi_dev.dev_num - 1))
	4013	+ stream->cifdev->id_use_cnt++;
	4014	+ } else {
	4015	+ stream->cifdev->id_use_cnt++;
	4016	+ }
	4017	+ if (!(capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	4018	+ index < capture_info->multi_dev.dev_num - 1)) {
	4019	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	4020	+ rkcif_assign_new_buffer_pingpong(stream,
	4021	+ RKCIF_YUV_ADDR_STATE_INIT,
	4022	+ channel->id);
	4023	+ else if (mode == RKCIF_STREAM_MODE_TOISP \|\|
	4024	+ mode == RKCIF_STREAM_MODE_TOISP_RDBK)
	4025	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	4026	+ RKCIF_YUV_ADDR_STATE_INIT,
	4027	+ channel->id);
	4028	+ }
	4029	+ dev->intr_mask = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_INTEN);
	4030	+ return 0;
	4031	+}
	4032	+
	4033	+static int rkcif_csi_stream_start(struct rkcif_stream *stream, unsigned int mode)
1970	4034	{
1971	4035	struct rkcif_device *dev = stream->cifdev;
1972	4036	struct rkcif_sensor_info *active_sensor = dev->active_sensor;
..	..	@@ -1974,23 +4038,22 @@
1974	4038	enum v4l2_mbus_type mbus_type = active_sensor->mbus.type;
1975	4039	struct csi_channel_info *channel;
1976	4040	u32 ret = 0;
	4041	+ int i;
1977	4042
1978		- if (stream->state != RKCIF_STATE_RESET_IN_STREAMING)
	4043	+ if (stream->state < RKCIF_STATE_STREAMING) {
1979	4044	stream->frame_idx = 0;
	4045	+ stream->buf_wake_up_cnt = 0;
	4046	+ stream->frame_phase = 0;
	4047	+ stream->lack_buf_cnt = 0;
	4048	+ stream->is_in_vblank = false;
	4049	+ stream->is_change_toisp = false;
	4050	+ }
1980	4051
1981		- if (mbus_type == V4L2_MBUS_CSI2) {
1982		- rkcif_csi_get_vc_num(dev, flags);
	4052	+ rkcif_csi_get_vc_num(dev, flags);
1983	4053
1984		- channel = &dev->channels[stream->id];
1985		- channel->id = stream->id;
1986		- rkcif_csi_channel_init(stream, channel);
1987		- rkcif_csi_channel_set(stream, channel, V4L2_MBUS_CSI2);
1988		- } else if (mbus_type == V4L2_MBUS_CCP2) {
1989		- rkcif_csi_get_vc_num(dev, flags);
1990		-
1991		- channel = &dev->channels[stream->id];
1992		- channel->id = stream->id;
1993		-
	4054	+ channel = &dev->channels[stream->id];
	4055	+ channel->id = stream->id;
	4056	+ if (mbus_type == V4L2_MBUS_CCP2) {
1994	4057	ret = v4l2_subdev_call(dev->terminal_sensor.sd, core,
1995	4058	ioctl, RKMODULE_GET_LVDS_CFG,
1996	4059	&channel->lvds_cfg);
..	..	@@ -1998,18 +4061,63 @@
1998	4061	v4l2_err(&dev->v4l2_dev, "Err: get lvds config failed!!\n");
1999	4062	return ret;
2000	4063	}
2001		-
2002		- rkcif_csi_channel_init(stream, channel);
2003		- rkcif_csi_channel_set(stream, channel, V4L2_MBUS_CCP2);
2004	4064	}
2005		-
2006		- stream->line_int_cnt = 0;
2007		- if (stream->is_line_wake_up)
2008		- stream->is_can_stop = false;
2009		- else
2010		- stream->is_can_stop = true;
2011		- stream->state = RKCIF_STATE_STREAMING;
2012		- dev->workmode = RKCIF_WORKMODE_PINGPONG;
	4065	+ rkcif_csi_channel_init(stream, channel);
	4066	+ if (stream->state != RKCIF_STATE_STREAMING) {
	4067	+ if (mode == RKCIF_STREAM_MODE_CAPTURE) {
	4068	+ stream->dma_en \|= RKCIF_DMAEN_BY_VICAP;
	4069	+ } else if (mode == RKCIF_STREAM_MODE_TOISP_RDBK) {
	4070	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	4071	+ } else if (mode == RKCIF_STREAM_MODE_TOISP) {
	4072	+ if (dev->hdr.hdr_mode == HDR_X2 &&
	4073	+ stream->id == 0)
	4074	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	4075	+ else if (dev->hdr.hdr_mode == HDR_X3 && (stream->id == 0 \|\| stream->id == 1))
	4076	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	4077	+ } else if (mode == RKCIF_STREAM_MODE_ROCKIT) {
	4078	+ stream->dma_en \|= RKCIF_DMAEN_BY_ROCKIT;
	4079	+ }
	4080	+ if (stream->cifdev->chip_id < CHIP_RK3588_CIF) {
	4081	+ rkcif_csi_channel_set(stream, channel, mbus_type);
	4082	+ } else {
	4083	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4084	+ for (i = 0; i < channel->capture_info.multi_dev.dev_num; i++) {
	4085	+ dev->csi_host_idx = channel->capture_info.multi_dev.dev_idx[i];
	4086	+ rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode, i);
	4087	+ }
	4088	+ } else {
	4089	+ rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode, 0);
	4090	+ }
	4091	+ }
	4092	+ } else {
	4093	+ if (stream->cifdev->chip_id >= CHIP_RK3588_CIF) {
	4094	+ if (mode == RKCIF_STREAM_MODE_CAPTURE) {
	4095	+ stream->to_en_dma = RKCIF_DMAEN_BY_VICAP;
	4096	+ } else if (mode == RKCIF_STREAM_MODE_TOISP_RDBK) {
	4097	+ stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
	4098	+ } else if (mode == RKCIF_STREAM_MODE_TOISP) {
	4099	+ if (dev->hdr.hdr_mode == HDR_X2 &&
	4100	+ stream->id == 0 &&
	4101	+ (!stream->dma_en))
	4102	+ stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
	4103	+ else if (dev->hdr.hdr_mode == HDR_X3 &&
	4104	+ (stream->id == 0 \|\| stream->id == 1) &&
	4105	+ (!stream->dma_en))
	4106	+ stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
	4107	+ } else if (mode == RKCIF_STREAM_MODE_ROCKIT) {
	4108	+ stream->to_en_dma = RKCIF_DMAEN_BY_ROCKIT;
	4109	+ }
	4110	+ }
	4111	+ }
	4112	+ if (stream->state != RKCIF_STATE_STREAMING) {
	4113	+ stream->line_int_cnt = 0;
	4114	+ if (stream->is_line_wake_up)
	4115	+ stream->is_can_stop = false;
	4116	+ else
	4117	+ stream->is_can_stop = true;
	4118	+ stream->state = RKCIF_STATE_STREAMING;
	4119	+ dev->workmode = RKCIF_WORKMODE_PINGPONG;
	4120	+ }
2013	4121
2014	4122	return 0;
2015	4123	}
..	..	@@ -2020,17 +4128,28 @@
2020	4128	struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
2021	4129	u32 val;
2022	4130	int id;
	4131	+ int i = 0;
2023	4132
2024		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	4133	+ stream->cifdev->id_use_cnt--;
	4134	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	4135	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
2025	4136	mbus_cfg->type == V4L2_MBUS_CCP2) {
2026	4137	id = stream->id;
2027	4138	val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(id));
2028		- if (mbus_cfg->type == V4L2_MBUS_CSI2)
2029		- val &= ~CSI_ENABLE_CAPTURE;
	4139	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	4140	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
	4141	+ val &= ~(CSI_ENABLE_CAPTURE \| CSI_DMA_ENABLE);
2030	4142	else
2031	4143	val &= ~LVDS_ENABLE_CAPTURE;
2032	4144
2033		- rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4145	+ if (cif_dev->channels[id].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4146	+ for (i = 0; i < cif_dev->channels[id].capture_info.multi_dev.dev_num; i++) {
	4147	+ cif_dev->csi_host_idx = cif_dev->channels[id].capture_info.multi_dev.dev_idx[i];
	4148	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4149	+ }
	4150	+ } else {
	4151	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4152	+ }
2034	4153
2035	4154	rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT,
2036	4155	CSI_START_INTSTAT(id) \|
..	..	@@ -2042,8 +4161,25 @@
2042	4161	CSI_DMA_END_INTEN(id) \|
2043	4162	CSI_LINE_INTEN(id)));
2044	4163
2045		- rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
2046		- ~CSI_ALL_ERROR_INTEN);
	4164	+ if (stream->cifdev->chip_id < CHIP_RK3588_CIF) {
	4165	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
	4166	+ ~CSI_ALL_ERROR_INTEN);
	4167	+ } else {
	4168	+ if (stream->cifdev->id_use_cnt == 0) {
	4169	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
	4170	+ ~CSI_ALL_ERROR_INTEN_V1);
	4171	+ if (cif_dev->channels[id].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4172	+ for (i = 0; i < cif_dev->channels[id].capture_info.multi_dev.dev_num; i++) {
	4173	+ cif_dev->csi_host_idx = cif_dev->channels[id].capture_info.multi_dev.dev_idx[i];
	4174	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
	4175	+ ~CSI_ENABLE_CAPTURE);
	4176	+ }
	4177	+ } else {
	4178	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
	4179	+ ~CSI_ENABLE_CAPTURE);
	4180	+ }
	4181	+ }
	4182	+ }
2047	4183
2048	4184	} else {
2049	4185	if (atomic_read(&cif_dev->pipe.stream_cnt) == 1) {
..	..	@@ -2053,16 +4189,17 @@
2053	4189	rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, 0x0);
2054	4190	rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, 0x3ff);
2055	4191	rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS, 0x0);
	4192	+ if (IS_ENABLED(CONFIG_CPU_RV1106))
	4193	+ rkcif_config_dvp_pin(cif_dev, false);
2056	4194	}
2057		- stream->is_dvp_yuv_addr_init = false;
2058	4195	}
2059		-
2060	4196	stream->state = RKCIF_STATE_READY;
	4197	+ stream->dma_en = 0;
2061	4198	}
2062	4199
2063	4200	static bool rkcif_is_extending_line_for_height(struct rkcif_device *dev,
2064		- struct rkcif_stream *stream,
2065		- const struct cif_input_fmt *fmt)
	4201	+ struct rkcif_stream *stream,
	4202	+ const struct cif_input_fmt *fmt)
2066	4203	{
2067	4204	bool is_extended = false;
2068	4205	struct rkmodule_hdr_cfg hdr_cfg;
..	..	@@ -2076,17 +4213,17 @@
2076	4213	RKMODULE_GET_HDR_CFG,
2077	4214	&hdr_cfg);
2078	4215	if (!ret)
2079		- dev->hdr.mode = hdr_cfg.hdr_mode;
	4216	+ dev->hdr = hdr_cfg;
2080	4217	else
2081		- dev->hdr.mode = NO_HDR;
	4218	+ dev->hdr.hdr_mode = NO_HDR;
2082	4219	}
2083	4220
2084	4221	if (fmt && fmt->fmt_type == CIF_FMT_TYPE_RAW) {
2085		- if ((dev->hdr.mode == HDR_X2 &&
	4222	+ if ((dev->hdr.hdr_mode == HDR_X2 &&
2086	4223	stream->id == RKCIF_STREAM_MIPI_ID1) \|\|
2087		- (dev->hdr.mode == HDR_X3 &&
	4224	+ (dev->hdr.hdr_mode == HDR_X3 &&
2088	4225	stream->id == RKCIF_STREAM_MIPI_ID2) \|\|
2089		- (dev->hdr.mode == NO_HDR)) {
	4226	+ (dev->hdr.hdr_mode == NO_HDR)) {
2090	4227	is_extended = true;
2091	4228	}
2092	4229	}
..	..	@@ -2134,7 +4271,7 @@
2134	4271	plane_fmt = &pixm->plane_fmt[i];
2135	4272	sizes[i] = plane_fmt->sizeimage / height * h;
2136	4273	}
2137		-
	4274	+ stream->total_buf_num = *num_buffers;
2138	4275	v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s count %d, size %d, extended(%d, %d)\n",
2139	4276	v4l2_type_names[queue->type], *num_buffers, sizes[0],
2140	4277	is_extended, extend_line->is_extended);
..	..	@@ -2143,91 +4280,192 @@
2143	4280	}
2144	4281
2145	4282	static void rkcif_check_buffer_update_pingpong(struct rkcif_stream *stream,
2146		- int channel_id)
	4283	+ int channel_id)
2147	4284	{
2148	4285	struct rkcif_device *dev = stream->cifdev;
2149	4286	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2150	4287	struct rkcif_buffer *buffer = NULL;
2151		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2152		- u32 frm_addr_y, frm_addr_uv;
	4288	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
	4289	+ u32 frm_addr_y = 0, frm_addr_uv = 0;
	4290	+ u32 frm0_addr_y = 0, frm0_addr_uv = 0;
	4291	+ u32 frm1_addr_y = 0, frm1_addr_uv = 0;
	4292	+ u32 buff_addr_y = 0, buff_addr_cbcr = 0;
	4293	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
2153	4294	unsigned long flags;
	4295	+ int frame_phase = 0;
	4296	+ bool is_dual_update_buf = false;
2154	4297
	4298	+ spin_lock_irqsave(&stream->vbq_lock, flags);
2155	4299	if (stream->state == RKCIF_STATE_STREAMING &&
2156		- stream->curr_buf == stream->next_buf &&
2157		- stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED &&
2158		- (!dummy_buf->vaddr)) {
2159		- if (!stream->is_line_wake_up) {
2160		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	4300	+ ((stream->curr_buf == stream->next_buf &&
	4301	+ stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED &&
	4302	+ (!dummy_buf->vaddr)) \|\|
	4303	+ stream->curr_buf == NULL \|\|
	4304	+ stream->next_buf == NULL)) {
	4305	+ frame_phase = stream->frame_phase_cache;
	4306	+ if (!stream->is_line_wake_up \|\|
	4307	+ (stream->is_line_wake_up && stream->frame_idx < 2)) {
	4308	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	4309	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
2161	4310	mbus_cfg->type == V4L2_MBUS_CCP2) {
2162		- frm_addr_y = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2163		- get_reg_index_of_frm0_y_addr(channel_id) :
2164		- get_reg_index_of_frm1_y_addr(channel_id);
2165		- frm_addr_uv = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2166		- get_reg_index_of_frm0_uv_addr(channel_id) :
2167		- get_reg_index_of_frm1_uv_addr(channel_id);
	4311	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
	4312	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
	4313	+ frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
	4314	+ frm1_addr_uv = get_reg_index_of_frm1_uv_addr(channel_id);
2168	4315	} else {
2169		- frm_addr_y = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2170		- get_dvp_reg_index_of_frm0_y_addr(channel_id) :
2171		- get_dvp_reg_index_of_frm1_y_addr(channel_id);
2172		- frm_addr_uv = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2173		- get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
2174		- get_dvp_reg_index_of_frm1_uv_addr(channel_id);
	4316	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
	4317	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
	4318	+ frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(channel_id);
	4319	+ frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(channel_id);
2175	4320	}
2176		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2177		- "stream[%d] update buf in %s, stream->frame_phase_cache %d\n",
2178		- stream->id, __func__, stream->frame_phase_cache);
2179		- spin_lock_irqsave(&stream->vbq_lock, flags);
	4321	+ if (frame_phase & CIF_CSI_FRAME0_READY) {
	4322	+ frm_addr_y = frm0_addr_y;
	4323	+ frm_addr_uv = frm0_addr_uv;
	4324	+ } else {
	4325	+ frm_addr_y = frm1_addr_y;
	4326	+ frm_addr_uv = frm1_addr_uv;
	4327	+ }
	4328	+ if (!stream->dma_en && stream->curr_buf == NULL && stream->next_buf == NULL)
	4329	+ is_dual_update_buf = true;
2180	4330	if (!list_empty(&stream->buf_head)) {
2181		- if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
	4331	+ if (frame_phase == CIF_CSI_FRAME0_READY) {
2182	4332	stream->curr_buf = list_first_entry(&stream->buf_head,
2183	4333	struct rkcif_buffer, queue);
2184	4334	if (stream->curr_buf) {
2185	4335	list_del(&stream->curr_buf->queue);
2186	4336	buffer = stream->curr_buf;
2187	4337	}
2188		- } else if (stream->frame_phase_cache == CIF_CSI_FRAME1_READY) {
2189		- stream->next_buf = list_first_entry(&stream->buf_head,
	4338	+ if (buffer && is_dual_update_buf)
	4339	+ stream->next_buf = buffer;
	4340	+ } else if (frame_phase == CIF_CSI_FRAME1_READY) {
	4341	+ if (stream->next_buf == NULL &&
	4342	+ stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	4343	+ stream->next_buf = stream->curr_buf;
	4344	+ } else {
	4345	+ stream->next_buf = list_first_entry(&stream->buf_head,
2190	4346	struct rkcif_buffer, queue);
2191		- if (stream->next_buf) {
2192		- list_del(&stream->next_buf->queue);
2193		- buffer = stream->next_buf;
	4347	+ if (stream->next_buf) {
	4348	+ list_del(&stream->next_buf->queue);
	4349	+ buffer = stream->next_buf;
	4350	+ }
	4351	+ if (buffer && is_dual_update_buf)
	4352	+ stream->curr_buf = buffer;
	4353	+ }
	4354	+ }
	4355	+ } else {
	4356	+ v4l2_info(&dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
	4357	+ }
	4358	+ if (buffer) {
	4359	+ if (is_dual_update_buf) {
	4360	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	4361	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	4362	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4363	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4364	+ frm0_addr_y,
	4365	+ frm0_addr_uv,
	4366	+ buff_addr_y,
	4367	+ buff_addr_cbcr,
	4368	+ false);
	4369	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4370	+ frm1_addr_y,
	4371	+ frm1_addr_uv,
	4372	+ buff_addr_y,
	4373	+ buff_addr_cbcr,
	4374	+ false);
	4375	+ } else {
	4376	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	4377	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4378	+ rkcif_write_register(dev,
	4379	+ frm0_addr_uv,
	4380	+ buff_addr_cbcr);
	4381	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	4382	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4383	+ rkcif_write_register(dev,
	4384	+ frm1_addr_uv,
	4385	+ buff_addr_cbcr);
	4386	+ }
	4387	+ } else {
	4388	+
	4389	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	4390	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	4391	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4392	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4393	+ frm_addr_y,
	4394	+ frm_addr_uv,
	4395	+ buff_addr_y,
	4396	+ buff_addr_cbcr,
	4397	+ false);
	4398	+ } else {
	4399	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	4400	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4401	+ rkcif_write_register(dev,
	4402	+ frm_addr_uv,
	4403	+ buff_addr_cbcr);
2194	4404	}
2195	4405	}
2196	4406	}
2197		- spin_unlock_irqrestore(&stream->vbq_lock, flags);
2198		- if (buffer) {
2199		- rkcif_write_register(dev, frm_addr_y,
2200		- buffer->buff_addr[RKCIF_PLANE_Y]);
2201		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2202		- rkcif_write_register(dev, frm_addr_uv,
2203		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
2204		- }
2205	4407	} else {
2206		- spin_lock_irqsave(&stream->vbq_lock, flags);
	4408	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4409	+ "%s %d, is_wake_up %d, frame_idx %d\n",
	4410	+ __func__, __LINE__, stream->is_line_wake_up, stream->frame_idx);
2207	4411	if (stream->curr_buf == stream->next_buf) {
2208	4412	if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
2209	4413	stream->curr_buf = list_first_entry(&stream->buf_head,
2210	4414	struct rkcif_buffer, queue);
	4415	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	4416	+ "%s %d, stream[%d] buf idx %d\n",
	4417	+ __func__, __LINE__, stream->id, stream->curr_buf->vb.vb2_buf.index);
2211	4418	if (stream->curr_buf)
2212	4419	list_del(&stream->curr_buf->queue);
2213	4420	} else if (stream->frame_phase_cache == CIF_CSI_FRAME1_READY) {
2214	4421	stream->next_buf = list_first_entry(&stream->buf_head,
2215	4422	struct rkcif_buffer, queue);
	4423	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev,
	4424	+ "%s %d, stream[%d] buf idx %d\n",
	4425	+ __func__, __LINE__, stream->id, stream->next_buf->vb.vb2_buf.index);
2216	4426	if (stream->next_buf)
2217	4427	list_del(&stream->next_buf->queue);
2218	4428	}
2219	4429	stream->is_buf_active = true;
2220	4430	}
2221		- spin_unlock_irqrestore(&stream->vbq_lock, flags);
2222	4431	}
	4432	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4433	+ "%s, stream[%d] update buffer, frame_phase %d, is_stop %s, lack_buf_cnt %d\n",
	4434	+ __func__, stream->id, frame_phase,
	4435	+ (stream->dma_en ? "false" : "true"),
	4436	+ stream->lack_buf_cnt);
	4437	+ if (!stream->dma_en) {
	4438	+ if (stream->to_stop_dma) {
	4439	+ stream->to_stop_dma = 0;
	4440	+ wake_up(&stream->wq_stopped);
	4441	+ } else {
	4442	+ stream->to_en_dma = RKCIF_DMAEN_BY_VICAP;
	4443	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4444	+ "%s stream[%d] start dma capture, frame cnt %d\n",
	4445	+ __func__, stream->id, stream->frame_idx);
	4446	+ }
	4447	+ } else {
	4448	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4449	+ "%s %d, dma_en 0x%x, frame cnt %d\n",
	4450	+ __func__, __LINE__, stream->dma_en, stream->frame_idx);
	4451	+ }
	4452	+ if (stream->lack_buf_cnt)
	4453	+ stream->lack_buf_cnt--;
	4454	+
	4455	+ } else {
	4456	+ v4l2_info(&dev->v4l2_dev, "%s %d, state %d, curr_buf %p, next_buf %p\n",
	4457	+ __func__, __LINE__, stream->state, stream->curr_buf, stream->next_buf);
2223	4458	}
	4459	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	4460	+ if (stream->to_en_dma)
	4461	+ rkcif_enable_dma_capture(stream, true);
2224	4462	}
2225	4463
2226	4464	/*
2227	4465	* The vb2_buffer are stored in rkcif_buffer, in order to unify
2228	4466	* mplane buffer and none-mplane buffer.
2229	4467	*/
2230		-static void rkcif_buf_queue(struct vb2_buffer *vb)
	4468	+void rkcif_buf_queue(struct vb2_buffer *vb)
2231	4469	{
2232	4470	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2233	4471	struct rkcif_buffer *cifbuf = to_rkcif_buffer(vbuf);
..	..	@@ -2236,8 +4474,32 @@
2236	4474	struct v4l2_pix_format_mplane *pixm = &stream->pixm;
2237	4475	const struct cif_output_fmt *fmt = stream->cif_fmt_out;
2238	4476	struct rkcif_hw *hw_dev = stream->cifdev->hw_dev;
	4477	+ struct rkcif_tools_buffer *tools_buf;
	4478	+ struct rkcif_tools_vdev *tools_vdev = stream->tools_vdev;
2239	4479	unsigned long flags;
2240	4480	int i;
	4481	+ bool is_find_tools_buf = false;
	4482	+
	4483	+ if (tools_vdev) {
	4484	+ spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
	4485	+ if (!list_empty(&tools_vdev->src_buf_head)) {
	4486	+ list_for_each_entry(tools_buf, &tools_vdev->src_buf_head, list) {
	4487	+ if (tools_buf->vb == vbuf) {
	4488	+ is_find_tools_buf = true;
	4489	+ break;
	4490	+ }
	4491	+ }
	4492	+ if (is_find_tools_buf) {
	4493	+ if (tools_buf->use_cnt)
	4494	+ tools_buf->use_cnt--;
	4495	+ if (tools_buf->use_cnt) {
	4496	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	4497	+ return;
	4498	+ }
	4499	+ }
	4500	+ }
	4501	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	4502	+ }
2241	4503
2242	4504	memset(cifbuf->buff_addr, 0, sizeof(cifbuf->buff_addr));
2243	4505	/* If mplanes > 1, every c-plane has its own m-plane,
..	..	@@ -2246,7 +4508,7 @@
2246	4508	for (i = 0; i < fmt->mplanes; i++) {
2247	4509	void *addr = vb2_plane_vaddr(vb, i);
2248	4510
2249		- if (hw_dev->iommu_en) {
	4511	+ if (hw_dev->is_dma_sg_ops) {
2250	4512	struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, i);
2251	4513
2252	4514	cifbuf->buff_addr[i] = sg_dma_address(sgt->sgl);
..	..	@@ -2255,7 +4517,7 @@
2255	4517	}
2256	4518	if (rkcif_debug && addr && !hw_dev->iommu_en) {
2257	4519	memset(addr, 0, pixm->plane_fmt[i].sizeimage);
2258		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
	4520	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
2259	4521	"Clear buffer, size: 0x%08x\n",
2260	4522	pixm->plane_fmt[i].sizeimage);
2261	4523	}
..	..	@@ -2269,40 +4531,297 @@
2269	4531	spin_lock_irqsave(&stream->vbq_lock, flags);
2270	4532	list_add_tail(&cifbuf->queue, &stream->buf_head);
2271	4533	spin_unlock_irqrestore(&stream->vbq_lock, flags);
2272		- if (stream->cifdev->workmode == RKCIF_WORKMODE_PINGPONG)
	4534	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP && (!cifbuf->dbuf)) {
	4535	+ struct rkisp_rx_buf *dbufs = NULL;
	4536	+
	4537	+ dbufs = kzalloc(sizeof(struct rkisp_rx_buf), GFP_KERNEL);
	4538	+
	4539	+ memset(dbufs, 0, sizeof(struct rkisp_rx_buf));
	4540	+ if (stream->cifdev->hdr.hdr_mode == HDR_X2 && stream->id == 0)
	4541	+ dbufs->type = BUF_MIDDLE;
	4542	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 0)
	4543	+ dbufs->type = BUF_LONG;
	4544	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 1)
	4545	+ dbufs->type = BUF_MIDDLE;
	4546	+ cifbuf->dbuf = hw_dev->mem_ops->get_dmabuf(vb->planes[0].mem_priv, O_RDWR);
	4547	+ if (cifbuf->dbuf)
	4548	+ dbufs->dbuf = cifbuf->dbuf;
	4549	+ list_add_tail(&dbufs->list, &stream->rx_buf_head_vicap);
	4550	+ }
	4551	+ if (stream->cifdev->workmode == RKCIF_WORKMODE_PINGPONG &&
	4552	+ stream->lack_buf_cnt &&
	4553	+ stream->cur_stream_mode & RKCIF_STREAM_MODE_CAPTURE)
2273	4554	rkcif_check_buffer_update_pingpong(stream, stream->id);
	4555	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4556	+ "stream[%d] buf queue, index: %d, dma_addr 0x%x\n",
	4557	+ stream->id, vb->index, cifbuf->buff_addr[0]);
	4558	+ atomic_inc(&stream->buf_cnt);
	4559	+}
	4560	+
	4561	+void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num)
	4562	+{
	4563	+ struct rkcif_rx_buffer *buf;
	4564	+ struct rkcif_device *dev = stream->cifdev;
	4565	+ struct sditf_priv *priv = dev->sditf[0];
	4566	+ struct v4l2_subdev *sd;
	4567	+ int i = 0;
	4568	+ unsigned long flags;
	4569	+ phys_addr_t resmem_free_start;
	4570	+ phys_addr_t resmem_free_end;
	4571	+ u32 share_head_size = 0;
	4572	+
	4573	+ if (!priv)
	4574	+ return;
	4575	+
	4576	+ sd = get_rkisp_sd(dev->sditf[0]);
	4577	+ if (!sd)
	4578	+ return;
	4579	+
	4580	+ if (dev->is_rtt_suspend && dev->is_thunderboot) {
	4581	+ stream->curr_buf_toisp = NULL;
	4582	+ stream->next_buf_toisp = NULL;
	4583	+ INIT_LIST_HEAD(&stream->rx_buf_head);
	4584	+
	4585	+ for (i = 0; i < buf_num; i++) {
	4586	+ buf = &stream->rx_buf[i];
	4587	+ if (buf->dbufs.is_init)
	4588	+ v4l2_subdev_call(sd, core, ioctl,
	4589	+ RKISP_VICAP_CMD_RX_BUFFER_FREE, &buf->dbufs);
	4590	+ buf->dummy.is_free = true;
	4591	+ }
	4592	+
	4593	+ if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
	4594	+ share_head_size = dev->thunderboot_sensor_num * sizeof(struct rkisp32_thunderboot_resmem_head);
	4595	+ if (share_head_size != dev->share_mem_size)
	4596	+ v4l2_info(&stream->cifdev->v4l2_dev,
	4597	+ "share mem head error, rtt head size %d, arm head size %d\n",
	4598	+ dev->share_mem_size, share_head_size);
	4599	+ resmem_free_start = dev->resmem_pa + share_head_size + dev->nr_buf_size;
	4600	+ resmem_free_end = dev->resmem_pa + dev->resmem_size;
	4601	+ v4l2_info(&stream->cifdev->v4l2_dev,
	4602	+ "free reserved mem start 0x%x, end 0x%x, share_head_size 0x%x, nr_buf_size 0x%x\n",
	4603	+ (u32)resmem_free_start, (u32)resmem_free_end, share_head_size, dev->nr_buf_size);
	4604	+ free_reserved_area(phys_to_virt(resmem_free_start),
	4605	+ phys_to_virt(resmem_free_end),
	4606	+ -1, "rkisp_thunderboot");
	4607	+ }
	4608	+ atomic_set(&stream->buf_cnt, 0);
	4609	+ stream->total_buf_num = 0;
	4610	+ stream->rx_buf_num = 0;
	4611	+
	4612	+ return;
	4613	+ }
	4614	+
	4615	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	4616	+ stream->curr_buf_toisp = NULL;
	4617	+ stream->next_buf_toisp = NULL;
	4618	+ INIT_LIST_HEAD(&stream->rx_buf_head);
	4619	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	4620	+
	4621	+ if (dev->is_thunderboot)
	4622	+ spin_lock_irqsave(&dev->buffree_lock, flags);
	4623	+ for (i = 0; i < buf_num; i++) {
	4624	+ buf = &stream->rx_buf[i];
	4625	+ if (buf->dummy.is_free)
	4626	+ continue;
	4627	+ if (buf->dbufs.is_init)
	4628	+ v4l2_subdev_call(sd, core, ioctl,
	4629	+ RKISP_VICAP_CMD_RX_BUFFER_FREE, &buf->dbufs);
	4630	+ if (!dev->is_thunderboot)
	4631	+ rkcif_free_buffer(dev, &buf->dummy);
	4632	+ else
	4633	+ list_add_tail(&buf->list_free, &priv->buf_free_list);
	4634	+ atomic_dec(&stream->buf_cnt);
	4635	+ stream->total_buf_num--;
	4636	+ }
	4637	+ stream->rx_buf_num = 0;
	4638	+
	4639	+ if (dev->is_thunderboot) {
	4640	+ spin_unlock_irqrestore(&dev->buffree_lock, flags);
	4641	+ schedule_work(&priv->buffree_work.work);
	4642	+ }
	4643	+ stream->dma_en &= ~RKCIF_DMAEN_BY_ISP;
2274	4644	v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2275		- "stream[%d] buf queue, index: %d\n",
2276		- stream->id, vb->index);
	4645	+ "free rx_buf, buf_num %d\n", buf_num);
	4646	+}
	4647	+
	4648	+static void rkcif_get_resmem_head(struct rkcif_device *cif_dev);
	4649	+int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num)
	4650	+{
	4651	+ struct rkcif_device *dev = stream->cifdev;
	4652	+ struct v4l2_pix_format_mplane *pixm = &stream->pixm;
	4653	+ struct rkcif_dummy_buffer *dummy;
	4654	+ struct rkcif_rx_buffer *buf;
	4655	+ struct sditf_priv *priv = dev->sditf[0];
	4656	+ int frm_type = 0;
	4657	+ int i = 0;
	4658	+ int ret = 0;
	4659	+
	4660	+ if (!priv)
	4661	+ return -EINVAL;
	4662	+
	4663	+ if (buf_num > RKISP_VICAP_BUF_CNT_MAX)
	4664	+ return -EINVAL;
	4665	+
	4666	+ if (dev->hdr.hdr_mode == NO_HDR) {
	4667	+ if (stream->id == 0)
	4668	+ frm_type = BUF_SHORT;
	4669	+ else
	4670	+ return -EINVAL;
	4671	+ } else if (dev->hdr.hdr_mode == HDR_X2) {
	4672	+ if (stream->id == 0)
	4673	+ frm_type = BUF_MIDDLE;
	4674	+ else if (stream->id == 1)
	4675	+ frm_type = BUF_SHORT;
	4676	+ else
	4677	+ return -EINVAL;
	4678	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
	4679	+ if (stream->id == 0)
	4680	+ frm_type = BUF_LONG;
	4681	+ else if (stream->id == 1)
	4682	+ frm_type = BUF_MIDDLE;
	4683	+ else if (stream->id == 2)
	4684	+ frm_type = BUF_SHORT;
	4685	+ else
	4686	+ return -EINVAL;
	4687	+ }
	4688	+ while (true) {
	4689	+ buf = &stream->rx_buf[i];
	4690	+ memset(buf, 0, sizeof(*buf));
	4691	+ dummy = &buf->dummy;
	4692	+ dummy->size = pixm->plane_fmt[0].sizeimage;
	4693	+ dummy->is_need_vaddr = true;
	4694	+ dummy->is_need_dbuf = true;
	4695	+ if (dev->is_thunderboot) {
	4696	+ if (i == 0)
	4697	+ rkcif_get_resmem_head(dev);
	4698	+ buf->buf_idx = i;
	4699	+ ret = rkcif_alloc_reserved_mem_buf(dev, buf);
	4700	+ if (ret) {
	4701	+ stream->rx_buf_num = i;
	4702	+ v4l2_info(&dev->v4l2_dev,
	4703	+ "reserved mem support alloc buf num %d, require buf num %d\n",
	4704	+ i, buf_num);
	4705	+ break;
	4706	+ }
	4707	+ if (dev->rdbk_debug)
	4708	+ v4l2_info(&dev->v4l2_dev,
	4709	+ "stream[%d] buf addr 0x%llx\n",
	4710	+ stream->id, (u64)dummy->dma_addr);
	4711	+ } else {
	4712	+ ret = rkcif_alloc_buffer(dev, dummy);
	4713	+ if (ret) {
	4714	+ stream->rx_buf_num = i;
	4715	+ v4l2_info(&dev->v4l2_dev,
	4716	+ "alloc buf num %d, require buf num %d\n",
	4717	+ i, buf_num);
	4718	+ break;
	4719	+ }
	4720	+ buf->dbufs.dbuf = dummy->dbuf;
	4721	+ }
	4722	+ buf->dbufs.is_init = false;
	4723	+ buf->dbufs.type = frm_type;
	4724	+ list_add_tail(&buf->list, &stream->rx_buf_head);
	4725	+ dummy->is_free = false;
	4726	+ if (stream->is_compact)
	4727	+ buf->dbufs.is_uncompact = false;
	4728	+ else
	4729	+ buf->dbufs.is_uncompact = true;
	4730	+ if (priv && i == 0) {
	4731	+ buf->dbufs.is_first = true;
	4732	+ if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	4733	+ rkcif_s_rx_buffer(stream, &buf->dbufs);
	4734	+ }
	4735	+ i++;
	4736	+ if (!dev->is_thunderboot && i >= buf_num) {
	4737	+ stream->rx_buf_num = buf_num;
	4738	+ break;
	4739	+ } else if (i >= RKISP_VICAP_BUF_CNT_MAX) {
	4740	+ stream->rx_buf_num = i;
	4741	+ v4l2_info(&dev->v4l2_dev,
	4742	+ "reserved mem alloc buf num %d\n", i);
	4743	+ break;
	4744	+ }
	4745	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
	4746	+ "init rx_buf,dma_addr 0x%llx size: 0x%x\n",
	4747	+ (u64)dummy->dma_addr, pixm->plane_fmt[0].sizeimage);
	4748	+ }
	4749	+ if (stream->rx_buf_num) {
	4750	+ stream->total_buf_num = stream->rx_buf_num;
	4751	+ atomic_set(&stream->buf_cnt, stream->rx_buf_num);
	4752	+ return 0;
	4753	+ } else {
	4754	+ return -EINVAL;
	4755	+ }
2277	4756	}
2278	4757
2279	4758	static int rkcif_create_dummy_buf(struct rkcif_stream *stream)
2280	4759	{
2281		- u32 fourcc;
2282	4760	struct rkcif_device *dev = stream->cifdev;
2283		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2284		- struct rkcif_hw *hw_dev = dev->hw_dev;
	4761	+ struct rkcif_hw *hw = dev->hw_dev;
	4762	+ struct rkcif_dummy_buffer *dummy_buf = &hw->dummy_buf;
	4763	+ struct rkcif_device *tmp_dev = NULL;
	4764	+ struct v4l2_subdev_frame_interval_enum fie;
	4765	+ struct v4l2_subdev_format fmt;
	4766	+ u32 max_size = 0;
	4767	+ u32 size = 0;
	4768	+ int ret = 0;
	4769	+ int i, j;
2285	4770
2286		- /* get a maximum plane size */
2287		- dummy_buf->size = max3(stream->pixm.plane_fmt[0].bytesperline *
2288		- stream->pixm.height,
2289		- stream->pixm.plane_fmt[1].sizeimage,
2290		- stream->pixm.plane_fmt[2].sizeimage);
2291		- /*
2292		- * rk cif don't support output yuyv fmt data
2293		- * if user request yuyv fmt, the input mode must be RAW8
2294		- * and the width is double Because the real input fmt is
2295		- * yuyv
2296		- */
2297		- fourcc = stream->cif_fmt_out->fourcc;
2298		- if (fourcc == V4L2_PIX_FMT_YUYV \|\| fourcc == V4L2_PIX_FMT_YVYU \|\|
2299		- fourcc == V4L2_PIX_FMT_UYVY \|\| fourcc == V4L2_PIX_FMT_VYUY)
2300		- dummy_buf->size *= 2;
	4771	+ for (i = 0; i < hw->dev_num; i++) {
	4772	+ tmp_dev = hw->cif_dev[i];
	4773	+ if (tmp_dev->terminal_sensor.sd) {
	4774	+ for (j = 0; j < 32; j++) {
	4775	+ memset(&fie, 0, sizeof(fie));
	4776	+ fie.index = j;
	4777	+ fie.pad = 0;
	4778	+ fie.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	4779	+ ret = v4l2_subdev_call(tmp_dev->terminal_sensor.sd,
	4780	+ pad, enum_frame_interval,
	4781	+ NULL, &fie);
	4782	+ if (!ret) {
	4783	+ if (fie.code == MEDIA_BUS_FMT_RGB888_1X24 \|\|
	4784	+ fie.code == MEDIA_BUS_FMT_BGR888_1X24 \|\|
	4785	+ fie.code == MEDIA_BUS_FMT_GBR888_1X24)
	4786	+ size = fie.width * fie.height * 3;
	4787	+ else
	4788	+ size = fie.width * fie.height * 2;
	4789	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
	4790	+ "%s enum fmt, width %d, height %d\n",
	4791	+ __func__, fie.width, fie.height);
	4792	+ } else {
	4793	+ break;
	4794	+ }
	4795	+ if (size > max_size)
	4796	+ max_size = size;
	4797	+ }
	4798	+ } else {
	4799	+ continue;
	4800	+ }
	4801	+ }
2301	4802
2302		- dummy_buf->vaddr = dma_alloc_coherent(hw_dev->dev, dummy_buf->size,
2303		- &dummy_buf->dma_addr,
2304		- GFP_KERNEL);
2305		- if (!dummy_buf->vaddr) {
	4803	+ if (max_size == 0 && dev->terminal_sensor.sd) {
	4804	+ fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	4805	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	4806	+ pad, get_fmt, NULL, &fmt);
	4807	+ if (!ret) {
	4808	+ if (fmt.format.code == MEDIA_BUS_FMT_RGB888_1X24 \|\|
	4809	+ fmt.format.code == MEDIA_BUS_FMT_BGR888_1X24 \|\|
	4810	+ fmt.format.code == MEDIA_BUS_FMT_GBR888_1X24)
	4811	+ size = fmt.format.width * fmt.format.height * 3;
	4812	+ else
	4813	+ size = fmt.format.width * fmt.format.height * 2;
	4814	+ if (size > max_size)
	4815	+ max_size = size;
	4816	+ }
	4817	+ }
	4818	+
	4819	+ dummy_buf->size = max_size;
	4820	+
	4821	+ dummy_buf->is_need_vaddr = true;
	4822	+ dummy_buf->is_need_dbuf = true;
	4823	+ ret = rkcif_alloc_buffer(dev, dummy_buf);
	4824	+ if (ret) {
2306	4825	v4l2_err(&dev->v4l2_dev,
2307	4826	"Failed to allocate the memory for dummy buffer\n");
2308	4827	return -ENOMEM;
..	..	@@ -2311,18 +4830,16 @@
2311	4830	v4l2_info(&dev->v4l2_dev, "Allocate dummy buffer, size: 0x%08x\n",
2312	4831	dummy_buf->size);
2313	4832
2314		- return 0;
	4833	+ return ret;
2315	4834	}
2316	4835
2317	4836	static void rkcif_destroy_dummy_buf(struct rkcif_stream *stream)
2318	4837	{
2319	4838	struct rkcif_device *dev = stream->cifdev;
2320		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2321		- struct rkcif_hw *hw_dev = dev->hw_dev;
	4839	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2322	4840
2323	4841	if (dummy_buf->vaddr)
2324		- dma_free_coherent(hw_dev->dev, dummy_buf->size,
2325		- dummy_buf->vaddr, dummy_buf->dma_addr);
	4842	+ rkcif_free_buffer(dev, dummy_buf);
2326	4843	dummy_buf->dma_addr = 0;
2327	4844	dummy_buf->vaddr = NULL;
2328	4845	}
..	..	@@ -2336,7 +4853,7 @@
2336	4853	if (dev->luma_vdev.enable)
2337	4854	rkcif_stop_luma(&dev->luma_vdev);
2338	4855
2339		- if (dev->hdr.mode != NO_HDR) {
	4856	+ if (dev->hdr.hdr_mode != NO_HDR) {
2340	4857	if (dev->chip_id == CHIP_RK1808_CIF) {
2341	4858	val = rkcif_read_register(dev, CIF_REG_MIPI_WATER_LINE);
2342	4859	val \|= CIF_MIPI_LVDS_SW_DMA_IDLE_RK1808;
..	..	@@ -2360,14 +4877,22 @@
2360	4877	reset_control_deassert(cif_hw->cif_rst[i]);
2361	4878
2362	4879	if (cif_hw->iommu_en) {
2363		- struct iommu_domain *domain;
2364		-
2365		- domain = iommu_get_domain_for_dev(cif_hw->dev);
2366		- if (domain) {
2367		- iommu_detach_device(domain, cif_hw->dev);
2368		- iommu_attach_device(domain, cif_hw->dev);
2369		- }
	4880	+ rockchip_iommu_disable(cif_hw->dev);
	4881	+ rockchip_iommu_enable(cif_hw->dev);
2370	4882	}
	4883	+}
	4884	+
	4885	+void rkcif_do_soft_reset(struct rkcif_device *dev)
	4886	+{
	4887	+ if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	4888	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	4889	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)
	4890	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
	4891	+ else
	4892	+ rkcif_write_register_or(dev, CIF_REG_DVP_CTRL, 0x000A0000);
	4893	+ usleep_range(10, 20);
	4894	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
	4895	+ "vicap do soft reset 0x%x\n", 0x000A0000);
2371	4896	}
2372	4897
2373	4898	static void rkcif_release_rdbk_buf(struct rkcif_stream *stream)
..	..	@@ -2412,9 +4937,52 @@
2412	4937
2413	4938	}
2414	4939
2415		-static void rkcif_stop_streaming(struct vb2_queue *queue)
	4940	+static void rkcif_detach_sync_mode(struct rkcif_device *cif_dev)
2416	4941	{
2417		- struct rkcif_stream *stream = queue->drv_priv;
	4942	+ int i = 0;
	4943	+ struct rkcif_hw *hw = cif_dev->hw_dev;
	4944	+ struct rkcif_device *tmp_dev;
	4945	+ struct rkcif_multi_sync_config *sync_config;
	4946	+
	4947	+ if ((!cif_dev->sync_cfg.type) \|\|
	4948	+ (atomic_read(&cif_dev->pipe.stream_cnt) != 0))
	4949	+ return;
	4950	+ mutex_lock(&hw->dev_lock);
	4951	+ memset(&cif_dev->sync_cfg, 0, sizeof(cif_dev->sync_cfg));
	4952	+ sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
	4953	+ sync_config->streaming_cnt--;
	4954	+ if (cif_dev->sync_cfg.type == EXTERNAL_MASTER_MODE) {
	4955	+ for (i = 0; i < sync_config->ext_master.count; i++) {
	4956	+ tmp_dev = sync_config->ext_master.cif_dev[i];
	4957	+ if (tmp_dev == cif_dev) {
	4958	+ sync_config->ext_master.is_streaming[i] = false;
	4959	+ break;
	4960	+ }
	4961	+ }
	4962	+ }
	4963	+ if (cif_dev->sync_cfg.type == INTERNAL_MASTER_MODE)
	4964	+ sync_config->int_master.is_streaming[0] = false;
	4965	+ if (cif_dev->sync_cfg.type == SLAVE_MODE) {
	4966	+ for (i = 0; i < sync_config->slave.count; i++) {
	4967	+ tmp_dev = sync_config->slave.cif_dev[i];
	4968	+ if (tmp_dev == cif_dev) {
	4969	+ sync_config->slave.is_streaming[i] = false;
	4970	+ break;
	4971	+ }
	4972	+ }
	4973	+ }
	4974	+
	4975	+ if (!sync_config->streaming_cnt && sync_config->is_attach) {
	4976	+ sync_config->is_attach = false;
	4977	+ sync_config->mode = RKCIF_NOSYNC_MODE;
	4978	+ sync_config->dev_cnt = 0;
	4979	+ }
	4980	+ mutex_unlock(&hw->dev_lock);
	4981	+}
	4982	+
	4983	+void rkcif_do_stop_stream(struct rkcif_stream *stream,
	4984	+ unsigned int mode)
	4985	+{
2418	4986	struct rkcif_vdev_node *node = &stream->vnode;
2419	4987	struct rkcif_device *dev = stream->cifdev;
2420	4988	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
..	..	@@ -2424,95 +4992,172 @@
2424	4992	bool can_reset = true;
2425	4993	int i;
2426	4994	unsigned long flags;
	4995	+ u32 vblank = 0;
	4996	+ u32 frame_time_ns = 0;
	4997	+ u64 cur_time = 0;
	4998	+ u64 fs_time = 0;
2427	4999
2428	5000	mutex_lock(&dev->stream_lock);
2429	5001
2430		- v4l2_info(&dev->v4l2_dev, "stream[%d] start stopping\n", stream->id);
	5002	+ v4l2_info(&dev->v4l2_dev, "stream[%d] start stopping, total mode 0x%x, cur 0x%x\n",
	5003	+ stream->id, stream->cur_stream_mode, mode);
2431	5004
2432		- stream->stopping = true;
	5005	+ if (mode == stream->cur_stream_mode) {
	5006	+ if (stream->dma_en) {
	5007	+ if (!dev->sensor_linetime)
	5008	+ dev->sensor_linetime = rkcif_get_linetime(stream);
	5009	+ vblank = rkcif_get_sensor_vblank(dev);
	5010	+ if (vblank) {
	5011	+ frame_time_ns = (vblank + dev->terminal_sensor.raw_rect.height) *
	5012	+ dev->sensor_linetime;
	5013	+ spin_lock_irqsave(&stream->fps_lock, flags);
	5014	+ fs_time = stream->readout.fs_timestamp;
	5015	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	5016	+ cur_time = rkcif_time_get_ns(dev);
	5017	+ if (cur_time > fs_time &&
	5018	+ cur_time - fs_time < (frame_time_ns - 10000000)) {
	5019	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	5020	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
	5021	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	5022	+ else if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
	5023	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	5024	+ stream->is_stop_capture = true;
	5025	+ rkcif_stop_dma_capture(stream);
	5026	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	5027	+ }
	5028	+ }
	5029	+ }
	5030	+ stream->stopping = true;
	5031	+ ret = wait_event_timeout(stream->wq_stopped,
	5032	+ stream->state != RKCIF_STATE_STREAMING,
	5033	+ msecs_to_jiffies(500));
	5034	+ if (!ret) {
	5035	+ rkcif_stream_stop(stream);
	5036	+ stream->stopping = false;
	5037	+ }
2433	5038
2434		- ret = wait_event_timeout(stream->wq_stopped,
2435		- stream->state != RKCIF_STATE_STREAMING,
2436		- msecs_to_jiffies(1000));
2437		- if (!ret) {
2438		- rkcif_stream_stop(stream);
2439		- stream->stopping = false;
	5039	+ media_pipeline_stop(&node->vdev.entity);
	5040	+ ret = dev->pipe.set_stream(&dev->pipe, false);
	5041	+ if (ret < 0)
	5042	+ v4l2_err(v4l2_dev, "pipeline stream-off failed error:%d\n",
	5043	+ ret);
	5044	+
	5045	+ dev->is_start_hdr = false;
	5046	+ stream->is_dvp_yuv_addr_init = false;
	5047	+ if (stream->skip_info.skip_en) {
	5048	+ stream->skip_info.skip_en = false;
	5049	+ stream->skip_info.skip_to_en = true;
	5050	+ }
	5051	+ } else if (mode == RKCIF_STREAM_MODE_CAPTURE && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	5052	+ //only stop dma
	5053	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	5054	+ stream->is_wait_dma_stop = true;
	5055	+ wait_event_timeout(stream->wq_stopped,
	5056	+ !stream->is_wait_dma_stop,
	5057	+ msecs_to_jiffies(1000));
	5058	+ } else if (mode == RKCIF_STREAM_MODE_TOISP && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	5059	+ //only stop dma
	5060	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	5061	+ stream->is_wait_dma_stop = true;
	5062	+ wait_event_timeout(stream->wq_stopped,
	5063	+ !stream->is_wait_dma_stop,
	5064	+ msecs_to_jiffies(1000));
	5065	+ }
	5066	+ if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE) {
	5067	+ /* release buffers */
	5068	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	5069	+ if (stream->curr_buf)
	5070	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	5071	+ if (stream->next_buf &&
	5072	+ stream->next_buf != stream->curr_buf)
	5073	+ list_add_tail(&stream->next_buf->queue, &stream->buf_head);
	5074	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	5075	+
	5076	+ if (dev->hdr.hdr_mode == HDR_X2 \|\|
	5077	+ dev->hdr.hdr_mode == HDR_X3)
	5078	+ rkcif_release_rdbk_buf(stream);
	5079	+
	5080	+ stream->curr_buf = NULL;
	5081	+ stream->next_buf = NULL;
	5082	+
	5083	+ rkcif_rx_buffer_free(stream);
	5084	+ list_for_each_entry(buf, &stream->buf_head, queue) {
	5085	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	5086	+ "stream[%d] buf return addr 0x%x\n",
	5087	+ stream->id, buf->buff_addr[0]);
	5088	+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
	5089	+ }
	5090	+ INIT_LIST_HEAD(&stream->buf_head);
	5091	+ while (!list_empty(&stream->vb_done_list)) {
	5092	+ buf = list_first_entry(&stream->vb_done_list,
	5093	+ struct rkcif_buffer, queue);
	5094	+ if (buf) {
	5095	+ list_del(&buf->queue);
	5096	+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
	5097	+ }
	5098	+ }
	5099	+ stream->total_buf_num = 0;
	5100	+ atomic_set(&stream->buf_cnt, 0);
	5101	+ stream->lack_buf_cnt = 0;
	5102	+ stream->dma_en &= ~RKCIF_DMAEN_BY_VICAP;
2440	5103	}
2441	5104
2442		- media_pipeline_stop(&node->vdev.entity);
2443		- ret = dev->pipe.set_stream(&dev->pipe, false);
2444		- if (ret < 0)
2445		- v4l2_err(v4l2_dev, "pipeline stream-off failed error:%d\n",
2446		- ret);
2447		-
2448		- dev->is_start_hdr = false;
2449		- stream->is_dvp_yuv_addr_init = false;
2450		-
2451		- /* release buffers */
2452		- if (stream->curr_buf)
2453		- list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
2454		-
2455		- if (stream->next_buf &&
2456		- stream->next_buf != stream->curr_buf)
2457		- list_add_tail(&stream->next_buf->queue, &stream->buf_head);
2458		-
2459		- if (dev->hdr.mode != NO_HDR)
2460		- rkcif_release_rdbk_buf(stream);
2461		-
2462		- stream->curr_buf = NULL;
2463		- stream->next_buf = NULL;
2464		-
2465		- while (!list_empty(&stream->buf_head)) {
2466		- buf = list_first_entry(&stream->buf_head,
2467		- struct rkcif_buffer, queue);
2468		- list_del(&buf->queue);
2469		- vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
2470		- }
2471		-
2472		- ret = dev->pipe.close(&dev->pipe);
2473		- if (ret < 0)
2474		- v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
2475		-
2476		- if (dev->hdr.mode == HDR_X2) {
2477		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
2478		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY) {
	5105	+ if (mode == stream->cur_stream_mode) {
	5106	+ ret = dev->pipe.close(&dev->pipe);
	5107	+ if (ret < 0)
	5108	+ v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
	5109	+ if (dev->hdr.hdr_mode == HDR_X2) {
	5110	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
	5111	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY) {
	5112	+ dev->can_be_reset = true;
	5113	+ }
	5114	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
	5115	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
	5116	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY &&
	5117	+ dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_READY) {
	5118	+ dev->can_be_reset = true;
	5119	+ }
	5120	+ } else {
2479	5121	dev->can_be_reset = true;
2480	5122	}
2481		- } else if (dev->hdr.mode == HDR_X3) {
2482		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
2483		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY &&
2484		- dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_READY) {
2485		- dev->can_be_reset = true;
	5123	+ mutex_lock(&hw_dev->dev_lock);
	5124	+ for (i = 0; i < hw_dev->dev_num; i++) {
	5125	+ if (atomic_read(&hw_dev->cif_dev[i]->pipe.stream_cnt) != 0) {
	5126	+ can_reset = false;
	5127	+ break;
	5128	+ }
2486	5129	}
2487		- } else {
2488		- dev->can_be_reset = true;
2489		- }
2490		-
2491		- spin_lock_irqsave(&hw_dev->hw_timer.timer_lock, flags);
2492		- for (i = 0; i < hw_dev->dev_num; i++) {
2493		- if (atomic_read(&hw_dev->cif_dev[i]->pipe.stream_cnt) != 0) {
2494		- can_reset = false;
2495		- break;
	5130	+ mutex_unlock(&hw_dev->dev_lock);
	5131	+ if (dev->can_be_reset && dev->chip_id >= CHIP_RK3588_CIF) {
	5132	+ rkcif_do_soft_reset(dev);
	5133	+ atomic_set(&dev->streamoff_cnt, 0);
2496	5134	}
	5135	+ if (dev->can_be_reset && can_reset) {
	5136	+ dev->can_be_reset = false;
	5137	+ dev->reset_work_cancel = true;
	5138	+ dev->early_line = 0;
	5139	+ dev->sensor_linetime = 0;
	5140	+ dev->wait_line = 0;
	5141	+ stream->is_line_wake_up = false;
	5142	+ }
	5143	+ if (can_reset && hw_dev->dummy_buf.vaddr)
	5144	+ rkcif_destroy_dummy_buf(stream);
2497	5145	}
	5146	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	5147	+ tasklet_disable(&stream->vb_done_tasklet);
2498	5148
2499		- if (dev->can_be_reset && can_reset) {
2500		- rkcif_do_cru_reset(dev);
2501		- dev->can_be_reset = false;
2502		- dev->reset_work_cancel = true;
2503		- hw_dev->hw_timer.is_running = false;
2504		- hw_dev->reset_info.is_need_reset = 0;
2505		- }
2506		- spin_unlock_irqrestore(&hw_dev->hw_timer.timer_lock, flags);
2507		-
2508		- pm_runtime_put_sync(dev->dev);
2509		-
2510		- if (!atomic_read(&dev->pipe.stream_cnt) && dev->dummy_buf.vaddr)
2511		- rkcif_destroy_dummy_buf(stream);
2512		-
2513		- v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished\n", stream->id);
2514		-
	5149	+ stream->cur_stream_mode &= ~mode;
	5150	+ INIT_LIST_HEAD(&stream->vb_done_list);
	5151	+ v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished, dma_en 0x%x\n", stream->id, stream->dma_en);
2515	5152	mutex_unlock(&dev->stream_lock);
	5153	+ rkcif_detach_sync_mode(dev);
	5154	+}
	5155	+
	5156	+static void rkcif_stop_streaming(struct vb2_queue *queue)
	5157	+{
	5158	+ struct rkcif_stream *stream = queue->drv_priv;
	5159	+
	5160	+ rkcif_do_stop_stream(stream, RKCIF_STREAM_MODE_CAPTURE);
2516	5161	}
2517	5162
2518	5163	/*
..	..	@@ -2588,6 +5233,70 @@
2588	5233	return mode;
2589	5234	}
2590	5235
	5236	+static u32 rkcif_determine_input_mode_rk3588(struct rkcif_stream *stream)
	5237	+{
	5238	+ struct rkcif_device *dev = stream->cifdev;
	5239	+ struct rkcif_sensor_info *sensor_info = dev->active_sensor;
	5240	+ struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
	5241	+ __u32 intf = BT656_STD_RAW;
	5242	+ u32 mode = INPUT_MODE_YUV;
	5243	+ v4l2_std_id std;
	5244	+ int ret;
	5245	+
	5246	+ ret = v4l2_subdev_call(sensor_info->sd, video, querystd, &std);
	5247	+ if (ret == 0) {
	5248	+ /* retrieve std from sensor if exist */
	5249	+ switch (std) {
	5250	+ case V4L2_STD_NTSC:
	5251	+ case V4L2_STD_PAL:
	5252	+ mode = INPUT_BT656_YUV422;
	5253	+ break;
	5254	+ case V4L2_STD_ATSC:
	5255	+ mode = INPUT_BT1120_YUV422;
	5256	+ break;
	5257	+ default:
	5258	+ v4l2_err(&dev->v4l2_dev,
	5259	+ "std: %lld is not supported", std);
	5260	+ }
	5261	+ mode \|= CSI_WRDDR_TYPE_RAW8 << 6;
	5262	+ } else {
	5263	+ /* determine input mode by mbus_code (fmt_type) */
	5264	+ switch (stream->cif_fmt_in->fmt_type) {
	5265	+ case CIF_FMT_TYPE_YUV:
	5266	+ if (sensor_info->mbus.type == V4L2_MBUS_BT656) {
	5267	+ if ((sensor_info->mbus.flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE)
	5268	+ mode = INPUT_BT1120_YUV422;
	5269	+ else
	5270	+ mode = INPUT_BT656_YUV422;
	5271	+ } else {
	5272	+ mode = INPUT_BT601_YUV422;
	5273	+ }
	5274	+ mode \|= CSI_WRDDR_TYPE_RAW8 << 6;
	5275	+ break;
	5276	+ case CIF_FMT_TYPE_RAW:
	5277	+ ret = v4l2_subdev_call(terminal_sensor->sd,
	5278	+ core, ioctl,
	5279	+ RKMODULE_GET_BT656_INTF_TYPE,
	5280	+ &intf);
	5281	+ if (!ret) {
	5282	+ if (intf == BT656_SONY_RAW)
	5283	+ mode = INPUT_SONY_RAW;
	5284	+ else
	5285	+ mode = INPUT_BT601_RAW;
	5286	+ } else {
	5287	+ mode = INPUT_BT601_RAW;
	5288	+ }
	5289	+ mode \|= stream->cif_fmt_in->csi_fmt_val << 6;
	5290	+ break;
	5291	+ }
	5292	+ }
	5293	+ if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
	5294	+ mode \|= TRANSMIT_PROGRESS_RK3588;
	5295	+ else
	5296	+ mode \|= TRANSMIT_INTERFACE_RK3588;
	5297	+ return mode;
	5298	+}
	5299	+
2591	5300	static inline u32 rkcif_scl_ctl(struct rkcif_stream *stream)
2592	5301	{
2593	5302	u32 fmt_type = stream->cif_fmt_in->fmt_type;
..	..	@@ -2612,15 +5321,21 @@
2612	5321	case V4L2_PIX_FMT_NV61:
2613	5322	case V4L2_PIX_FMT_NV12:
2614	5323	case V4L2_PIX_FMT_NV21:
2615		- case V4L2_PIX_FMT_YUYV:
2616		- case V4L2_PIX_FMT_YVYU:
2617		- case V4L2_PIX_FMT_UYVY:
2618		- case V4L2_PIX_FMT_VYUY:
2619	5324	case V4L2_PIX_FMT_GREY:
2620	5325	case V4L2_PIX_FMT_Y16:
2621	5326	bpp = fmt->bpp[plane_index];
2622	5327	break;
	5328	+ case V4L2_PIX_FMT_YUYV:
	5329	+ case V4L2_PIX_FMT_YVYU:
	5330	+ case V4L2_PIX_FMT_UYVY:
	5331	+ case V4L2_PIX_FMT_VYUY:
	5332	+ if (stream->cifdev->chip_id < CHIP_RK3588_CIF)
	5333	+ bpp = fmt->bpp[plane_index];
	5334	+ else
	5335	+ bpp = fmt->bpp[plane_index + 1];
	5336	+ break;
2623	5337	case V4L2_PIX_FMT_RGB24:
	5338	+ case V4L2_PIX_FMT_BGR24:
2624	5339	case V4L2_PIX_FMT_RGB565:
2625	5340	case V4L2_PIX_FMT_BGR666:
2626	5341	case V4L2_PIX_FMT_SRGGB8:
..	..	@@ -2636,8 +5351,13 @@
2636	5351	case V4L2_PIX_FMT_SGBRG12:
2637	5352	case V4L2_PIX_FMT_SBGGR12:
2638	5353	case V4L2_PIX_FMT_SBGGR16:
	5354	+ case V4L2_PIX_FMT_SGBRG16:
	5355	+ case V4L2_PIX_FMT_SGRBG16:
	5356	+ case V4L2_PIX_FMT_SRGGB16:
2639	5357	case V4l2_PIX_FMT_SPD16:
2640	5358	case V4l2_PIX_FMT_EBD8:
	5359	+ case V4L2_PIX_FMT_Y10:
	5360	+ case V4L2_PIX_FMT_Y12:
2641	5361	if (stream->cifdev->chip_id < CHIP_RV1126_CIF) {
2642	5362	bpp = max(fmt->bpp[plane_index], (u8)CIF_RAW_STORED_BIT_WIDTH);
2643	5363	cal = CIF_RAW_STORED_BIT_WIDTH;
..	..	@@ -2653,7 +5373,8 @@
2653	5373	}
2654	5374	break;
2655	5375	default:
2656		- pr_err("fourcc: %d is not supported!\n", fmt->fourcc);
	5376	+ v4l2_err(&stream->cifdev->v4l2_dev, "fourcc: %d is not supported!\n",
	5377	+ fmt->fourcc);
2657	5378	break;
2658	5379	}
2659	5380	}
..	..	@@ -2687,7 +5408,8 @@
2687	5408
2688	5409	if (dev->terminal_sensor.sd) {
2689	5410	input_sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
2690		-
	5411	+ input_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	5412	+ input_sel.pad = 0;
2691	5413	ret = v4l2_subdev_call(dev->terminal_sensor.sd,
2692	5414	pad, get_selection, NULL,
2693	5415	&input_sel);
..	..	@@ -2697,6 +5419,7 @@
2697	5419	stream->crop_mask \|= CROP_SRC_SENSOR_MASK;
2698	5420	dev->terminal_sensor.selection = input_sel;
2699	5421	} else {
	5422	+ stream->crop_mask &= ~CROP_SRC_SENSOR_MASK;
2700	5423	dev->terminal_sensor.selection.r = dev->terminal_sensor.raw_rect;
2701	5424	}
2702	5425	}
..	..	@@ -2717,8 +5440,10 @@
2717	5440	stream->crop[CROP_SRC_ACT].top = stream->crop[CROP_SRC_USR].top +
2718	5441	stream->crop[CROP_SRC_SENSOR].top;
2719	5442	}
2720		- } else {
	5443	+ } else if (stream->crop_mask & CROP_SRC_SENSOR_MASK) {
2721	5444	stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_SENSOR];
	5445	+ } else {
	5446	+ stream->crop[CROP_SRC_ACT] = dev->terminal_sensor.raw_rect;
2722	5447	}
2723	5448	}
2724	5449
..	..	@@ -2732,11 +5457,11 @@
2732	5457	struct rkcif_device *dev = stream->cifdev;
2733	5458	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
2734	5459	struct v4l2_rect input, *crop;
2735		- int vc;
2736	5460
2737	5461	if (dev->terminal_sensor.sd) {
2738		- stream->cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
2739		- &input, stream->id, &vc);
	5462	+ stream->cif_fmt_in = rkcif_get_input_fmt(dev,
	5463	+ &input, stream->id,
	5464	+ &dev->channels[stream->id]);
2740	5465	if (!stream->cif_fmt_in) {
2741	5466	v4l2_err(v4l2_dev, "Input fmt is invalid\n");
2742	5467	return -EINVAL;
..	..	@@ -2746,7 +5471,6 @@
2746	5471	return -EINVAL;
2747	5472	}
2748	5473
2749		- stream->vc = vc;
2750	5474	if (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
2751	5475	stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8) {
2752	5476	stream->crop_enable = false;
..	..	@@ -2764,7 +5488,9 @@
2764	5488	return -EINVAL;
2765	5489	}
2766	5490
2767		- if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2) {
	5491	+ if (dev->active_sensor &&
	5492	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	5493	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY)) {
2768	5494	if (crop->left > 0) {
2769	5495	int align_x = get_csi_crop_align(stream->cif_fmt_in);
2770	5496
..	..	@@ -2775,7 +5501,7 @@
2775	5501	return -EINVAL;
2776	5502	}
2777	5503	}
2778		- } else if (dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) {
	5504	+ } else if (dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) {
2779	5505	if (crop->left % 4 != 0 && crop->width % 4 != 0) {
2780	5506	v4l2_err(v4l2_dev,
2781	5507	"ERROR: lvds crop left and width must align %d\n", 4);
..	..	@@ -2807,8 +5533,8 @@
2807	5533	__func__, stream->id);
2808	5534	return -ENODEV;
2809	5535	}
2810		- ret = v4l2_subdev_call(sensor->sd, video, g_mbus_config,
2811		- &sensor->mbus);
	5536	+ ret = v4l2_subdev_call(sensor->sd, pad, get_mbus_config,
	5537	+ 0, &sensor->mbus);
2812	5538	if (ret && ret != -ENOIOCTLCMD) {
2813	5539	v4l2_err(&stream->cifdev->v4l2_dev,
2814	5540	"%s: get remote %s mbus failed!\n", __func__, sensor->sd->name);
..	..	@@ -2820,24 +5546,38 @@
2820	5546	terminal_sensor = &stream->cifdev->terminal_sensor;
2821	5547	get_remote_terminal_sensor(stream, &terminal_sensor->sd);
2822	5548	if (terminal_sensor->sd) {
2823		- ret = v4l2_subdev_call(terminal_sensor->sd, video, g_mbus_config,
2824		- &terminal_sensor->mbus);
	5549	+ ret = v4l2_subdev_call(terminal_sensor->sd, pad, get_mbus_config,
	5550	+ 0, &terminal_sensor->mbus);
2825	5551	if (ret && ret != -ENOIOCTLCMD) {
2826	5552	v4l2_err(&stream->cifdev->v4l2_dev,
2827	5553	"%s: get terminal %s mbus failed!\n",
2828	5554	__func__, terminal_sensor->sd->name);
2829	5555	return ret;
2830	5556	}
2831		- if (v4l2_subdev_call(terminal_sensor->sd, core, ioctl, RKMODULE_GET_CSI_DSI_INFO,
2832		- &terminal_sensor->dsi_input_en)) {
2833		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2834		- "%s: get terminal %s CSI/DSI sel failed, default csi input!\n",
	5557	+ ret = v4l2_subdev_call(terminal_sensor->sd, video,
	5558	+ g_frame_interval, &terminal_sensor->fi);
	5559	+ if (ret) {
	5560	+ v4l2_err(&stream->cifdev->v4l2_dev,
	5561	+ "%s: get terminal %s g_frame_interval failed!\n",
2835	5562	__func__, terminal_sensor->sd->name);
	5563	+ return ret;
	5564	+ }
	5565	+ if (v4l2_subdev_call(terminal_sensor->sd, core, ioctl, RKMODULE_GET_CSI_DSI_INFO,
	5566	+ &terminal_sensor->dsi_input_en)) {
	5567	+ v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
	5568	+ "%s: get terminal %s CSI/DSI sel failed, default csi input!\n",
	5569	+ __func__, terminal_sensor->sd->name);
2836	5570	terminal_sensor->dsi_input_en = 0;
2837	5571	}
	5572	+ } else {
	5573	+ v4l2_err(&stream->cifdev->v4l2_dev,
	5574	+ "%s: stream[%d] get remote terminal sensor failed!\n",
	5575	+ __func__, stream->id);
	5576	+ return -ENODEV;
2838	5577	}
2839	5578
2840		- if (terminal_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
	5579	+ if (terminal_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	5580	+ terminal_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
2841	5581	terminal_sensor->mbus.type == V4L2_MBUS_CCP2) {
2842	5582	switch (terminal_sensor->mbus.flags & V4L2_MBUS_CSI2_LANES) {
2843	5583	case V4L2_MBUS_CSI2_1_LANE:
..	..	@@ -2864,7 +5604,85 @@
2864	5604	return ret;
2865	5605	}
2866	5606
2867		-static int rkcif_stream_start(struct rkcif_stream *stream)
	5607	+static int rkcif_dvp_get_output_type_mask(struct rkcif_stream *stream)
	5608	+{
	5609	+ unsigned int mask;
	5610	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	5611	+
	5612	+ switch (fmt->fourcc) {
	5613	+ case V4L2_PIX_FMT_NV16:
	5614	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << 11) \|
	5615	+ (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
	5616	+ break;
	5617	+ case V4L2_PIX_FMT_NV61:
	5618	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << 11) \|
	5619	+ (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
	5620	+ break;
	5621	+ case V4L2_PIX_FMT_NV12:
	5622	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << 11) \|
	5623	+ (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
	5624	+ break;
	5625	+ case V4L2_PIX_FMT_NV21:
	5626	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << 11) \|
	5627	+ (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
	5628	+ break;
	5629	+ case V4L2_PIX_FMT_YUYV:
	5630	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5631	+ (CSI_YUV_OUTPUT_ORDER_YUYV << 1);
	5632	+ break;
	5633	+ case V4L2_PIX_FMT_YVYU:
	5634	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5635	+ (CSI_YUV_OUTPUT_ORDER_YVYU << 1);
	5636	+ break;
	5637	+ case V4L2_PIX_FMT_UYVY:
	5638	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5639	+ (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
	5640	+ break;
	5641	+ case V4L2_PIX_FMT_VYUY:
	5642	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5643	+ (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
	5644	+ break;
	5645	+ case V4L2_PIX_FMT_RGB24:
	5646	+ case V4L2_PIX_FMT_BGR24:
	5647	+ case V4L2_PIX_FMT_RGB565:
	5648	+ case V4L2_PIX_FMT_BGR666:
	5649	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
	5650	+ break;
	5651	+ case V4L2_PIX_FMT_SRGGB8:
	5652	+ case V4L2_PIX_FMT_SGRBG8:
	5653	+ case V4L2_PIX_FMT_SGBRG8:
	5654	+ case V4L2_PIX_FMT_SBGGR8:
	5655	+ case V4L2_PIX_FMT_SRGGB10:
	5656	+ case V4L2_PIX_FMT_SGRBG10:
	5657	+ case V4L2_PIX_FMT_SGBRG10:
	5658	+ case V4L2_PIX_FMT_SBGGR10:
	5659	+ case V4L2_PIX_FMT_SRGGB12:
	5660	+ case V4L2_PIX_FMT_SGRBG12:
	5661	+ case V4L2_PIX_FMT_SGBRG12:
	5662	+ case V4L2_PIX_FMT_SBGGR12:
	5663	+ case V4L2_PIX_FMT_GREY:
	5664	+ case V4L2_PIX_FMT_Y10:
	5665	+ case V4L2_PIX_FMT_Y12:
	5666	+ if (stream->is_compact)
	5667	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
	5668	+ else
	5669	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
	5670	+ break;
	5671	+ case V4L2_PIX_FMT_SBGGR16:
	5672	+ case V4L2_PIX_FMT_SGBRG16:
	5673	+ case V4L2_PIX_FMT_SGRBG16:
	5674	+ case V4L2_PIX_FMT_SRGGB16:
	5675	+ case V4L2_PIX_FMT_Y16:
	5676	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
	5677	+ break;
	5678	+ default:
	5679	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
	5680	+ break;
	5681	+ }
	5682	+ return mask;
	5683	+}
	5684	+
	5685	+static int rkcif_stream_start(struct rkcif_stream *stream, unsigned int mode)
2868	5686	{
2869	5687	u32 val, mbus_flags, href_pol, vsync_pol,
2870	5688	xfer_mode = 0, yc_swap = 0, inputmode = 0,
..	..	@@ -2873,20 +5691,66 @@
2873	5691	multi_id_mode = BT656_1120_MULTI_ID_MODE_1,
2874	5692	multi_id_sel = BT656_1120_MULTI_ID_SEL_LSB,
2875	5693	bt1120_edge_mode = BT1120_CLOCK_SINGLE_EDGES,
2876		- bt1120_flags = 0;
	5694	+ bt1120_flags = 0,
	5695	+ out_fmt_mask = 0,
	5696	+ in_fmt_yuv_order = 0;
2877	5697	struct rkmodule_bt656_mbus_info bt1120_info;
2878	5698	struct rkcif_device *dev = stream->cifdev;
2879	5699	struct rkcif_sensor_info *sensor_info;
2880	5700	struct v4l2_mbus_config *mbus;
2881	5701	struct rkcif_dvp_sof_subdev *sof_sd = &dev->dvp_sof_subdev;
2882	5702	const struct cif_output_fmt *fmt;
	5703	+ unsigned int dma_en = 0;
	5704	+ unsigned int dma_state = 0;
	5705	+ int i = 0;
	5706	+ u32 sav_detect = BT656_DETECT_SAV;
	5707	+ u32 reserved = 0;
2883	5708
2884		- if (stream->state != RKCIF_STATE_RESET_IN_STREAMING)
	5709	+ if (stream->state < RKCIF_STATE_STREAMING) {
2885	5710	stream->frame_idx = 0;
	5711	+ stream->buf_wake_up_cnt = 0;
	5712	+ stream->lack_buf_cnt = 0;
	5713	+ stream->frame_phase = 0;
	5714	+ stream->is_in_vblank = false;
	5715	+ stream->is_change_toisp = false;
	5716	+ }
2886	5717
2887	5718	sensor_info = dev->active_sensor;
2888	5719	mbus = &sensor_info->mbus;
2889	5720
	5721	+ dma_state = stream->dma_en;
	5722	+ if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE)
	5723	+ stream->dma_en \|= RKCIF_DMAEN_BY_VICAP;
	5724	+ else if ((mode & RKCIF_STREAM_MODE_TOISP_RDBK) == RKCIF_STREAM_MODE_TOISP_RDBK)
	5725	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	5726	+ else if ((mode & RKCIF_STREAM_MODE_ROCKIT) == RKCIF_STREAM_MODE_ROCKIT)
	5727	+ stream->dma_en \|= RKCIF_DMAEN_BY_ROCKIT;
	5728	+
	5729	+ if (dma_state)
	5730	+ return 0;
	5731	+
	5732	+ mbus_flags = mbus->flags;
	5733	+ if ((mbus_flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE) {
	5734	+ bt1120_edge_mode = (dev->chip_id < CHIP_RK3588_CIF ?
	5735	+ BT1120_CLOCK_DOUBLE_EDGES : BT1120_CLOCK_DOUBLE_EDGES_RK3588);
	5736	+ rkcif_enable_dvp_clk_dual_edge(dev, true);
	5737	+ } else {
	5738	+ bt1120_edge_mode = dev->chip_id < CHIP_RK3588_CIF ?
	5739	+ BT1120_CLOCK_SINGLE_EDGES : BT1120_CLOCK_SINGLE_EDGES_RK3588;
	5740	+ rkcif_enable_dvp_clk_dual_edge(dev, false);
	5741	+ }
	5742	+
	5743	+ if (IS_ENABLED(CONFIG_CPU_RV1106))
	5744	+ rkcif_config_dvp_pin(dev, true);
	5745	+
	5746	+ if (mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
	5747	+ rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_RISING);
	5748	+ else
	5749	+ rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_FALLING);
	5750	+
	5751	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	5752	+ rv1106_sdmmc_get_lock();
	5753	+#endif
2890	5754	if (sensor_info->sd && mbus->type == V4L2_MBUS_BT656) {
2891	5755	int ret;
2892	5756
..	..	@@ -2910,32 +5774,21 @@
2910	5774	multi_id_mode = BT656_1120_MULTI_ID_MODE_4;
2911	5775	else if (((bt1120_flags & RKMODULE_CAMERA_BT656_CHANNELS) >> 2) > 1)
2912	5776	multi_id_mode = BT656_1120_MULTI_ID_MODE_2;
2913		-
2914		- multi_id = DVP_SW_MULTI_ID(stream->id, stream->id, bt1120_info.id_en_bits);
	5777	+ for (i = 0; i < 4; i++)
	5778	+ multi_id \|= DVP_SW_MULTI_ID(i, i, bt1120_info.id_en_bits);
2915	5779	rkcif_write_register_or(dev, CIF_REG_DVP_MULTI_ID, multi_id);
2916	5780	}
2917	5781	}
2918		-
2919		- mbus_flags = mbus->flags;
2920		- if ((mbus_flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE) {
2921		- bt1120_edge_mode = BT1120_CLOCK_DOUBLE_EDGES;
2922		- rkcif_enable_dvp_clk_dual_edge(dev, true);
2923		- } else {
2924		- bt1120_edge_mode = BT1120_CLOCK_SINGLE_EDGES;
2925		- rkcif_enable_dvp_clk_dual_edge(dev, false);
2926		- }
2927		-
2928		- if (mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2929		- rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_RISING);
2930		- else
2931		- rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_FALLING);
2932	5782
2933	5783	href_pol = (mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) ?
2934	5784	HSY_HIGH_ACTIVE : HSY_LOW_ACTIVE;
2935	5785	vsync_pol = (mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) ?
2936	5786	VSY_HIGH_ACTIVE : VSY_LOW_ACTIVE;
2937	5787
2938		- inputmode = rkcif_determine_input_mode(stream);
	5788	+ if (dev->chip_id < CHIP_RK3588_CIF)
	5789	+ inputmode = rkcif_determine_input_mode(stream);
	5790	+ else
	5791	+ inputmode = rkcif_determine_input_mode_rk3588(stream);
2939	5792	if (dev->chip_id <= CHIP_RK1808_CIF) {
2940	5793	if (inputmode == INPUT_MODE_BT1120) {
2941	5794	if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
..	..	@@ -2945,7 +5798,7 @@
2945	5798	if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
2946	5799	yc_swap = BT1120_YC_SWAP;
2947	5800	}
2948		- } else {
	5801	+ } else if (dev->chip_id < CHIP_RK3588_CIF) {
2949	5802	if (sensor_info->mbus.type == V4L2_MBUS_BT656) {
2950	5803	if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
2951	5804	xfer_mode = BT1120_TRANSMIT_PROGRESS;
..	..	@@ -2957,9 +5810,14 @@
2957	5810	if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
2958	5811	yc_swap = BT1120_YC_SWAP;
2959	5812	}
	5813	+ } else {
	5814	+ if ((inputmode & INPUT_BT1120_YUV422) == INPUT_BT1120_YUV422)
	5815	+ if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
	5816	+ yc_swap = BT1120_YC_SWAP_RK3588;
2960	5817	}
2961	5818
2962		- if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2) {
	5819	+ if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	5820	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
2963	5821	inputmode = INPUT_MODE_MIPI;
2964	5822
2965	5823	/* if cif is linked with mipi,
..	..	@@ -2977,33 +5835,43 @@
2977	5835	mipimode = MIPI_MODE_32BITS_BYPASS;
2978	5836	}
2979	5837
2980		- val = vsync_pol \| href_pol \| inputmode \| mipimode
2981		- \| stream->cif_fmt_out->fmt_val
2982		- \| stream->cif_fmt_in->dvp_fmt_val
2983		- \| xfer_mode \| yc_swap \| multi_id_en
2984		- \| multi_id_sel \| multi_id_mode \| bt1120_edge_mode;
2985		-
2986		- if (stream->is_high_align)
2987		- val \|= CIF_HIGH_ALIGN;
2988		- else
2989		- val &= ~CIF_HIGH_ALIGN;
	5838	+ if (dev->chip_id < CHIP_RK3588_CIF) {
	5839	+ val = vsync_pol \| href_pol \| inputmode \| mipimode
	5840	+ \| stream->cif_fmt_out->fmt_val
	5841	+ \| stream->cif_fmt_in->dvp_fmt_val
	5842	+ \| xfer_mode \| yc_swap \| multi_id_en
	5843	+ \| multi_id_sel \| multi_id_mode \| bt1120_edge_mode;
	5844	+ if (stream->is_high_align)
	5845	+ val \|= CIF_HIGH_ALIGN;
	5846	+ else
	5847	+ val &= ~CIF_HIGH_ALIGN;
	5848	+ } else {
	5849	+ out_fmt_mask = rkcif_dvp_get_output_type_mask(stream);
	5850	+ in_fmt_yuv_order = rkcif_dvp_get_input_yuv_order(stream);
	5851	+ val = vsync_pol \| href_pol \| inputmode
	5852	+ \| yc_swap
	5853	+ \| out_fmt_mask
	5854	+ \| in_fmt_yuv_order
	5855	+ \| multi_id_en
	5856	+ \| sav_detect
	5857	+ \| multi_id_sel \| multi_id_mode \| bt1120_edge_mode;
	5858	+ if (stream->is_high_align)
	5859	+ val \|= CIF_HIGH_ALIGN_RK3588;
	5860	+ else
	5861	+ val &= ~CIF_HIGH_ALIGN_RK3588;
	5862	+ }
2990	5863	rkcif_write_register(dev, CIF_REG_DVP_FOR, val);
2991	5864
2992		- val = stream->pixm.width;
2993		- if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_RAW) {
2994		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
2995		- if (fmt->fourcc == V4L2_PIX_FMT_GREY \|\|
2996		- fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
2997		- fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
2998		- fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
2999		- fmt->fourcc == V4L2_PIX_FMT_SBGGR8)
	5865	+ if (dev->chip_id >= CHIP_RK3588_CIF) {
	5866	+ val = stream->pixm.plane_fmt[0].bytesperline;
	5867	+ } else {
	5868	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
	5869	+ if (fmt->fmt_type == CIF_FMT_TYPE_RAW &&
	5870	+ fmt->csi_fmt_val == CSI_WRDDR_TYPE_RAW8)
3000	5871	val = ALIGN(stream->pixm.width * fmt->raw_bpp / 8, 256);
3001	5872	else
3002	5873	val = stream->pixm.width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
3003	5874	}
3004		- rkcif_write_register(dev, CIF_REG_DVP_VIR_LINE_WIDTH, val);
3005		- rkcif_write_register(dev, CIF_REG_DVP_SET_SIZE,
3006		- stream->pixm.width \| (stream->pixm.height << 16));
3007	5875
3008	5876	if (stream->crop_enable) {
3009	5877	dev->channels[stream->id].crop_en = 1;
..	..	@@ -3019,6 +5887,10 @@
3019	5887	dev->channels[stream->id].crop_en = 0;
3020	5888	}
3021	5889
	5890	+ rkcif_write_register(dev, CIF_REG_DVP_VIR_LINE_WIDTH, val);
	5891	+ rkcif_write_register(dev, CIF_REG_DVP_SET_SIZE,
	5892	+ dev->channels[stream->id].width \|
	5893	+ (dev->channels[stream->id].height << 16));
3022	5894	rkcif_write_register(dev, CIF_REG_DVP_CROP,
3023	5895	dev->channels[stream->id].crop_st_y << CIF_CROP_Y_SHIFT \|
3024	5896	dev->channels[stream->id].crop_st_x);
..	..	@@ -3026,17 +5898,44 @@
3026	5898	if (atomic_read(&dev->pipe.stream_cnt) <= 1)
3027	5899	rkcif_write_register(dev, CIF_REG_DVP_FRAME_STATUS, FRAME_STAT_CLS);
3028	5900
3029		- rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, INTSTAT_CLS);
3030		- rkcif_write_register(dev, CIF_REG_DVP_SCL_CTRL, rkcif_scl_ctl(stream));
	5901	+ if (dev->chip_id < CHIP_RK3588_CIF) {
	5902	+ rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, INTSTAT_CLS);
	5903	+ rkcif_write_register(dev, CIF_REG_DVP_SCL_CTRL, rkcif_scl_ctl(stream));
	5904	+ rkcif_write_register_or(dev, CIF_REG_DVP_INTEN,
	5905	+ DVP_DMA_END_INTSTAT(stream->id) \|
	5906	+ INTSTAT_ERR \| PST_INF_FRAME_END);
	5907	+ /* enable line int for sof */
	5908	+ rkcif_write_register(dev, CIF_REG_DVP_LINE_INT_NUM, 0x1);
	5909	+ rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, LINE_INT_EN);
	5910	+ } else {
	5911	+ if (dev->chip_id == CHIP_RV1106_CIF)
	5912	+ reserved = 0xfc3c0000;
	5913	+ else
	5914	+ reserved = 0;
	5915	+ rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, 0x3c3ffff \| reserved);
	5916	+ rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, 0x033ffff);//0x3c3ffff
	5917	+ }
3031	5918
3032		- if (dev->chip_id < CHIP_RK1808_CIF)
3033		- rkcif_assign_new_buffer_oneframe(stream,
3034		- RKCIF_YUV_ADDR_STATE_INIT);
3035		- else
3036		- rkcif_assign_new_buffer_pingpong(stream,
	5919	+ if (stream->dma_en) {
	5920	+ if (dev->chip_id < CHIP_RK1808_CIF) {
	5921	+ rkcif_assign_new_buffer_oneframe(stream,
	5922	+ RKCIF_YUV_ADDR_STATE_INIT);
	5923	+ } else {
	5924	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	5925	+ rkcif_assign_new_buffer_pingpong(stream,
3037	5926	RKCIF_YUV_ADDR_STATE_INIT,
3038	5927	stream->id);
3039		-
	5928	+ else if (mode == RKCIF_STREAM_MODE_TOISP \|\|
	5929	+ mode == RKCIF_STREAM_MODE_TOISP_RDBK)
	5930	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	5931	+ RKCIF_YUV_ADDR_STATE_INIT,
	5932	+ stream->id);
	5933	+ else if (mode == RKCIF_STREAM_MODE_ROCKIT)
	5934	+ rkcif_assign_new_buffer_pingpong_rockit(stream,
	5935	+ RKCIF_YUV_ADDR_STATE_INIT,
	5936	+ stream->id);
	5937	+ }
	5938	+ }
3040	5939	rkcif_write_register_or(dev, CIF_REG_DVP_INTEN,
3041	5940	DVP_DMA_END_INTSTAT(stream->id) \|
3042	5941	INTSTAT_ERR \| PST_INF_FRAME_END);
..	..	@@ -3052,14 +5951,48 @@
3052	5951	else
3053	5952	workmode = MODE_LINELOOP;
3054	5953
3055		- if (inputmode == INPUT_MODE_BT1120) {
	5954	+ if ((inputmode & INPUT_MODE_BT1120) == INPUT_MODE_BT1120) {
3056	5955	workmode = MODE_PINGPONG;
3057	5956	dev->workmode = RKCIF_WORKMODE_PINGPONG;
3058	5957	}
3059	5958
3060		- rkcif_write_register(dev, CIF_REG_DVP_CTRL,
3061		- AXI_BURST_16 \| workmode \| ENABLE_CAPTURE);
3062		-
	5959	+ if (dev->chip_id == CHIP_RK3588_CIF) {
	5960	+ if (stream->dma_en)
	5961	+ dma_en = DVP_DMA_EN;
	5962	+ if (stream->lack_buf_cnt == 2)
	5963	+ dma_en = 0;
	5964	+ rkcif_write_register(dev, CIF_REG_DVP_CTRL,
	5965	+ DVP_SW_WATER_LINE_25
	5966	+ \| dma_en
	5967	+ \| DVP_PRESS_EN
	5968	+ \| DVP_HURRY_EN
	5969	+ \| DVP_SW_WATER_LINE_25
	5970	+ \| DVP_SW_PRESS_VALUE(3)
	5971	+ \| DVP_SW_HURRY_VALUE(3)
	5972	+ \| ENABLE_CAPTURE);
	5973	+ } else if (dev->chip_id == CHIP_RV1106_CIF) {
	5974	+ if (stream->dma_en)
	5975	+ dma_en = DVP_SW_DMA_EN(stream->id);
	5976	+ if (stream->lack_buf_cnt == 2)
	5977	+ dma_en = 0;
	5978	+ rkcif_write_register(dev, CIF_REG_DVP_CTRL,
	5979	+ DVP_SW_WATER_LINE_25
	5980	+ \| DVP_PRESS_EN
	5981	+ \| DVP_HURRY_EN
	5982	+ \| DVP_SW_WATER_LINE_25
	5983	+ \| DVP_SW_PRESS_VALUE(3)
	5984	+ \| DVP_SW_HURRY_VALUE(3)
	5985	+ \| DVP_SW_CAP_EN(stream->id)
	5986	+ \| dma_en
	5987	+ \| ENABLE_CAPTURE);
	5988	+ } else {
	5989	+ rkcif_write_register(dev, CIF_REG_DVP_CTRL,
	5990	+ AXI_BURST_16 \| workmode \| ENABLE_CAPTURE);
	5991	+ }
	5992	+ dev->intr_mask = rkcif_read_register(dev, CIF_REG_DVP_INTSTAT);
	5993	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	5994	+ rv1106_sdmmc_put_lock();
	5995	+#endif
3063	5996	atomic_set(&sof_sd->frm_sync_seq, 0);
3064	5997	stream->state = RKCIF_STATE_STREAMING;
3065	5998	stream->cifdev->dvp_sof_in_oneframe = 0;
..	..	@@ -3067,34 +6000,199 @@
3067	6000	return 0;
3068	6001	}
3069	6002
3070		-static int rkcif_start_streaming(struct vb2_queue *queue, unsigned int count)
	6003	+static void rkcif_attach_sync_mode(struct rkcif_device *cifdev)
3071	6004	{
3072		- struct rkcif_stream *stream = queue->drv_priv;
	6005	+ struct rkcif_hw *hw = cifdev->hw_dev;
	6006	+ struct rkcif_device *dev;
	6007	+ struct sditf_priv *priv;
	6008	+ int i = 0, j = 0;
	6009	+ int ret = 0;
	6010	+ int count = 0;
	6011	+ int sync_type = NO_SYNC_MODE;
	6012	+ int sync_group = 0;
	6013	+ struct rkcif_sync_cfg sync_cfg;
	6014	+ struct rkcif_multi_sync_config *sync_config;
	6015	+
	6016	+ mutex_lock(&hw->dev_lock);
	6017	+ if (cifdev->sditf_cnt <= 1) {
	6018	+ ret = v4l2_subdev_call(cifdev->terminal_sensor.sd,
	6019	+ core, ioctl,
	6020	+ RKMODULE_GET_SYNC_MODE,
	6021	+ &sync_type);
	6022	+ if (!ret)
	6023	+ sync_cfg.type = sync_type;
	6024	+ else
	6025	+ sync_cfg.type = NO_SYNC_MODE;
	6026	+ ret = v4l2_subdev_call(cifdev->terminal_sensor.sd,
	6027	+ core, ioctl,
	6028	+ RKMODULE_GET_GROUP_ID,
	6029	+ &sync_group);
	6030	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	6031	+ sync_cfg.group = sync_group;
	6032	+ else
	6033	+ sync_cfg.group = 0;
	6034	+ } else {
	6035	+ for (j = 0; j < cifdev->sditf_cnt; j++) {
	6036	+ ret \|= v4l2_subdev_call(cifdev->sditf[j]->sensor_sd,
	6037	+ core, ioctl,
	6038	+ RKMODULE_GET_SYNC_MODE,
	6039	+ &sync_type);
	6040	+ if (!ret && sync_type)
	6041	+ break;
	6042	+ }
	6043	+ if (!ret)
	6044	+ sync_cfg.type = sync_type;
	6045	+ else
	6046	+ sync_cfg.type = NO_SYNC_MODE;
	6047	+ ret = v4l2_subdev_call(cifdev->sditf[j]->sensor_sd,
	6048	+ core, ioctl,
	6049	+ RKMODULE_GET_GROUP_ID,
	6050	+ &sync_group);
	6051	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	6052	+ sync_cfg.group = sync_group;
	6053	+ else
	6054	+ sync_cfg.group = 0;
	6055	+ }
	6056	+ cifdev->sync_cfg = sync_cfg;
	6057	+ if (sync_cfg.type == NO_SYNC_MODE \|\|
	6058	+ hw->sync_config[sync_cfg.group].is_attach) {
	6059	+ mutex_unlock(&hw->dev_lock);
	6060	+ return;
	6061	+ }
	6062	+
	6063	+ sync_config = &hw->sync_config[sync_cfg.group];
	6064	+ memset(sync_config, 0, sizeof(struct rkcif_multi_sync_config));
	6065	+ for (i = 0; i < hw->dev_num; i++) {
	6066	+ dev = hw->cif_dev[i];
	6067	+ if (dev->sditf_cnt <= 1) {
	6068	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	6069	+ core, ioctl,
	6070	+ RKMODULE_GET_SYNC_MODE,
	6071	+ &sync_type);
	6072	+ if (!ret)
	6073	+ sync_cfg.type = sync_type;
	6074	+ else
	6075	+ sync_cfg.type = NO_SYNC_MODE;
	6076	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	6077	+ core, ioctl,
	6078	+ RKMODULE_GET_GROUP_ID,
	6079	+ &sync_group);
	6080	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	6081	+ sync_cfg.group = sync_group;
	6082	+ else
	6083	+ sync_cfg.group = 0;
	6084	+ } else {
	6085	+ priv = dev->sditf[0];
	6086	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	6087	+ for (j = 0; j < dev->sditf_cnt; j++) {
	6088	+ ret \|= v4l2_subdev_call(dev->sditf[j]->sensor_sd,
	6089	+ core, ioctl,
	6090	+ RKMODULE_GET_SYNC_MODE,
	6091	+ &sync_type);
	6092	+ if (!ret && sync_type) {
	6093	+ priv = dev->sditf[j];
	6094	+ break;
	6095	+ }
	6096	+ }
	6097	+ if (!ret)
	6098	+ sync_cfg.type = sync_type;
	6099	+ else
	6100	+ sync_cfg.type = NO_SYNC_MODE;
	6101	+ ret = v4l2_subdev_call(priv->sensor_sd,
	6102	+ core, ioctl,
	6103	+ RKMODULE_GET_GROUP_ID,
	6104	+ &sync_group);
	6105	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	6106	+ sync_cfg.group = sync_group;
	6107	+ else
	6108	+ sync_cfg.group = 0;
	6109	+ }
	6110	+ }
	6111	+ if (sync_cfg.group == cifdev->sync_cfg.group) {
	6112	+ if (sync_cfg.type == EXTERNAL_MASTER_MODE) {
	6113	+ count = sync_config->ext_master.count;
	6114	+ sync_config->ext_master.cif_dev[count] = dev;
	6115	+ sync_config->ext_master.count++;
	6116	+ sync_config->dev_cnt++;
	6117	+ sync_config->sync_mask \|= BIT(dev->csi_host_idx);
	6118	+ } else if (sync_cfg.type == INTERNAL_MASTER_MODE) {
	6119	+ count = sync_config->int_master.count;
	6120	+ sync_config->int_master.cif_dev[count] = dev;
	6121	+ sync_config->int_master.count++;
	6122	+ sync_config->dev_cnt++;
	6123	+ sync_config->sync_mask \|= BIT(dev->csi_host_idx);
	6124	+ } else if (sync_cfg.type == SLAVE_MODE) {
	6125	+ count = sync_config->slave.count;
	6126	+ sync_config->slave.cif_dev[count] = dev;
	6127	+ sync_config->slave.count++;
	6128	+ sync_config->dev_cnt++;
	6129	+ sync_config->sync_mask \|= BIT(dev->csi_host_idx);
	6130	+ }
	6131	+ dev->sync_cfg = sync_cfg;
	6132	+ } else {
	6133	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	6134	+ core, ioctl,
	6135	+ RKMODULE_GET_SYNC_MODE,
	6136	+ &sync_type);
	6137	+ }
	6138	+ }
	6139	+ if (sync_config->int_master.count == 1) {
	6140	+ if (sync_config->ext_master.count) {
	6141	+ sync_config->mode = RKCIF_MASTER_MASTER;
	6142	+ sync_config->is_attach = true;
	6143	+ } else if (sync_config->slave.count) {
	6144	+ sync_config->mode = RKCIF_MASTER_SLAVE;
	6145	+ sync_config->is_attach = true;
	6146	+ } else {
	6147	+ dev_info(hw->dev,
	6148	+ "Missing slave device, do not use sync mode\n");
	6149	+ }
	6150	+ if (sync_config->is_attach)
	6151	+ dev_info(hw->dev,
	6152	+ "group %d, int_master %d, ext_master %d, slave %d\n",
	6153	+ i,
	6154	+ sync_config->int_master.count,
	6155	+ sync_config->ext_master.count,
	6156	+ sync_config->slave.count);
	6157	+ }
	6158	+ mutex_unlock(&hw->dev_lock);
	6159	+}
	6160	+
	6161	+static void rkcif_monitor_reset_event(struct rkcif_device *dev);
	6162	+
	6163	+int rkcif_do_start_stream(struct rkcif_stream *stream, unsigned int mode)
	6164	+{
3073	6165	struct rkcif_vdev_node *node = &stream->vnode;
3074	6166	struct rkcif_device *dev = stream->cifdev;
	6167	+ struct rkcif_hw *hw_dev = dev->hw_dev;
3075	6168	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
3076	6169	struct rkcif_sensor_info *sensor_info = dev->active_sensor;
3077		- struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
	6170	+ struct rkcif_sensor_info *terminal_sensor = NULL;
3078	6171	struct rkmodule_hdr_cfg hdr_cfg;
	6172	+ struct rkcif_csi_info csi_info = {0};
3079	6173	int rkmodule_stream_seq = RKMODULE_START_STREAM_DEFAULT;
3080	6174	int ret;
	6175	+ int i = 0;
	6176	+ u32 skip_frame = 0;
3081	6177
3082	6178	v4l2_info(&dev->v4l2_dev, "stream[%d] start streaming\n", stream->id);
3083	6179
	6180	+ rkcif_attach_sync_mode(dev);
3084	6181	mutex_lock(&dev->stream_lock);
3085	6182
3086		- if (WARN_ON(stream->state != RKCIF_STATE_READY)) {
	6183	+ if ((stream->cur_stream_mode & RKCIF_STREAM_MODE_CAPTURE) == mode) {
3087	6184	ret = -EBUSY;
3088	6185	v4l2_err(v4l2_dev, "stream in busy state\n");
3089	6186	goto destroy_buf;
3090	6187	}
	6188	+ if (stream->dma_en == 0)
	6189	+ stream->fs_cnt_in_single_frame = 0;
3091	6190	if (stream->is_line_wake_up)
3092	6191	stream->is_line_inten = true;
3093	6192	else
3094	6193	stream->is_line_inten = false;
3095		- stream->fs_cnt_in_single_frame = 0;
3096	6194
3097		- if (dev->active_sensor) {
	6195	+ if (!dev->active_sensor) {
3098	6196	ret = rkcif_update_sensor_info(stream);
3099	6197	if (ret < 0) {
3100	6198	v4l2_err(v4l2_dev,
..	..	@@ -3103,16 +6201,16 @@
3103	6201	goto out;
3104	6202	}
3105	6203	}
3106		-
	6204	+ terminal_sensor = &dev->terminal_sensor;
3107	6205	if (terminal_sensor->sd) {
3108	6206	ret = v4l2_subdev_call(terminal_sensor->sd,
3109	6207	core, ioctl,
3110	6208	RKMODULE_GET_HDR_CFG,
3111	6209	&hdr_cfg);
3112	6210	if (!ret)
3113		- dev->hdr.mode = hdr_cfg.hdr_mode;
	6211	+ dev->hdr = hdr_cfg;
3114	6212	else
3115		- dev->hdr.mode = NO_HDR;
	6213	+ dev->hdr.hdr_mode = NO_HDR;
3116	6214
3117	6215	ret = v4l2_subdev_call(terminal_sensor->sd,
3118	6216	video, g_frame_interval, &terminal_sensor->fi);
..	..	@@ -3133,109 +6231,158 @@
3133	6231	if (ret < 0)
3134	6232	goto destroy_buf;
3135	6233
	6234	+ mutex_lock(&hw_dev->dev_lock);
	6235	+ if (atomic_read(&dev->pipe.stream_cnt) == 0 &&
	6236	+ dev->active_sensor &&
	6237	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	6238	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	6239	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)) {
	6240	+ if (dev->channels[0].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	6241	+ csi_info.csi_num = dev->channels[0].capture_info.multi_dev.dev_num;
	6242	+ if (csi_info.csi_num > RKCIF_MAX_CSI_NUM) {
	6243	+ v4l2_err(v4l2_dev,
	6244	+ "csi num %d, max %d\n",
	6245	+ csi_info.csi_num, RKCIF_MAX_CSI_NUM);
	6246	+ goto out;
	6247	+ }
	6248	+ for (i = 0; i < csi_info.csi_num; i++) {
	6249	+ csi_info.csi_idx[i] = dev->channels[0].capture_info.multi_dev.dev_idx[i];
	6250	+ if (dev->hw_dev->is_rk3588s2)
	6251	+ v4l2_info(v4l2_dev, "rk3588s2 combine mode attach to mipi%d\n",
	6252	+ csi_info.csi_idx[i]);
	6253	+ }
	6254	+ } else {
	6255	+ csi_info.csi_num = 1;
	6256	+ dev->csi_host_idx = dev->csi_host_idx_def;
	6257	+ csi_info.csi_idx[0] = dev->csi_host_idx;
	6258	+ }
	6259	+ ret = v4l2_subdev_call(dev->active_sensor->sd,
	6260	+ core, ioctl,
	6261	+ RKCIF_CMD_SET_CSI_IDX,
	6262	+ &csi_info);
	6263	+ if (ret)
	6264	+ v4l2_err(&dev->v4l2_dev, "set csi idx %d fail\n", dev->csi_host_idx);
	6265	+
	6266	+ }
	6267	+
3136	6268	if (((dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_BT656) \|\|
3137	6269	dev->is_use_dummybuf) &&
3138		- (!dev->dummy_buf.vaddr)) {
	6270	+ (!dev->hw_dev->dummy_buf.vaddr) &&
	6271	+ mode == RKCIF_STREAM_MODE_CAPTURE) {
3139	6272	ret = rkcif_create_dummy_buf(stream);
3140	6273	if (ret < 0) {
	6274	+ mutex_unlock(&hw_dev->dev_lock);
3141	6275	v4l2_err(v4l2_dev, "Failed to create dummy_buf, %d\n", ret);
3142	6276	goto destroy_buf;
3143	6277	}
3144	6278	}
	6279	+ mutex_unlock(&hw_dev->dev_lock);
3145	6280
3146		- /* enable clocks/power-domains */
3147		- ret = pm_runtime_get_sync(dev->dev);
3148		- if (ret < 0) {
3149		- v4l2_err(v4l2_dev, "Failed to get runtime pm, %d\n",
3150		- ret);
3151		- goto destroy_buf;
3152		- }
	6281	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	6282	+ tasklet_enable(&stream->vb_done_tasklet);
3153	6283
3154		- ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
3155		- if (ret < 0) {
3156		- v4l2_err(v4l2_dev, "open cif pipeline failed %d\n",
3157		- ret);
3158		- goto destroy_buf;
3159		- }
	6284	+ if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
	6285	+ ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
	6286	+ if (ret < 0) {
	6287	+ v4l2_err(v4l2_dev, "open cif pipeline failed %d\n",
	6288	+ ret);
	6289	+ goto destroy_buf;
	6290	+ }
3160	6291
3161		- /*
3162		- * start sub-devices
3163		- * When use bt601, the sampling edge of cif is random,
3164		- * can be rising or fallling after powering on cif.
3165		- * To keep the coherence of edge, open sensor in advance.
3166		- */
3167		- if (sensor_info->mbus.type == V4L2_MBUS_PARALLEL \|\|
3168		- rkmodule_stream_seq == RKMODULE_START_STREAM_FRONT) {
3169		- ret = dev->pipe.set_stream(&dev->pipe, true);
3170		- if (ret < 0)
3171		- goto runtime_put;
3172		- }
3173		-
3174		- if (dev->chip_id >= CHIP_RK1808_CIF) {
3175		- if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
3176		- dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)
3177		- ret = rkcif_csi_stream_start(stream);
	6292	+ /*
	6293	+ * start sub-devices
	6294	+ * When use bt601, the sampling edge of cif is random,
	6295	+ * can be rising or fallling after powering on cif.
	6296	+ * To keep the coherence of edge, open sensor in advance.
	6297	+ */
	6298	+ if (sensor_info->mbus.type == V4L2_MBUS_PARALLEL \|\|
	6299	+ rkmodule_stream_seq == RKMODULE_START_STREAM_FRONT) {
	6300	+ ret = dev->pipe.set_stream(&dev->pipe, true);
	6301	+ if (ret < 0)
	6302	+ goto destroy_buf;
	6303	+ }
	6304	+ ret = v4l2_subdev_call(terminal_sensor->sd,
	6305	+ core, ioctl,
	6306	+ RKMODULE_GET_SKIP_FRAME,
	6307	+ &skip_frame);
	6308	+ if (!ret && skip_frame < RKCIF_SKIP_FRAME_MAX)
	6309	+ stream->skip_frame = skip_frame;
3178	6310	else
3179		- ret = rkcif_stream_start(stream);
	6311	+ stream->skip_frame = 0;
	6312	+ stream->cur_skip_frame = stream->skip_frame;
	6313	+ }
	6314	+ if (dev->chip_id >= CHIP_RK1808_CIF) {
	6315	+ if (dev->active_sensor &&
	6316	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	6317	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	6318	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2))
	6319	+ ret = rkcif_csi_stream_start(stream, mode);
	6320	+ else
	6321	+ ret = rkcif_stream_start(stream, mode);
3180	6322	} else {
3181		- ret = rkcif_stream_start(stream);
	6323	+ ret = rkcif_stream_start(stream, mode);
3182	6324	}
3183	6325
3184	6326	if (ret < 0)
3185		- goto runtime_put;
	6327	+ goto destroy_buf;
3186	6328
3187		- ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
3188		- if (ret < 0) {
3189		- v4l2_err(&dev->v4l2_dev, "start pipeline failed %d\n",
3190		- ret);
3191		- goto pipe_stream_off;
	6329	+ if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
	6330	+ ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
	6331	+ if (ret < 0) {
	6332	+ v4l2_err(&dev->v4l2_dev, "start pipeline failed %d\n",
	6333	+ ret);
	6334	+ goto pipe_stream_off;
	6335	+ }
	6336	+
	6337	+ if (sensor_info->mbus.type != V4L2_MBUS_PARALLEL &&
	6338	+ rkmodule_stream_seq != RKMODULE_START_STREAM_FRONT) {
	6339	+ ret = dev->pipe.set_stream(&dev->pipe, true);
	6340	+ if (ret < 0)
	6341	+ goto stop_stream;
	6342	+ }
3192	6343	}
3193		-
3194		- if (sensor_info->mbus.type != V4L2_MBUS_PARALLEL &&
3195		- rkmodule_stream_seq != RKMODULE_START_STREAM_FRONT) {
3196		- ret = dev->pipe.set_stream(&dev->pipe, true);
3197		- if (ret < 0)
3198		- goto stop_stream;
3199		- }
3200		-
3201		- if (dev->hdr.mode == NO_HDR) {
3202		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING) {
3203		- rkcif_start_luma(&dev->luma_vdev,
	6344	+ if (dev->chip_id == CHIP_RV1126_CIF \|\|
	6345	+ dev->chip_id == CHIP_RV1126_CIF_LITE \|\|
	6346	+ dev->chip_id == CHIP_RK3568_CIF) {
	6347	+ if (dev->hdr.hdr_mode == NO_HDR) {
	6348	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING)
	6349	+ rkcif_start_luma(&dev->luma_vdev,
	6350	+ dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
	6351	+ } else if (dev->hdr.hdr_mode == HDR_X2) {
	6352	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
	6353	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING)
	6354	+ rkcif_start_luma(&dev->luma_vdev,
	6355	+ dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
	6356	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
	6357	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
	6358	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING &&
	6359	+ dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_STREAMING)
	6360	+ rkcif_start_luma(&dev->luma_vdev,
3204	6361	dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
3205	6362	}
3206		- } else if (dev->hdr.mode == HDR_X2) {
3207		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
3208		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING) {
3209		- rkcif_start_luma(&dev->luma_vdev,
3210		- dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
3211		- }
3212		- } else if (dev->hdr.mode == HDR_X3) {
3213		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
3214		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING &&
3215		- dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_STREAMING) {
3216		- rkcif_start_luma(&dev->luma_vdev,
3217		- dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
3218		- }
3219	6363	}
3220		-
3221	6364	dev->reset_work_cancel = false;
3222		- if (dev->hdr.mode == NO_HDR)
3223		- stream->streamon_timestamp = ktime_get_ns();
	6365	+ stream->cur_stream_mode \|= mode;
	6366	+ rkcif_monitor_reset_event(dev);
3224	6367	goto out;
3225	6368
3226	6369	stop_stream:
3227	6370	rkcif_stream_stop(stream);
3228	6371	pipe_stream_off:
3229	6372	dev->pipe.set_stream(&dev->pipe, false);
3230		-runtime_put:
3231		- pm_runtime_put_sync(dev->dev);
	6373	+
3232	6374	destroy_buf:
3233		- if (stream->next_buf)
3234		- vb2_buffer_done(&stream->next_buf->vb.vb2_buf,
3235		- VB2_BUF_STATE_QUEUED);
	6375	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	6376	+ tasklet_disable(&stream->vb_done_tasklet);
3236	6377	if (stream->curr_buf)
3237		- vb2_buffer_done(&stream->curr_buf->vb.vb2_buf,
3238		- VB2_BUF_STATE_QUEUED);
	6378	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	6379	+ if (stream->next_buf &&
	6380	+ stream->next_buf != stream->curr_buf)
	6381	+ list_add_tail(&stream->next_buf->queue, &stream->buf_head);
	6382	+
	6383	+ stream->curr_buf = NULL;
	6384	+ stream->next_buf = NULL;
	6385	+ atomic_set(&stream->buf_cnt, 0);
3239	6386	while (!list_empty(&stream->buf_head)) {
3240	6387	struct rkcif_buffer *buf;
3241	6388
..	..	@@ -3247,6 +6394,15 @@
3247	6394
3248	6395	out:
3249	6396	mutex_unlock(&dev->stream_lock);
	6397	+ return ret;
	6398	+}
	6399	+
	6400	+static int rkcif_start_streaming(struct vb2_queue *queue, unsigned int count)
	6401	+{
	6402	+ struct rkcif_stream *stream = queue->drv_priv;
	6403	+ int ret = 0;
	6404	+
	6405	+ ret = rkcif_do_start_stream(stream, RKCIF_STREAM_MODE_CAPTURE);
3250	6406	return ret;
3251	6407	}
3252	6408
..	..	@@ -3269,10 +6425,7 @@
3269	6425	q->io_modes = VB2_MMAP \| VB2_DMABUF;
3270	6426	q->drv_priv = stream;
3271	6427	q->ops = &rkcif_vb2_ops;
3272		- if (hw_dev->iommu_en)
3273		- q->mem_ops = &vb2_dma_sg_memops;
3274		- else
3275		- q->mem_ops = &vb2_dma_contig_memops;
	6428	+ q->mem_ops = hw_dev->mem_ops;
3276	6429	q->buf_struct_size = sizeof(struct rkcif_buffer);
3277	6430	if (stream->cifdev->is_use_dummybuf)
3278	6431	q->min_buffers_needed = 1;
..	..	@@ -3284,14 +6437,17 @@
3284	6437	q->allow_cache_hints = 1;
3285	6438	q->bidirectional = 1;
3286	6439	q->gfp_flags = GFP_DMA32;
	6440	+ if (hw_dev->is_dma_contig)
	6441	+ q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
3287	6442	return vb2_queue_init(q);
3288	6443	}
3289	6444
3290		-static void rkcif_set_fmt(struct rkcif_stream *stream,
3291		- struct v4l2_pix_format_mplane *pixm,
3292		- bool try)
	6445	+int rkcif_set_fmt(struct rkcif_stream *stream,
	6446	+ struct v4l2_pix_format_mplane *pixm,
	6447	+ bool try)
3293	6448	{
3294	6449	struct rkcif_device *dev = stream->cifdev;
	6450	+ struct sditf_priv *priv = dev->sditf[0];
3295	6451	const struct cif_output_fmt *fmt;
3296	6452	const struct cif_input_fmt *cif_fmt_in = NULL;
3297	6453	struct v4l2_rect input_rect;
..	..	@@ -3299,9 +6455,13 @@
3299	6455	u32 xsubs = 1, ysubs = 1, i;
3300	6456	struct rkmodule_hdr_cfg hdr_cfg;
3301	6457	struct rkcif_extend_info *extend_line = &stream->extend_line;
3302		- int ret, vc;
	6458	+ struct csi_channel_info *channel_info = &dev->channels[stream->id];
	6459	+ int ret;
3303	6460
3304		- fmt = find_output_fmt(stream, pixm->pixelformat);
	6461	+ for (i = 0; i < RKCIF_MAX_PLANE; i++)
	6462	+ memset(&pixm->plane_fmt[i], 0, sizeof(struct v4l2_plane_pix_format));
	6463	+
	6464	+ fmt = rkcif_find_output_fmt(stream, pixm->pixelformat);
3305	6465	if (!fmt)
3306	6466	fmt = &out_fmts[0];
3307	6467
..	..	@@ -3309,10 +6469,19 @@
3309	6469	input_rect.height = RKCIF_DEFAULT_HEIGHT;
3310	6470
3311	6471	if (dev->terminal_sensor.sd) {
3312		- cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
3313		- &input_rect, stream->id, &vc);
	6472	+ cif_fmt_in = rkcif_get_input_fmt(dev,
	6473	+ &input_rect, stream->id,
	6474	+ channel_info);
3314	6475	stream->cif_fmt_in = cif_fmt_in;
	6476	+ } else {
	6477	+ v4l2_err(&stream->cifdev->v4l2_dev,
	6478	+ "terminal subdev does not exist\n");
	6479	+ return -EINVAL;
3315	6480	}
	6481	+
	6482	+ ret = rkcif_output_fmt_check(stream, fmt);
	6483	+ if (ret)
	6484	+ return -EINVAL;
3316	6485
3317	6486	if (dev->terminal_sensor.sd) {
3318	6487	ret = v4l2_subdev_call(dev->terminal_sensor.sd,
..	..	@@ -3320,9 +6489,9 @@
3320	6489	RKMODULE_GET_HDR_CFG,
3321	6490	&hdr_cfg);
3322	6491	if (!ret)
3323		- dev->hdr.mode = hdr_cfg.hdr_mode;
	6492	+ dev->hdr = hdr_cfg;
3324	6493	else
3325		- dev->hdr.mode = NO_HDR;
	6494	+ dev->hdr.hdr_mode = NO_HDR;
3326	6495
3327	6496	dev->terminal_sensor.raw_rect = input_rect;
3328	6497	}
..	..	@@ -3343,6 +6512,11 @@
3343	6512	fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
3344	6513
3345	6514	planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
	6515	+
	6516	+ if (cif_fmt_in &&
	6517	+ (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 \|\|
	6518	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8))
	6519	+ stream->crop_enable = false;
3346	6520
3347	6521	for (i = 0; i < planes; i++) {
3348	6522	struct v4l2_plane_pix_format *plane_fmt;
..	..	@@ -3366,6 +6540,9 @@
3366	6540	}
3367	6541	}
3368	6542
	6543	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	6544	+ height *= dev->sditf_cnt;
	6545	+
3369	6546	extend_line->pixm.height = height + RKMODULE_EXTEND_LINE;
3370	6547
3371	6548	/* compact mode need bytesperline 4bytes align,
..	..	@@ -3373,25 +6550,29 @@
3373	6550	* to optimize reading and writing of ddr, aliged with 256.
3374	6551	*/
3375	6552	if (fmt->fmt_type == CIF_FMT_TYPE_RAW &&
3376		- (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
3377		- stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8)) {
	6553	+ cif_fmt_in &&
	6554	+ (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
	6555	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8)) {
3378	6556	stream->is_compact = false;
3379	6557	}
3380	6558
3381	6559	if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
3382		- (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
	6560	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	6561	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
3383	6562	dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) &&
3384		- fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888) {
3385		- bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
3386		- } else if (fmt->fourcc == V4L2_PIX_FMT_GREY \|\|
3387		- fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
3388		- fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
3389		- fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
3390		- fmt->fourcc == V4L2_PIX_FMT_SBGGR8) {
	6563	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	6564	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
3391	6565	bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
3392	6566	} else {
3393		- bpp = rkcif_align_bits_per_pixel(stream, fmt, i);
3394		- bpl = width * bpp / CIF_YUV_STORED_BIT_WIDTH;
	6567	+ if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
	6568	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	6569	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565 &&
	6570	+ dev->chip_id >= CHIP_RK3588_CIF) {
	6571	+ bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
	6572	+ } else {
	6573	+ bpp = rkcif_align_bits_per_pixel(stream, fmt, i);
	6574	+ bpl = width * bpp / CIF_YUV_STORED_BIT_WIDTH;
	6575	+ }
3395	6576	}
3396	6577	size = bpl * height;
3397	6578	imagesize += size;
..	..	@@ -3431,6 +6612,7 @@
3431	6612	pixm->width, pixm->height,
3432	6613	stream->pixm.width, stream->pixm.height);
3433	6614	}
	6615	+ return 0;
3434	6616	}
3435	6617
3436	6618	void rkcif_stream_init(struct rkcif_device *dev, u32 id)
..	..	@@ -3445,6 +6627,9 @@
3445	6627	stream->cifdev = dev;
3446	6628
3447	6629	INIT_LIST_HEAD(&stream->buf_head);
	6630	+ INIT_LIST_HEAD(&stream->rx_buf_head);
	6631	+ INIT_LIST_HEAD(&stream->rx_buf_head_vicap);
	6632	+ INIT_LIST_HEAD(&stream->rockit_buf_head);
3448	6633	spin_lock_init(&stream->vbq_lock);
3449	6634	spin_lock_init(&stream->fps_lock);
3450	6635	stream->state = RKCIF_STATE_READY;
..	..	@@ -3480,6 +6665,8 @@
3480	6665	}
3481	6666
3482	6667	stream->is_high_align = false;
	6668	+ stream->is_finish_stop_dma = false;
	6669	+ stream->is_wait_dma_stop = false;
3483	6670
3484	6671	if (dev->chip_id == CHIP_RV1126_CIF \|\|
3485	6672	dev->chip_id == CHIP_RV1126_CIF_LITE)
..	..	@@ -3499,7 +6686,19 @@
3499	6686	dev->wait_line_cache = 0;
3500	6687	dev->wait_line_bak = 0;
3501	6688	}
3502		-
	6689	+ stream->cur_stream_mode = 0;
	6690	+ stream->dma_en = 0;
	6691	+ stream->to_en_dma = 0;
	6692	+ stream->to_stop_dma = 0;
	6693	+ stream->to_en_scale = false;
	6694	+ stream->buf_owner = 0;
	6695	+ stream->buf_replace_cnt = 0;
	6696	+ stream->is_stop_capture = false;
	6697	+ stream->is_single_cap = false;
	6698	+ atomic_set(&stream->buf_cnt, 0);
	6699	+ stream->rx_buf_num = 0;
	6700	+ init_completion(&stream->stop_complete);
	6701	+ stream->is_wait_stop_complete = false;
3503	6702	}
3504	6703
3505	6704	static int rkcif_fh_open(struct file *filp)
..	..	@@ -3509,6 +6708,7 @@
3509	6708	struct rkcif_stream *stream = to_rkcif_stream(vnode);
3510	6709	struct rkcif_device *cifdev = stream->cifdev;
3511	6710	int ret;
	6711	+ int i = 0;
3512	6712
3513	6713	ret = rkcif_attach_hw(cifdev);
3514	6714	if (ret)
..	..	@@ -3524,31 +6724,35 @@
3524	6724	return ret;
3525	6725	}
3526	6726
3527		- /*
3528		- * Soft reset via CRU.
3529		- * Because CRU would reset iommu too, so there's not chance
3530		- * to reset cif once we hold buffers after buf queued
3531		- */
3532		- if (cifdev->chip_id == CHIP_RK1808_CIF \|\|
3533		- cifdev->chip_id == CHIP_RV1126_CIF \|\|
3534		- cifdev->chip_id == CHIP_RV1126_CIF_LITE \|\|
3535		- cifdev->chip_id == CHIP_RK3568_CIF) {
3536		- mutex_lock(&cifdev->stream_lock);
3537		- if (!atomic_read(&cifdev->fh_cnt))
3538		- rkcif_soft_reset(cifdev, true);
3539		- atomic_inc(&cifdev->fh_cnt);
3540		- mutex_unlock(&cifdev->stream_lock);
3541		- } else {
3542		- rkcif_soft_reset(cifdev, true);
	6727	+ ret = pm_runtime_resume_and_get(cifdev->dev);
	6728	+ if (ret < 0) {
	6729	+ v4l2_err(vdev, "Failed to get runtime pm, %d\n",
	6730	+ ret);
	6731	+ return ret;
3543	6732	}
3544	6733
3545	6734	ret = v4l2_fh_open(filp);
3546	6735	if (!ret) {
3547		- ret = v4l2_pipeline_pm_use(&vnode->vdev.entity, 1);
	6736	+ mutex_lock(&cifdev->stream_lock);
	6737	+ ret = v4l2_pipeline_pm_get(&vnode->vdev.entity);
	6738	+ v4l2_info(vdev, "open video, entity use_countt %d\n",
	6739	+ vnode->vdev.entity.use_count);
	6740	+ mutex_unlock(&cifdev->stream_lock);
3548	6741	if (ret < 0)
3549	6742	vb2_fop_release(filp);
3550	6743	}
3551		-
	6744	+ if (cifdev->sditf_cnt > 1) {
	6745	+ for (i = 0; i < cifdev->sditf_cnt; i++) {
	6746	+ if (cifdev->sditf[i]->sensor_sd)
	6747	+ ret \|= v4l2_subdev_call(cifdev->sditf[i]->sensor_sd,
	6748	+ core,
	6749	+ s_power,
	6750	+ 1);
	6751	+ }
	6752	+ if (ret < 0)
	6753	+ v4l2_err(vdev, "set sensor power on fail, ret %d\n",
	6754	+ ret);
	6755	+ }
3552	6756	return ret;
3553	6757	}
3554	6758
..	..	@@ -3559,22 +6763,30 @@
3559	6763	struct rkcif_stream *stream = to_rkcif_stream(vnode);
3560	6764	struct rkcif_device *cifdev = stream->cifdev;
3561	6765	int ret = 0;
	6766	+ int i = 0;
3562	6767
3563	6768	ret = vb2_fop_release(filp);
3564	6769	if (!ret) {
3565		- ret = v4l2_pipeline_pm_use(&vnode->vdev.entity, 0);
3566		- if (ret < 0)
3567		- v4l2_err(&cifdev->v4l2_dev,
3568		- "set pipeline power failed %d\n", ret);
	6770	+ mutex_lock(&cifdev->stream_lock);
	6771	+ v4l2_pipeline_pm_put(&vnode->vdev.entity);
	6772	+ v4l2_info(vdev, "close video, entity use_count %d\n",
	6773	+ vnode->vdev.entity.use_count);
	6774	+ mutex_unlock(&cifdev->stream_lock);
3569	6775	}
3570	6776
3571		- mutex_lock(&cifdev->stream_lock);
3572		- if (!atomic_dec_return(&cifdev->fh_cnt))
3573		- rkcif_soft_reset(cifdev, true);
3574		- else if (atomic_read(&cifdev->fh_cnt) < 0)
3575		- atomic_set(&cifdev->fh_cnt, 0);
3576		- mutex_unlock(&cifdev->stream_lock);
3577		-
	6777	+ pm_runtime_put_sync(cifdev->dev);
	6778	+ if (cifdev->sditf_cnt > 1) {
	6779	+ for (i = 0; i < cifdev->sditf_cnt; i++) {
	6780	+ if (cifdev->sditf[i]->sensor_sd)
	6781	+ ret \|= v4l2_subdev_call(cifdev->sditf[i]->sensor_sd,
	6782	+ core,
	6783	+ s_power,
	6784	+ 0);
	6785	+ }
	6786	+ if (ret < 0)
	6787	+ v4l2_err(vdev, "set sensor power on fail, ret %d\n",
	6788	+ ret);
	6789	+ }
3578	6790	return ret;
3579	6791	}
3580	6792
..	..	@@ -3584,6 +6796,9 @@
3584	6796	.unlocked_ioctl = video_ioctl2,
3585	6797	.poll = vb2_fop_poll,
3586	6798	.mmap = vb2_fop_mmap,
	6799	+#ifdef CONFIG_COMPAT
	6800	+ .compat_ioctl32 = video_ioctl2,
	6801	+#endif
3587	6802	};
3588	6803
3589	6804	static int rkcif_enum_input(struct file file, void priv,
..	..	@@ -3602,41 +6817,50 @@
3602	6817	struct v4l2_format *f)
3603	6818	{
3604	6819	struct rkcif_stream *stream = video_drvdata(file);
	6820	+ int ret = 0;
3605	6821
3606		- rkcif_set_fmt(stream, &f->fmt.pix_mp, true);
	6822	+ ret = rkcif_set_fmt(stream, &f->fmt.pix_mp, true);
3607	6823
3608		- return 0;
	6824	+ return ret;
3609	6825	}
3610	6826
3611	6827	static int rkcif_enum_framesizes(struct file file, void prov,
3612	6828	struct v4l2_frmsizeenum *fsize)
3613	6829	{
	6830	+ struct v4l2_frmsize_discrete *d = &fsize->discrete;
3614	6831	struct v4l2_frmsize_stepwise *s = &fsize->stepwise;
3615	6832	struct rkcif_stream *stream = video_drvdata(file);
3616	6833	struct rkcif_device *dev = stream->cifdev;
3617	6834	struct v4l2_rect input_rect;
3618		- int vc;
	6835	+ struct csi_channel_info csi_info;
3619	6836
3620	6837	if (fsize->index != 0)
3621	6838	return -EINVAL;
3622	6839
3623		- if (!find_output_fmt(stream, fsize->pixel_format))
	6840	+ if (!rkcif_find_output_fmt(stream, fsize->pixel_format))
3624	6841	return -EINVAL;
3625	6842
3626	6843	input_rect.width = RKCIF_DEFAULT_WIDTH;
3627	6844	input_rect.height = RKCIF_DEFAULT_HEIGHT;
3628	6845
3629	6846	if (dev->terminal_sensor.sd)
3630		- get_input_fmt(dev->terminal_sensor.sd,
3631		- &input_rect, stream->id, &vc);
	6847	+ rkcif_get_input_fmt(dev,
	6848	+ &input_rect, stream->id,
	6849	+ &csi_info);
3632	6850
3633		- fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
3634		- s->min_width = CIF_MIN_WIDTH;
3635		- s->min_height = CIF_MIN_HEIGHT;
3636		- s->max_width = input_rect.width;
3637		- s->max_height = input_rect.height;
3638		- s->step_width = OUTPUT_STEP_WISE;
3639		- s->step_height = OUTPUT_STEP_WISE;
	6851	+ if (dev->hw_dev->adapt_to_usbcamerahal) {
	6852	+ fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
	6853	+ d->width = input_rect.width;
	6854	+ d->height = input_rect.height;
	6855	+ } else {
	6856	+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
	6857	+ s->min_width = CIF_MIN_WIDTH;
	6858	+ s->min_height = CIF_MIN_HEIGHT;
	6859	+ s->max_width = input_rect.width;
	6860	+ s->max_height = input_rect.height;
	6861	+ s->step_width = OUTPUT_STEP_WISE;
	6862	+ s->step_height = OUTPUT_STEP_WISE;
	6863	+ }
3640	6864
3641	6865	return 0;
3642	6866	}
..	..	@@ -3668,13 +6892,19 @@
3668	6892	fi.interval.denominator = 30;
3669	6893	}
3670	6894
3671		- fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
3672		- fival->stepwise.step.numerator = 1;
3673		- fival->stepwise.step.denominator = 1;
3674		- fival->stepwise.max.numerator = 1;
3675		- fival->stepwise.max.denominator = 1;
3676		- fival->stepwise.min.numerator = fi.interval.numerator;
3677		- fival->stepwise.min.denominator = fi.interval.denominator;
	6895	+ if (dev->hw_dev->adapt_to_usbcamerahal) {
	6896	+ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
	6897	+ fival->discrete.numerator = fi.interval.numerator;
	6898	+ fival->discrete.denominator = fi.interval.denominator;
	6899	+ } else {
	6900	+ fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
	6901	+ fival->stepwise.step.numerator = 1;
	6902	+ fival->stepwise.step.denominator = 1;
	6903	+ fival->stepwise.max.numerator = 1;
	6904	+ fival->stepwise.max.denominator = 1;
	6905	+ fival->stepwise.min.numerator = fi.interval.numerator;
	6906	+ fival->stepwise.min.denominator = fi.interval.denominator;
	6907	+ }
3678	6908
3679	6909	return 0;
3680	6910	}
..	..	@@ -3683,13 +6913,57 @@
3683	6913	struct v4l2_fmtdesc *f)
3684	6914	{
3685	6915	const struct cif_output_fmt *fmt = NULL;
	6916	+ struct rkcif_stream *stream = video_drvdata(file);
	6917	+ struct rkcif_device *dev = stream->cifdev;
	6918	+ const struct cif_input_fmt *cif_fmt_in = NULL;
	6919	+ struct v4l2_rect input_rect;
	6920	+ int i = 0;
	6921	+ int ret = 0;
	6922	+ int fource_idx = 0;
3686	6923
3687	6924	if (f->index >= ARRAY_SIZE(out_fmts))
3688	6925	return -EINVAL;
3689	6926
3690		- fmt = &out_fmts[f->index];
3691		- f->pixelformat = fmt->fourcc;
	6927	+ if (dev->terminal_sensor.sd) {
	6928	+ cif_fmt_in = rkcif_get_input_fmt(dev,
	6929	+ &input_rect, stream->id,
	6930	+ &dev->channels[stream->id]);
	6931	+ stream->cif_fmt_in = cif_fmt_in;
	6932	+ } else {
	6933	+ v4l2_err(&stream->cifdev->v4l2_dev,
	6934	+ "terminal subdev does not exist\n");
	6935	+ return -EINVAL;
	6936	+ }
3692	6937
	6938	+ if (f->index != 0)
	6939	+ fource_idx = stream->new_fource_idx;
	6940	+
	6941	+ for (i = fource_idx; i < ARRAY_SIZE(out_fmts); i++) {
	6942	+ fmt = &out_fmts[i];
	6943	+ ret = rkcif_output_fmt_check(stream, fmt);
	6944	+ if (!ret) {
	6945	+ f->pixelformat = fmt->fourcc;
	6946	+ stream->new_fource_idx = i + 1;
	6947	+ break;
	6948	+ }
	6949	+ }
	6950	+ if (i == ARRAY_SIZE(out_fmts))
	6951	+ return -EINVAL;
	6952	+
	6953	+ switch (f->pixelformat) {
	6954	+ case V4l2_PIX_FMT_EBD8:
	6955	+ strscpy(f->description,
	6956	+ "Embedded data 8-bit",
	6957	+ sizeof(f->description));
	6958	+ break;
	6959	+ case V4l2_PIX_FMT_SPD16:
	6960	+ strscpy(f->description,
	6961	+ "Shield pix data 16-bit",
	6962	+ sizeof(f->description));
	6963	+ break;
	6964	+ default:
	6965	+ break;
	6966	+ }
3693	6967	return 0;
3694	6968	}
3695	6969
..	..	@@ -3698,15 +6972,16 @@
3698	6972	{
3699	6973	struct rkcif_stream *stream = video_drvdata(file);
3700	6974	struct rkcif_device *dev = stream->cifdev;
	6975	+ int ret = 0;
3701	6976
3702	6977	if (vb2_is_busy(&stream->vnode.buf_queue)) {
3703	6978	v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
3704	6979	return -EBUSY;
3705	6980	}
3706	6981
3707		- rkcif_set_fmt(stream, &f->fmt.pix_mp, false);
	6982	+ ret = rkcif_set_fmt(stream, &f->fmt.pix_mp, false);
3708	6983
3709		- return 0;
	6984	+ return ret;
3710	6985	}
3711	6986
3712	6987	static int rkcif_g_fmt_vid_cap_mplane(struct file file, void fh,
..	..	@@ -3733,8 +7008,8 @@
3733	7008	return 0;
3734	7009	}
3735	7010
3736		-static int rkcif_cropcap(struct file file, void fh,
3737		- struct v4l2_cropcap *cap)
	7011	+static __maybe_unused int rkcif_cropcap(struct file file, void fh,
	7012	+ struct v4l2_cropcap *cap)
3738	7013	{
3739	7014	struct rkcif_stream *stream = video_drvdata(file);
3740	7015	struct rkcif_device *dev = stream->cifdev;
..	..	@@ -3760,78 +7035,16 @@
3760	7035	return ret;
3761	7036	}
3762	7037
3763		-static int rkcif_s_crop(struct file file, void fh, const struct v4l2_crop *a)
3764		-{
3765		- struct rkcif_stream *stream = video_drvdata(file);
3766		- struct rkcif_device *dev = stream->cifdev;
3767		- const struct v4l2_rect *rect = &a->c;
3768		- struct v4l2_rect sensor_crop;
3769		- struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
3770		- int ret;
3771		-
3772		- ret = rkcif_sanity_check_fmt(stream, rect);
3773		- if (ret) {
3774		- v4l2_err(&dev->v4l2_dev, "set crop failed\n");
3775		- return ret;
3776		- }
3777		-
3778		- if (stream->crop_mask & CROP_SRC_SENSOR) {
3779		- sensor_crop = stream->crop[CROP_SRC_SENSOR];
3780		- if (rect->left + rect->width > sensor_crop.width \|\|
3781		- rect->top + rect->height > sensor_crop.height) {
3782		- v4l2_err(&dev->v4l2_dev,
3783		- "crop size is bigger than sensor input:left:%d, top:%d, width:%d, height:%d\n",
3784		- sensor_crop.left, sensor_crop.top, sensor_crop.width, sensor_crop.height);
3785		- return -EINVAL;
3786		- }
3787		- } else {
3788		- if (rect->left + rect->width > raw_rect->width \|\|
3789		- rect->top + rect->height > raw_rect->height) {
3790		- v4l2_err(&dev->v4l2_dev,
3791		- "crop size is bigger than sensor raw input:left:%d, top:%d, width:%d, height:%d\n",
3792		- raw_rect->left, raw_rect->top, raw_rect->width, raw_rect->height);
3793		- return -EINVAL;
3794		- }
3795		- }
3796		-
3797		- stream->crop[CROP_SRC_USR] = *rect;
3798		- stream->crop_enable = true;
3799		- stream->crop_mask \|= CROP_SRC_USR_MASK;
3800		- stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_USR];
3801		- if (stream->crop_mask & CROP_SRC_SENSOR) {
3802		- stream->crop[CROP_SRC_ACT].left = sensor_crop.left + stream->crop[CROP_SRC_USR].left;
3803		- stream->crop[CROP_SRC_ACT].top = sensor_crop.top + stream->crop[CROP_SRC_USR].top;
3804		- }
3805		-
3806		- if (stream->state == RKCIF_STATE_STREAMING) {
3807		- stream->crop_dyn_en = true;
3808		-
3809		- v4l2_info(&dev->v4l2_dev, "enable dynamic crop, S_CROP(%ux%u@%u:%u) type: %d\n",
3810		- rect->width, rect->height, rect->left, rect->top, a->type);
3811		- } else {
3812		- v4l2_info(&dev->v4l2_dev, "static crop, S_CROP(%ux%u@%u:%u) type: %d\n",
3813		- rect->width, rect->height, rect->left, rect->top, a->type);
3814		- }
3815		-
3816		- return ret;
3817		-}
3818		-
3819		-static int rkcif_g_crop(struct file file, void fh, struct v4l2_crop *a)
3820		-{
3821		- struct rkcif_stream *stream = video_drvdata(file);
3822		-
3823		- a->c = stream->crop[CROP_SRC_ACT];
3824		-
3825		- return 0;
3826		-}
3827		-
3828	7038	static int rkcif_s_selection(struct file file, void fh,
3829		- struct v4l2_selection *s)
	7039	+ struct v4l2_selection *s)
3830	7040	{
3831	7041	struct rkcif_stream *stream = video_drvdata(file);
3832	7042	struct rkcif_device *dev = stream->cifdev;
3833	7043	struct v4l2_subdev *sensor_sd;
3834	7044	struct v4l2_subdev_selection sd_sel;
	7045	+ const struct v4l2_rect *rect = &s->r;
	7046	+ struct v4l2_rect sensor_crop;
	7047	+ struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
3835	7048	u16 pad = 0;
3836	7049	int ret = 0;
3837	7050
..	..	@@ -3840,18 +7053,69 @@
3840	7053	goto err;
3841	7054	}
3842	7055
3843		- sensor_sd = get_remote_sensor(stream, &pad);
	7056	+ if (s->target == V4L2_SEL_TGT_CROP_BOUNDS) {
	7057	+ sensor_sd = get_remote_sensor(stream, &pad);
3844	7058
3845		- sd_sel.r = s->r;
3846		- sd_sel.pad = pad;
3847		- sd_sel.target = s->target;
3848		- sd_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	7059	+ sd_sel.r = s->r;
	7060	+ sd_sel.pad = pad;
	7061	+ sd_sel.target = s->target;
	7062	+ sd_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
3849	7063
3850		- ret = v4l2_subdev_call(sensor_sd, pad, set_selection, NULL, &sd_sel);
3851		- if (!ret) {
3852		- s->r = sd_sel.r;
3853		- v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s: pad:%d, which:%d, target:%d\n",
3854		- __func__, pad, sd_sel.which, sd_sel.target);
	7064	+ ret = v4l2_subdev_call(sensor_sd, pad, set_selection, NULL, &sd_sel);
	7065	+ if (!ret) {
	7066	+ s->r = sd_sel.r;
	7067	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s: pad:%d, which:%d, target:%d\n",
	7068	+ __func__, pad, sd_sel.which, sd_sel.target);
	7069	+ }
	7070	+ } else if (s->target == V4L2_SEL_TGT_CROP) {
	7071	+ ret = rkcif_sanity_check_fmt(stream, rect);
	7072	+ if (ret) {
	7073	+ v4l2_err(&dev->v4l2_dev, "set crop failed\n");
	7074	+ return ret;
	7075	+ }
	7076	+
	7077	+ if (stream->crop_mask & CROP_SRC_SENSOR) {
	7078	+ sensor_crop = stream->crop[CROP_SRC_SENSOR];
	7079	+ if (rect->left + rect->width > sensor_crop.width \|\|
	7080	+ rect->top + rect->height > sensor_crop.height) {
	7081	+ v4l2_err(&dev->v4l2_dev,
	7082	+ "crop size is bigger than sensor input:left:%d, top:%d, width:%d, height:%d\n",
	7083	+ sensor_crop.left, sensor_crop.top,
	7084	+ sensor_crop.width, sensor_crop.height);
	7085	+ return -EINVAL;
	7086	+ }
	7087	+ } else {
	7088	+ if (rect->left + rect->width > raw_rect->width \|\|
	7089	+ rect->top + rect->height > raw_rect->height) {
	7090	+ v4l2_err(&dev->v4l2_dev,
	7091	+ "crop size is bigger than sensor raw input:left:%d, top:%d, width:%d, height:%d\n",
	7092	+ raw_rect->left, raw_rect->top,
	7093	+ raw_rect->width, raw_rect->height);
	7094	+ return -EINVAL;
	7095	+ }
	7096	+ }
	7097	+
	7098	+ stream->crop[CROP_SRC_USR] = *rect;
	7099	+ stream->crop_enable = true;
	7100	+ stream->crop_mask \|= CROP_SRC_USR_MASK;
	7101	+ stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_USR];
	7102	+ if (stream->crop_mask & CROP_SRC_SENSOR) {
	7103	+ sensor_crop = stream->crop[CROP_SRC_SENSOR];
	7104	+ stream->crop[CROP_SRC_ACT].left = sensor_crop.left + stream->crop[CROP_SRC_USR].left;
	7105	+ stream->crop[CROP_SRC_ACT].top = sensor_crop.top + stream->crop[CROP_SRC_USR].top;
	7106	+ }
	7107	+
	7108	+ if (stream->state == RKCIF_STATE_STREAMING) {
	7109	+ stream->crop_dyn_en = true;
	7110	+
	7111	+ v4l2_info(&dev->v4l2_dev, "enable dynamic crop, S_SELECTION(%ux%u@%u:%u) target: %d\n",
	7112	+ rect->width, rect->height, rect->left, rect->top, s->target);
	7113	+ } else {
	7114	+ v4l2_info(&dev->v4l2_dev, "static crop, S_SELECTION(%ux%u@%u:%u) target: %d\n",
	7115	+ rect->width, rect->height, rect->left, rect->top, s->target);
	7116	+ }
	7117	+ } else {
	7118	+ goto err;
3855	7119	}
3856	7120
3857	7121	return ret;
..	..	@@ -3861,7 +7125,7 @@
3861	7125	}
3862	7126
3863	7127	static int rkcif_g_selection(struct file file, void fh,
3864		- struct v4l2_selection *s)
	7128	+ struct v4l2_selection *s)
3865	7129	{
3866	7130	struct rkcif_stream *stream = video_drvdata(file);
3867	7131	struct rkcif_device *dev = stream->cifdev;
..	..	@@ -3912,19 +7176,144 @@
3912	7176	return -EINVAL;
3913	7177	}
3914	7178
	7179	+static int rkcif_get_max_common_div(int a, int b)
	7180	+{
	7181	+ int remainder = a % b;
	7182	+
	7183	+ while (remainder != 0) {
	7184	+ a = b;
	7185	+ b = remainder;
	7186	+ remainder = a % b;
	7187	+ }
	7188	+ return b;
	7189	+}
	7190	+
	7191	+void rkcif_set_fps(struct rkcif_stream stream, struct rkcif_fps fps)
	7192	+{
	7193	+ struct rkcif_sensor_info *sensor = &stream->cifdev->terminal_sensor;
	7194	+ struct rkcif_device *cif_dev = stream->cifdev;
	7195	+ struct rkcif_stream *tmp_stream = NULL;
	7196	+ u32 numerator, denominator;
	7197	+ u32 def_fps = 0;
	7198	+ u32 cur_fps = 0;
	7199	+ int cap_m, skip_n;
	7200	+ int i = 0;
	7201	+ int max_common_div;
	7202	+ bool skip_en = false;
	7203	+ s32 vblank_def = 0;
	7204	+ s32 vblank_curr = 0;
	7205	+ int ret = 0;
	7206	+
	7207	+ if (!stream->cifdev->terminal_sensor.sd) {
	7208	+ ret = rkcif_update_sensor_info(stream);
	7209	+ if (ret) {
	7210	+ v4l2_err(&stream->cifdev->v4l2_dev,
	7211	+ "%s update sensor info fail\n",
	7212	+ __func__);
	7213	+ return;
	7214	+ }
	7215	+
	7216	+ }
	7217	+ if (!stream->cifdev->terminal_sensor.sd)
	7218	+ return;
	7219	+ numerator = sensor->fi.interval.numerator;
	7220	+ denominator = sensor->fi.interval.denominator;
	7221	+ def_fps = denominator / numerator;
	7222	+
	7223	+ vblank_def = rkcif_get_sensor_vblank_def(cif_dev);
	7224	+ vblank_curr = rkcif_get_sensor_vblank(cif_dev);
	7225	+ if (vblank_def)
	7226	+ cur_fps = def_fps * (u32)(vblank_def + sensor->raw_rect.height) /
	7227	+ (u32)(vblank_curr + sensor->raw_rect.height);
	7228	+ else
	7229	+ cur_fps = def_fps;
	7230	+
	7231	+ if (fps->fps == 0 \|\| fps->fps > cur_fps) {
	7232	+ v4l2_err(&stream->cifdev->v4l2_dev,
	7233	+ "set fps %d fps failed, current fps %d fps\n",
	7234	+ fps->fps, cur_fps);
	7235	+ return;
	7236	+ }
	7237	+ cap_m = fps->fps;
	7238	+ skip_n = cur_fps - fps->fps;
	7239	+ max_common_div = rkcif_get_max_common_div(cap_m, skip_n);
	7240	+ cap_m /= max_common_div;
	7241	+ skip_n /= max_common_div;
	7242	+ if (cap_m > 64) {
	7243	+ skip_n = skip_n / (cap_m / 64);
	7244	+ if (skip_n == 0)
	7245	+ skip_n = 1;
	7246	+ cap_m = 64;
	7247	+ }
	7248	+ if (skip_n > 7) {
	7249	+ cap_m = cap_m / (skip_n / 7);
	7250	+ if (cap_m == 0)
	7251	+ cap_m = 1;
	7252	+ skip_n = 7;
	7253	+ }
	7254	+
	7255	+ if (fps->fps == cur_fps)
	7256	+ skip_en = false;
	7257	+ else
	7258	+ skip_en = true;
	7259	+
	7260	+ if (fps->ch_num > 1 && fps->ch_num < 4) {
	7261	+ for (i = 0; i < fps->ch_num; i++) {
	7262	+ tmp_stream = &cif_dev->stream[i];
	7263	+ if (skip_en) {
	7264	+ tmp_stream->skip_info.skip_to_en = true;
	7265	+ tmp_stream->skip_info.cap_m = cap_m;
	7266	+ tmp_stream->skip_info.skip_n = skip_n;
	7267	+ } else {
	7268	+ tmp_stream->skip_info.skip_to_dis = true;
	7269	+ }
	7270	+ }
	7271	+ } else {
	7272	+ if (skip_en) {
	7273	+ stream->skip_info.skip_to_en = true;
	7274	+ stream->skip_info.cap_m = cap_m;
	7275	+ stream->skip_info.skip_n = skip_n;
	7276	+ } else {
	7277	+ stream->skip_info.skip_to_dis = true;
	7278	+ }
	7279	+ }
	7280	+ v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
	7281	+ "skip_to_en %d, cap_m %d, skip_n %d\n",
	7282	+ stream->skip_info.skip_to_en,
	7283	+ cap_m,
	7284	+ skip_n);
	7285	+}
	7286	+
	7287	+static bool rkcif_check_can_be_online(struct rkcif_device *cif_dev)
	7288	+{
	7289	+ if (cif_dev->sditf[0] == NULL \|\| cif_dev->sditf[0]->mode.name == NULL \|\|
	7290	+ (cif_dev->chip_id == CHIP_RV1106_CIF &&
	7291	+ strstr(cif_dev->sditf[0]->mode.name, "unite")))
	7292	+ return false;
	7293	+ return true;
	7294	+}
	7295	+
3915	7296	static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
3916	7297	enum rkmodule_reset_src reset_src);
	7298	+static bool rkcif_check_single_dev_stream_on(struct rkcif_hw *hw);
3917	7299
3918	7300	static long rkcif_ioctl_default(struct file file, void fh,
3919		- bool valid_prio, unsigned int cmd, void *arg)
	7301	+ bool valid_prio, unsigned int cmd, void *arg)
3920	7302	{
3921	7303	struct rkcif_stream *stream = video_drvdata(file);
3922	7304	struct rkcif_device *dev = stream->cifdev;
3923	7305	const struct cif_input_fmt *in_fmt;
3924	7306	struct v4l2_rect rect;
3925		- int vc = 0;
3926		- struct rkcif_reset_info *reset_info;
3927		- int reset_src = 0;
	7307	+ struct csi_channel_info csi_info;
	7308	+ struct rkcif_fps fps;
	7309	+ int reset_src;
	7310	+ struct rkcif_quick_stream_param *stream_param;
	7311	+ bool is_single_dev = false;
	7312	+ struct v4l2_subdev *sd;
	7313	+ int ret = -EINVAL;
	7314	+ int i = 0;
	7315	+ int stream_num = 0;
	7316	+ bool is_can_be_online = false;
3928	7317
3929	7318	switch (cmd) {
3930	7319	case RKCIF_CMD_GET_CSI_MEMORY_MODE:
..	..	@@ -3939,7 +7328,8 @@
3939	7328	break;
3940	7329	case RKCIF_CMD_SET_CSI_MEMORY_MODE:
3941	7330	if (dev->terminal_sensor.sd) {
3942		- in_fmt = get_input_fmt(dev->terminal_sensor.sd, &rect, 0, &vc);
	7331	+ in_fmt = rkcif_get_input_fmt(dev,
	7332	+ &rect, 0, &csi_info);
3943	7333	if (in_fmt == NULL) {
3944	7334	v4l2_err(&dev->v4l2_dev, "can't get sensor input format\n");
3945	7335	return -EINVAL;
..	..	@@ -3965,15 +7355,98 @@
3965	7355	stream->is_high_align = false;
3966	7356	}
3967	7357	break;
3968		- case RKCIF_CMD_GET_RESET_INFO:
3969		- reset_info = (struct rkcif_reset_info *)arg;
3970		- *reset_info = dev->hw_dev->reset_info;
3971		- if (dev->hw_dev->reset_info.is_need_reset)
3972		- dev->hw_dev->reset_info.is_need_reset = 0;
	7358	+ case RKCIF_CMD_SET_FPS:
	7359	+ fps = (struct rkcif_fps )arg;
	7360	+ rkcif_set_fps(stream, &fps);
3973	7361	break;
3974	7362	case RKCIF_CMD_SET_RESET:
3975	7363	reset_src = (int )arg;
3976	7364	return rkcif_do_reset_work(dev, reset_src);
	7365	+ case RKCIF_CMD_SET_QUICK_STREAM:
	7366	+ stream_param = (struct rkcif_quick_stream_param *)arg;
	7367	+ if (!dev->sditf[0])
	7368	+ return -EINVAL;
	7369	+ if (dev->hdr.hdr_mode == HDR_X2)
	7370	+ stream_num = 2;
	7371	+ else if (dev->hdr.hdr_mode == HDR_X3)
	7372	+ stream_num = 3;
	7373	+ else
	7374	+ stream_num = 1;
	7375	+ if (stream_param->on) {
	7376	+ for (i = 0; i < stream_num; i++)
	7377	+ dev->stream[i].cur_skip_frame = dev->stream[i].skip_frame;
	7378	+ is_single_dev = rkcif_check_single_dev_stream_on(dev->hw_dev);
	7379	+ is_can_be_online = rkcif_check_can_be_online(dev);
	7380	+ if (is_single_dev && is_can_be_online) {
	7381	+ for (i = 0; i < stream_num - 1; i++) {
	7382	+ dev->stream[i].to_en_dma = RKCIF_DMAEN_BY_ISP;
	7383	+ rkcif_enable_dma_capture(&dev->stream[i], true);
	7384	+ }
	7385	+ dev->sditf[0]->mode.rdbk_mode = RKISP_VICAP_ONLINE;
	7386	+ sditf_change_to_online(dev->sditf[0]);
	7387	+ sd = get_rkisp_sd(dev->sditf[0]);
	7388	+ if (sd)
	7389	+ ret = v4l2_subdev_call(sd, core, ioctl,
	7390	+ RKISP_VICAP_CMD_MODE, &dev->sditf[0]->mode);
	7391	+ if (ret) {
	7392	+ v4l2_err(&dev->v4l2_dev, "set isp work mode online fail\n");
	7393	+ return -EINVAL;
	7394	+ }
	7395	+ } else {
	7396	+ sditf_disable_immediately(dev->sditf[0]);
	7397	+ dev->sditf[0]->mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO;
	7398	+ sd = get_rkisp_sd(dev->sditf[0]);
	7399	+ if (sd)
	7400	+ ret = v4l2_subdev_call(sd, core, ioctl,
	7401	+ RKISP_VICAP_CMD_MODE, &dev->sditf[0]->mode);
	7402	+ for (i = 0; i < stream_num; i++) {
	7403	+ if (dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO)
	7404	+ dev->stream[i].to_en_dma = RKCIF_DMAEN_BY_ISP;
	7405	+ else
	7406	+ dev->stream[i].to_en_dma = RKCIF_DMAEN_BY_VICAP;
	7407	+ rkcif_enable_dma_capture(&dev->stream[i], true);
	7408	+ }
	7409	+ }
	7410	+ rkcif_dphy_quick_stream(dev, stream_param->on);
	7411	+ v4l2_subdev_call(dev->terminal_sensor.sd, core, ioctl,
	7412	+ RKMODULE_SET_QUICK_STREAM, &stream_param->on);
	7413	+ } else {
	7414	+ if (dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_ONLINE) {
	7415	+ for (i = 0; i < stream_num - 1; i++) {
	7416	+ reinit_completion(&dev->stream[i].stop_complete);
	7417	+ dev->stream[i].is_wait_stop_complete = true;
	7418	+ dev->stream[i].to_stop_dma = RKCIF_DMAEN_BY_ISP;
	7419	+ wait_for_completion_timeout(&dev->stream[i].stop_complete,
	7420	+ msecs_to_jiffies(RKCIF_STOP_MAX_WAIT_TIME_MS));
	7421	+ }
	7422	+ stream->cifdev->sensor_state = stream_param->on;
	7423	+ stream->cifdev->sensor_state_change = true;
	7424	+ dev->stream[i].is_wait_stop_complete = true;
	7425	+ wait_for_completion_timeout(&dev->stream[i].stop_complete,
	7426	+ msecs_to_jiffies(RKCIF_STOP_MAX_WAIT_TIME_MS));
	7427	+ } else {
	7428	+ for (i = 0; i < stream_num; i++) {
	7429	+ dev->stream[i].is_wait_stop_complete = true;
	7430	+ reinit_completion(&dev->stream[i].stop_complete);
	7431	+ if (dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO)
	7432	+ dev->stream[i].to_stop_dma = RKCIF_DMAEN_BY_ISP;
	7433	+ else
	7434	+ dev->stream[i].to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	7435	+ wait_for_completion_timeout(&dev->stream[i].stop_complete,
	7436	+ msecs_to_jiffies(RKCIF_STOP_MAX_WAIT_TIME_MS));
	7437	+ }
	7438	+ rkcif_dphy_quick_stream(dev, stream_param->on);
	7439	+ v4l2_subdev_call(dev->terminal_sensor.sd, core, ioctl,
	7440	+ RKMODULE_SET_QUICK_STREAM, &stream_param->on);
	7441	+ }
	7442	+ stream_param->frame_num = dev->stream[0].frame_idx - 1;
	7443	+ if (!dev->is_rtt_suspend) {
	7444	+ dev->resume_mode = stream_param->resume_mode;
	7445	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	7446	+ "set resume mode %d\n", dev->resume_mode);
	7447	+ }
	7448	+ }
	7449	+ break;
3977	7450	default:
3978	7451	return -EINVAL;
3979	7452	}
..	..	@@ -3993,13 +7466,10 @@
3993	7466	.vidioc_streamoff = vb2_ioctl_streamoff,
3994	7467	.vidioc_enum_input = rkcif_enum_input,
3995	7468	.vidioc_try_fmt_vid_cap_mplane = rkcif_try_fmt_vid_cap_mplane,
3996		- .vidioc_enum_fmt_vid_cap_mplane = rkcif_enum_fmt_vid_cap_mplane,
	7469	+ .vidioc_enum_fmt_vid_cap = rkcif_enum_fmt_vid_cap_mplane,
3997	7470	.vidioc_s_fmt_vid_cap_mplane = rkcif_s_fmt_vid_cap_mplane,
3998	7471	.vidioc_g_fmt_vid_cap_mplane = rkcif_g_fmt_vid_cap_mplane,
3999	7472	.vidioc_querycap = rkcif_querycap,
4000		- .vidioc_cropcap = rkcif_cropcap,
4001		- .vidioc_s_crop = rkcif_s_crop,
4002		- .vidioc_g_crop = rkcif_g_crop,
4003	7473	.vidioc_s_selection = rkcif_s_selection,
4004	7474	.vidioc_g_selection = rkcif_g_selection,
4005	7475	.vidioc_enum_frameintervals = rkcif_enum_frameintervals,
..	..	@@ -4007,8 +7477,59 @@
4007	7477	.vidioc_default = rkcif_ioctl_default,
4008	7478	};
4009	7479
	7480	+void rkcif_vb_done_oneframe(struct rkcif_stream *stream,
	7481	+ struct vb2_v4l2_buffer *vb_done)
	7482	+{
	7483	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	7484	+ u32 i;
	7485	+
	7486	+ /* Dequeue a filled buffer */
	7487	+ for (i = 0; i < fmt->mplanes; i++) {
	7488	+ vb2_set_plane_payload(&vb_done->vb2_buf, i,
	7489	+ stream->pixm.plane_fmt[i].sizeimage);
	7490	+ }
	7491	+
	7492	+ vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE);
	7493	+ v4l2_dbg(2, rkcif_debug, &stream->cifdev->v4l2_dev,
	7494	+ "stream[%d] vb done, index: %d, sequence %d\n", stream->id,
	7495	+ vb_done->vb2_buf.index, vb_done->sequence);
	7496	+ atomic_dec(&stream->buf_cnt);
	7497	+}
	7498	+
	7499	+static void rkcif_tasklet_handle(unsigned long data)
	7500	+{
	7501	+ struct rkcif_stream stream = (struct rkcif_stream )data;
	7502	+ struct rkcif_buffer *buf = NULL;
	7503	+ unsigned long flags = 0;
	7504	+ LIST_HEAD(local_list);
	7505	+
	7506	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	7507	+ list_replace_init(&stream->vb_done_list, &local_list);
	7508	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	7509	+
	7510	+ while (!list_empty(&local_list)) {
	7511	+ buf = list_first_entry(&local_list,
	7512	+ struct rkcif_buffer, queue);
	7513	+ list_del(&buf->queue);
	7514	+ rkcif_vb_done_oneframe(stream, &buf->vb);
	7515	+ }
	7516	+}
	7517	+
	7518	+void rkcif_vb_done_tasklet(struct rkcif_stream stream, struct rkcif_buffer buf)
	7519	+{
	7520	+ unsigned long flags = 0;
	7521	+
	7522	+ if (!stream \|\| !buf)
	7523	+ return;
	7524	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	7525	+ list_add_tail(&buf->queue, &stream->vb_done_list);
	7526	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	7527	+ tasklet_schedule(&stream->vb_done_tasklet);
	7528	+}
	7529	+
4010	7530	static void rkcif_unregister_stream_vdev(struct rkcif_stream *stream)
4011	7531	{
	7532	+ tasklet_kill(&stream->vb_done_tasklet);
4012	7533	media_entity_cleanup(&stream->vnode.vdev.entity);
4013	7534	video_unregister_device(&stream->vnode.vdev);
4014	7535	}
..	..	@@ -4042,6 +7563,7 @@
4042	7563	vdev_name = CIF_DVP_VDEV_NAME;
4043	7564	break;
4044	7565	default:
	7566	+ ret = -EINVAL;
4045	7567	v4l2_err(v4l2_dev, "Invalid stream\n");
4046	7568	goto unreg;
4047	7569	}
..	..	@@ -4064,6 +7586,7 @@
4064	7586	vdev_name = CIF_MIPI_ID3_VDEV_NAME;
4065	7587	break;
4066	7588	default:
	7589	+ ret = -EINVAL;
4067	7590	v4l2_err(v4l2_dev, "Invalid stream\n");
4068	7591	goto unreg;
4069	7592	}
..	..	@@ -4082,6 +7605,7 @@
4082	7605	vdev_name = CIF_DVP_ID3_VDEV_NAME;
4083	7606	break;
4084	7607	default:
	7608	+ ret = -EINVAL;
4085	7609	v4l2_err(v4l2_dev, "Invalid stream\n");
4086	7610	goto unreg;
4087	7611	}
..	..	@@ -4108,7 +7632,7 @@
4108	7632	V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
4109	7633	vdev->queue = &node->buf_queue;
4110	7634
4111		- ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
	7635	+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
4112	7636	if (ret < 0) {
4113	7637	v4l2_err(v4l2_dev,
4114	7638	"video_register_device failed with error %d\n", ret);
..	..	@@ -4119,6 +7643,11 @@
4119	7643	if (ret < 0)
4120	7644	goto unreg;
4121	7645
	7646	+ INIT_LIST_HEAD(&stream->vb_done_list);
	7647	+ tasklet_init(&stream->vb_done_tasklet,
	7648	+ rkcif_tasklet_handle,
	7649	+ (unsigned long)stream);
	7650	+ tasklet_disable(&stream->vb_done_tasklet);
4122	7651	return 0;
4123	7652	unreg:
4124	7653	video_unregister_device(vdev);
..	..	@@ -4151,7 +7680,7 @@
4151	7680	if (ret < 0)
4152	7681	goto err;
4153	7682	}
4154		-
	7683	+ dev->num_channels = stream_num;
4155	7684	return 0;
4156	7685	err:
4157	7686	for (j = 0; j < i; j++) {
..	..	@@ -4219,8 +7748,8 @@
4219	7748	}
4220	7749
4221	7750	static struct v4l2_rect rkcif_lvds_sd_get_crop(struct rkcif_lvds_subdev subdev,
4222		- struct v4l2_subdev_pad_config *cfg,
4223		- enum v4l2_subdev_format_whence which)
	7751	+ struct v4l2_subdev_pad_config *cfg,
	7752	+ enum v4l2_subdev_format_whence which)
4224	7753	{
4225	7754	if (which == V4L2_SUBDEV_FORMAT_TRY)
4226	7755	return v4l2_subdev_get_try_crop(&subdev->sd, cfg, RKCIF_LVDS_PAD_SINK);
..	..	@@ -4229,8 +7758,8 @@
4229	7758	}
4230	7759
4231	7760	static int rkcif_lvds_sd_set_selection(struct v4l2_subdev *sd,
4232		- struct v4l2_subdev_pad_config *cfg,
4233		- struct v4l2_subdev_selection *sel)
	7761	+ struct v4l2_subdev_pad_config *cfg,
	7762	+ struct v4l2_subdev_selection *sel)
4234	7763	{
4235	7764	struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
4236	7765	struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
..	..	@@ -4245,8 +7774,8 @@
4245	7774	}
4246	7775
4247	7776	static int rkcif_lvds_sd_get_selection(struct v4l2_subdev *sd,
4248		- struct v4l2_subdev_pad_config *cfg,
4249		- struct v4l2_subdev_selection *sel)
	7777	+ struct v4l2_subdev_pad_config *cfg,
	7778	+ struct v4l2_subdev_selection *sel)
4250	7779	{
4251	7780	struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
4252	7781	struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
..	..	@@ -4302,13 +7831,13 @@
4302	7831	return -EINVAL;
4303	7832	}
4304	7833
4305		-static int rkcif_lvds_g_mbus_config(struct v4l2_subdev *sd,
	7834	+static int rkcif_lvds_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
4306	7835	struct v4l2_mbus_config *mbus)
4307	7836	{
4308	7837	struct v4l2_subdev *sensor_sd = get_lvds_remote_sensor(sd);
4309	7838	int ret;
4310	7839
4311		- ret = v4l2_subdev_call(sensor_sd, video, g_mbus_config, mbus);
	7840	+ ret = v4l2_subdev_call(sensor_sd, pad, get_mbus_config, 0, mbus);
4312	7841	if (ret)
4313	7842	return ret;
4314	7843
..	..	@@ -4331,12 +7860,13 @@
4331	7860	}
4332	7861
4333	7862	static int rkcif_sof_subscribe_event(struct v4l2_subdev sd, struct v4l2_fh fh,
4334		- struct v4l2_event_subscription *sub)
	7863	+ struct v4l2_event_subscription *sub)
4335	7864	{
4336		- if (sub->type != V4L2_EVENT_FRAME_SYNC)
	7865	+ if (sub->type == V4L2_EVENT_FRAME_SYNC \|\|
	7866	+ sub->type == V4L2_EVENT_RESET_DEV)
	7867	+ return v4l2_event_subscribe(fh, sub, RKCIF_V4L2_EVENT_ELEMS, NULL);
	7868	+ else
4337	7869	return -EINVAL;
4338		-
4339		- return v4l2_event_subscribe(fh, sub, 0, NULL);
4340	7870	}
4341	7871
4342	7872	static const struct media_entity_operations rkcif_lvds_sd_media_ops = {
..	..	@@ -4349,10 +7879,10 @@
4349	7879	.get_fmt = rkcif_lvds_sd_get_fmt,
4350	7880	.set_selection = rkcif_lvds_sd_set_selection,
4351	7881	.get_selection = rkcif_lvds_sd_get_selection,
	7882	+ .get_mbus_config = rkcif_lvds_g_mbus_config,
4352	7883	};
4353	7884
4354	7885	static const struct v4l2_subdev_video_ops rkcif_lvds_sd_video_ops = {
4355		- .g_mbus_config = rkcif_lvds_g_mbus_config,
4356	7886	.s_stream = rkcif_lvds_sd_s_stream,
4357	7887	};
4358	7888
..	..	@@ -4390,10 +7920,12 @@
4390	7920	return 0;
4391	7921	}
4392	7922
4393		-static void rkcif_lvds_set_sof(struct rkcif_device *dev, u32 seq)
	7923	+static u32 rkcif_lvds_set_sof(struct rkcif_device *dev, u32 seq)
4394	7924	{
4395	7925	if (dev)
4396	7926	atomic_set(&dev->lvds_subdev.frm_sync_seq, seq);
	7927	+
	7928	+ return 0;
4397	7929	}
4398	7930
4399	7931	int rkcif_register_lvds_subdev(struct rkcif_device *dev)
..	..	@@ -4402,6 +7934,7 @@
4402	7934	struct rkcif_lvds_subdev *lvds_subdev = &dev->lvds_subdev;
4403	7935	struct v4l2_subdev *sd;
4404	7936	int ret;
	7937	+ int pad_num = 4;
4405	7938
4406	7939	memset(lvds_subdev, 0, sizeof(*lvds_subdev));
4407	7940	lvds_subdev->cifdev = dev;
..	..	@@ -4410,7 +7943,7 @@
4410	7943	v4l2_subdev_init(sd, &rkcif_lvds_sd_ops);
4411	7944	sd->flags \|= V4L2_SUBDEV_FL_HAS_DEVNODE \| V4L2_SUBDEV_FL_HAS_EVENTS;
4412	7945	sd->entity.ops = &rkcif_lvds_sd_media_ops;
4413		- if (dev->chip_id == CHIP_RV1126_CIF)
	7946	+ if (dev->chip_id != CHIP_RV1126_CIF_LITE)
4414	7947	snprintf(sd->name, sizeof(sd->name), "rkcif-lvds-subdev");
4415	7948	else
4416	7949	snprintf(sd->name, sizeof(sd->name), "rkcif-lite-lvds-subdev");
..	..	@@ -4421,6 +7954,13 @@
4421	7954	lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID1].flags = MEDIA_PAD_FL_SOURCE;
4422	7955	lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID2].flags = MEDIA_PAD_FL_SOURCE;
4423	7956	lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID3].flags = MEDIA_PAD_FL_SOURCE;
	7957	+ if (dev->chip_id == CHIP_RV1106_CIF) {
	7958	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID0].flags = MEDIA_PAD_FL_SOURCE;
	7959	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID1].flags = MEDIA_PAD_FL_SOURCE;
	7960	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID2].flags = MEDIA_PAD_FL_SOURCE;
	7961	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID3].flags = MEDIA_PAD_FL_SOURCE;
	7962	+ pad_num = RKCIF_LVDS_PAD_MAX;
	7963	+ }
4424	7964
4425	7965	lvds_subdev->in_fmt.width = RKCIF_DEFAULT_WIDTH;
4426	7966	lvds_subdev->in_fmt.height = RKCIF_DEFAULT_HEIGHT;
..	..	@@ -4429,7 +7969,7 @@
4429	7969	lvds_subdev->crop.width = RKCIF_DEFAULT_WIDTH;
4430	7970	lvds_subdev->crop.height = RKCIF_DEFAULT_HEIGHT;
4431	7971
4432		- ret = media_entity_pads_init(&sd->entity, RKCIF_LVDS_PAD_MAX,
	7972	+ ret = media_entity_pads_init(&sd->entity, pad_num,
4433	7973	lvds_subdev->pads);
4434	7974	if (ret < 0)
4435	7975	return ret;
..	..	@@ -4481,10 +8021,12 @@
4481	8021	return 0;
4482	8022	}
4483	8023
4484		-static void rkcif_dvp_set_sof(struct rkcif_device *dev, u32 seq)
	8024	+static u32 rkcif_dvp_set_sof(struct rkcif_device *dev, u32 seq)
4485	8025	{
4486	8026	if (dev)
4487	8027	atomic_set(&dev->dvp_sof_subdev.frm_sync_seq, seq);
	8028	+
	8029	+ return 0;
4488	8030	}
4489	8031
4490	8032	static const struct v4l2_subdev_core_ops rkcif_dvp_sof_sd_core_ops = {
..	..	@@ -4537,28 +8079,6 @@
4537	8079	v4l2_device_unregister_subdev(sd);
4538	8080	}
4539	8081
4540		-
4541		-static void rkcif_vb_done_oneframe(struct rkcif_stream *stream,
4542		- struct vb2_v4l2_buffer *vb_done)
4543		-{
4544		- const struct cif_output_fmt *fmt = stream->cif_fmt_out;
4545		- u32 i;
4546		-
4547		- /* Dequeue a filled buffer */
4548		- for (i = 0; i < fmt->mplanes; i++) {
4549		- vb2_set_plane_payload(&vb_done->vb2_buf, i,
4550		- stream->pixm.plane_fmt[i].sizeimage);
4551		- }
4552		-
4553		- if (stream->cifdev->hdr.mode == NO_HDR)
4554		- vb_done->vb2_buf.timestamp = ktime_get_ns();
4555		-
4556		- vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE);
4557		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
4558		- "stream[%d] vb done, index: %d, sequence %d\n", stream->id,
4559		- vb_done->vb2_buf.index, vb_done->sequence);
4560		-}
4561		-
4562	8082	void rkcif_irq_oneframe(struct rkcif_device *cif_dev)
4563	8083	{
4564	8084	/* TODO: xuhf-debug: add stream type */
..	..	@@ -4590,7 +8110,7 @@
4590	8110	}
4591	8111
4592	8112	if ((intstat & FRAME_END)) {
4593		- struct vb2_v4l2_buffer *vb_done = NULL;
	8113	+ struct rkcif_buffer *active_buf = NULL;
4594	8114
4595	8115	rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT,
4596	8116	FRAME_END_CLR);
..	..	@@ -4623,11 +8143,11 @@
4623	8143	if (frmid % 2 != 0) {
4624	8144	stream->frame_phase = CIF_CSI_FRAME0_READY;
4625	8145	if (stream->curr_buf)
4626		- vb_done = &stream->curr_buf->vb;
	8146	+ active_buf = stream->curr_buf;
4627	8147	} else {
4628	8148	stream->frame_phase = CIF_CSI_FRAME1_READY;
4629	8149	if (stream->next_buf)
4630		- vb_done = &stream->next_buf->vb;
	8150	+ active_buf = stream->next_buf;
4631	8151	}
4632	8152
4633	8153	/* In one-frame mode:
..	..	@@ -4640,46 +8160,28 @@
4640	8160	ret = rkcif_assign_new_buffer_oneframe(stream,
4641	8161	RKCIF_YUV_ADDR_STATE_UPDATE);
4642	8162
4643		- if (vb_done && (!ret)) {
4644		- vb_done->sequence = stream->frame_idx;
4645		- rkcif_vb_done_oneframe(stream, vb_done);
	8163	+ if (active_buf && (!ret)) {
	8164	+ active_buf->vb.sequence = stream->frame_idx - 1;
	8165	+ rkcif_vb_done_tasklet(stream, active_buf);
4646	8166	}
4647	8167
4648		- stream->frame_idx++;
4649		- cif_dev->irq_stats.all_frm_end_cnt++;
	8168	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
4650	8169	}
4651	8170	}
4652	8171
4653	8172	static int rkcif_csi_g_mipi_id(struct v4l2_device *v4l2_dev,
4654		- unsigned int intstat)
	8173	+ unsigned int intstat)
4655	8174	{
4656		- if (intstat & CSI_FRAME_END_ID0) {
4657		- if ((intstat & CSI_FRAME_END_ID0) ==
4658		- CSI_FRAME_END_ID0)
4659		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID0\n");
	8175	+ if (intstat & CSI_FRAME_END_ID0)
4660	8176	return RKCIF_STREAM_MIPI_ID0;
4661		- }
4662	8177
4663		- if (intstat & CSI_FRAME_END_ID1) {
4664		- if ((intstat & CSI_FRAME_END_ID1) ==
4665		- CSI_FRAME_END_ID1)
4666		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID1\n");
	8178	+ if (intstat & CSI_FRAME_END_ID1)
4667	8179	return RKCIF_STREAM_MIPI_ID1;
4668		- }
4669	8180
4670		- if (intstat & CSI_FRAME_END_ID2) {
4671		- if ((intstat & CSI_FRAME_END_ID2) ==
4672		- CSI_FRAME_END_ID2)
4673		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID2\n");
	8181	+ if (intstat & CSI_FRAME_END_ID2)
4674	8182	return RKCIF_STREAM_MIPI_ID2;
4675		- }
4676		-
4677		- if (intstat & CSI_FRAME_END_ID3) {
4678		- if ((intstat & CSI_FRAME_END_ID3) ==
4679		- CSI_FRAME_END_ID3)
4680		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID3\n");
	8183	+ if (intstat & CSI_FRAME_END_ID3)
4681	8184	return RKCIF_STREAM_MIPI_ID3;
4682		- }
4683	8185
4684	8186	return -EINVAL;
4685	8187	}
..	..	@@ -4688,38 +8190,42 @@
4688	8190	u32 *intstat, u32 frm_stat)
4689	8191	{
4690	8192	if (*intstat & DVP_FRAME_END_ID0) {
4691		- if ((frm_stat & DVP_CHANNEL0_FRM_READ) ==
4692		- DVP_CHANNEL0_FRM_READ)
4693		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID0\n");
4694		-
4695	8193	*intstat &= ~DVP_FRAME_END_ID0;
4696	8194	return RKCIF_STREAM_MIPI_ID0;
4697	8195	}
4698	8196
4699	8197	if (*intstat & DVP_FRAME_END_ID1) {
4700		- if ((frm_stat & DVP_CHANNEL1_FRM_READ) ==
4701		- DVP_CHANNEL1_FRM_READ)
4702		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID1\n");
4703		-
4704	8198	*intstat &= ~DVP_FRAME_END_ID1;
4705	8199	return RKCIF_STREAM_MIPI_ID1;
4706	8200	}
4707	8201
4708	8202	if (*intstat & DVP_FRAME_END_ID2) {
4709		- if ((frm_stat & DVP_CHANNEL2_FRM_READ) ==
4710		- DVP_CHANNEL2_FRM_READ)
4711		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID2\n");
4712	8203	*intstat &= ~DVP_FRAME_END_ID2;
4713	8204	return RKCIF_STREAM_MIPI_ID2;
4714	8205	}
4715	8206
4716	8207	if (*intstat & DVP_FRAME_END_ID3) {
4717		- if ((frm_stat & DVP_CHANNEL3_FRM_READ) ==
4718		- DVP_CHANNEL3_FRM_READ)
4719		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID3\n");
4720	8208	*intstat &= ~DVP_FRAME_END_ID3;
4721	8209	return RKCIF_STREAM_MIPI_ID3;
4722	8210	}
	8211	+
	8212	+ return -EINVAL;
	8213	+}
	8214	+
	8215	+static int rkcif_dvp_g_ch_id_by_fe(struct v4l2_device *v4l2_dev,
	8216	+ u32 intstat)
	8217	+{
	8218	+ if (intstat & DVP_ALL_END_ID0)
	8219	+ return RKCIF_STREAM_MIPI_ID0;
	8220	+
	8221	+ if (intstat & DVP_ALL_END_ID1)
	8222	+ return RKCIF_STREAM_MIPI_ID1;
	8223	+
	8224	+ if (intstat & DVP_ALL_END_ID2)
	8225	+ return RKCIF_STREAM_MIPI_ID2;
	8226	+
	8227	+ if (intstat & DVP_ALL_END_ID3)
	8228	+ return RKCIF_STREAM_MIPI_ID3;
4723	8229
4724	8230	return -EINVAL;
4725	8231	}
..	..	@@ -4730,7 +8236,6 @@
4730	8236	struct rkcif_device,
4731	8237	reset_watchdog_timer);
4732	8238	struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
4733		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
4734	8239	bool is_triggered = false, is_assign_triggered = false, is_first_err = false;
4735	8240	unsigned long flags;
4736	8241	u64 cur_time, diff_time;
..	..	@@ -4741,11 +8246,11 @@
4741	8246	timer->csi2_err_cnt_odd != 0) {
4742	8247	timer->csi2_err_cnt_odd = 0;
4743	8248	timer->csi2_err_cnt_even = 0;
4744		- hw_timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
	8249	+ timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
4745	8250	timer->csi2_err_triggered_cnt++;
4746	8251	if (timer->csi2_err_triggered_cnt == 1) {
4747	8252	is_first_err = true;
4748		- timer->csi2_first_err_timestamp = ktime_get_ns();
	8253	+ timer->csi2_first_err_timestamp = rkcif_time_get_ns(dev);
4749	8254	}
4750	8255
4751	8256	is_assign_triggered = true;
..	..	@@ -4757,10 +8262,10 @@
4757	8262
4758	8263	if (!is_first_err) {
4759	8264	if (timer->csi2_err_triggered_cnt >= 1) {
4760		- cur_time = ktime_get_ns();
	8265	+ cur_time = rkcif_time_get_ns(dev);
4761	8266	diff_time = cur_time - timer->csi2_first_err_timestamp;
4762	8267	diff_time = div_u64(diff_time, 1000000);
4763		- if (diff_time >= hw_timer->err_time_interval) {
	8268	+ if (diff_time >= timer->err_time_interval) {
4764	8269	is_triggered = true;
4765	8270	v4l2_info(&dev->v4l2_dev, "trigger reset for time out of csi err\n");
4766	8271	goto end_judge;
..	..	@@ -4780,19 +8285,10 @@
4780	8285	* when fs cnt is beyond 2, it indicates that frame end is not coming,
4781	8286	* or fs and fe had been not paired.
4782	8287	*/
4783		- if (hw_timer->monitor_mode != RKCIF_MONITOR_MODE_HOTPLUG &&
4784		- (stream->is_fs_fe_not_paired \|\|
4785		- stream->fs_cnt_in_single_frame > RKCIF_FS_DETECTED_NUM)) {
	8288	+ if (stream->is_fs_fe_not_paired \|\|
	8289	+ stream->fs_cnt_in_single_frame > RKCIF_FS_DETECTED_NUM) {
4786	8290	is_triggered = true;
4787	8291	v4l2_info(&dev->v4l2_dev, "reset for fs & fe not paired\n");
4788		- }
4789		- if (dev->irq_stats.csi_bwidth_lack_cnt) {
4790		- is_triggered = true;
4791		- dev->irq_stats.csi_bwidth_lack_cnt = 0;
4792		- }
4793		- if (dev->irq_stats.csi_overflow_cnt) {
4794		- is_triggered = true;
4795		- dev->irq_stats.csi_overflow_cnt = 0;
4796	8292	}
4797	8293	end_judge:
4798	8294	spin_unlock_irqrestore(&timer->csi2_err_lock, flags);
..	..	@@ -4800,7 +8296,30 @@
4800	8296	return is_triggered;
4801	8297	}
4802	8298
4803		-static s32 rkcif_get_sensor_vblank(struct rkcif_device *dev)
	8299	+static bool rkcif_is_triggered_monitoring(struct rkcif_device *dev)
	8300	+{
	8301	+ struct rkcif_timer *timer = &dev->reset_watchdog_timer;
	8302	+ struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
	8303	+ bool ret = false;
	8304	+
	8305	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
	8306	+ ret = false;
	8307	+
	8308	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE \|\|
	8309	+ timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
	8310	+ if (stream->frame_idx >= timer->triggered_frame_num)
	8311	+ ret = true;
	8312	+ }
	8313	+
	8314	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
	8315	+ timer->is_csi2_err_occurred = rkcif_is_csi2_err_trigger_reset(timer);
	8316	+ ret = timer->is_csi2_err_occurred;
	8317	+ }
	8318	+
	8319	+ return ret;
	8320	+}
	8321	+
	8322	+s32 rkcif_get_sensor_vblank(struct rkcif_device *dev)
4804	8323	{
4805	8324	struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
4806	8325	struct v4l2_subdev *sd = terminal_sensor->sd;
..	..	@@ -4817,7 +8336,7 @@
4817	8336	return 0;
4818	8337	}
4819	8338
4820		-static s32 rkcif_get_sensor_vblank_def(struct rkcif_device *dev)
	8339	+s32 rkcif_get_sensor_vblank_def(struct rkcif_device *dev)
4821	8340	{
4822	8341	struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
4823	8342	struct v4l2_subdev *sd = terminal_sensor->sd;
..	..	@@ -4843,7 +8362,7 @@
4843	8362	const struct cif_output_fmt *fmt;
4844	8363	u32 fourcc;
4845	8364
4846		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
	8365	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
4847	8366	if (!fmt) {
4848	8367	v4l2_err(&dev->v4l2_dev, "can not find output format: 0x%x",
4849	8368	stream->pixm.pixelformat);
..	..	@@ -4859,13 +8378,14 @@
4859	8378	* writing of ddr, aliged with 256
4860	8379	*/
4861	8380	if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
4862		- fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888) {
	8381	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	8382	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
4863	8383	crop_vwidth = ALIGN(raw_width fmt->raw_bpp / 8, 256);
4864	8384	} else {
4865	8385	crop_vwidth = ALIGN(raw_width fmt->bpp[0] / 8, 8);
4866	8386	}
4867	8387
4868		- if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
	8388	+ if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 \|\| channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
4869	8389	crop_width = raw_width fmt->bpp[0] / 8;
4870	8390	/*
4871	8391	* rk cif don't support output yuyv fmt data
..	..	@@ -4893,12 +8413,15 @@
4893	8413	return;
4894	8414
4895	8415	mbus = &cif_dev->active_sensor->mbus;
4896		- if (mbus->type == V4L2_MBUS_CSI2 \|\|
	8416	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	8417	+ mbus->type == V4L2_MBUS_CSI2_CPHY \|\|
4897	8418	mbus->type == V4L2_MBUS_CCP2) {
4898	8419	struct csi_channel_info *channel = &cif_dev->channels[stream->id];
4899	8420
4900	8421	if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
4901	8422	crop_x = 3 * stream->crop[CROP_SRC_ACT].left;
	8423	+ else if (channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
	8424	+ crop_x = 2 * stream->crop[CROP_SRC_ACT].left;
4902	8425	else
4903	8426	crop_x = stream->crop[CROP_SRC_ACT].left;
4904	8427
..	..	@@ -4940,15 +8463,8 @@
4940	8463	crop_y << CIF_CROP_Y_SHIFT \| crop_x);
4941	8464
4942	8465	if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_RAW) {
4943		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
4944		- if (fmt->fourcc == V4L2_PIX_FMT_GREY \|\|
4945		- fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
4946		- fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
4947		- fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
4948		- fmt->fourcc == V4L2_PIX_FMT_SBGGR8)
4949		- crop_vwidth = ALIGN(raw_width * fmt->raw_bpp / 8, 256);
4950		- else
4951		- crop_vwidth = raw_width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
	8466	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
	8467	+ crop_vwidth = raw_width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
4952	8468	}
4953	8469	rkcif_write_register(cif_dev, CIF_REG_DVP_VIR_LINE_WIDTH, crop_vwidth);
4954	8470
..	..	@@ -4959,41 +8475,94 @@
4959	8475	stream->crop_dyn_en = false;
4960	8476	}
4961	8477
4962		-void rkcif_monitor_reset_event(struct rkcif_hw *hw)
	8478	+static void rkcif_monitor_reset_event(struct rkcif_device *dev)
4963	8479	{
4964		- struct rkcif_hw_timer *hw_timer = &hw->hw_timer;
4965		- struct rkcif_timer *timer = NULL;
4966		- struct rkcif_device *cif_dev = NULL;
4967	8480	struct rkcif_stream *stream = NULL;
4968		- unsigned long flags;
4969		- int i = 0, j = 0;
	8481	+ struct rkcif_timer *timer = &dev->reset_watchdog_timer;
	8482	+ unsigned int cycle = 0;
	8483	+ u64 fps, timestamp0, timestamp1;
	8484	+ unsigned long flags, fps_flags;
	8485	+ int i = 0;
4970	8486
4971		- if (hw_timer->is_running)
	8487	+ if (timer->is_running)
4972	8488	return;
4973	8489
4974		- if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
	8490	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
4975	8491	return;
4976	8492
4977		- spin_lock_irqsave(&hw_timer->timer_lock, flags);
4978		- hw_timer->is_running = true;
4979		- for (j = 0; i < hw->dev_num; j++) {
4980		- cif_dev = hw->cif_dev[i];
4981		- timer = &cif_dev->reset_watchdog_timer;
4982		- for (i = 0; i < cif_dev->num_channels; i++) {
4983		- stream = &cif_dev->stream[i];
4984		- if (stream->state == RKCIF_STATE_STREAMING)
4985		- timer->last_buf_wakeup_cnt[i] = stream->frame_idx;
4986		- }
	8493	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	8494	+ stream = &dev->stream[i];
	8495	+ if (stream->state == RKCIF_STATE_STREAMING)
	8496	+ break;
4987	8497	}
4988		- hw_timer->cycle_jif = msecs_to_jiffies(hw_timer->monitor_cycle);
4989		- hw_timer->timer.expires = jiffies + hw_timer->cycle_jif;
4990		- mod_timer(&hw_timer->timer, hw_timer->timer.expires);
4991	8498
4992		- spin_unlock_irqrestore(&hw_timer->timer_lock, flags);
	8499	+ if (i >= RKCIF_MAX_STREAM_MIPI)
	8500	+ return;
4993	8501
4994		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
4995		- "start monitor timer, monitor cycle %d\n",
4996		- hw_timer->monitor_cycle);
	8502	+ timer->is_triggered = rkcif_is_triggered_monitoring(dev);
	8503	+
	8504	+ if (timer->is_triggered) {
	8505	+ struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
	8506	+ enum rkcif_monitor_mode mode;
	8507	+ s32 vblank = 0;
	8508	+ u32 vts = 0;
	8509	+ u64 numerator = 0;
	8510	+ u64 denominator = 0;
	8511	+
	8512	+ if (stream->frame_idx > 2) {
	8513	+ spin_lock_irqsave(&stream->fps_lock, fps_flags);
	8514	+ timestamp0 = stream->fps_stats.frm0_timestamp;
	8515	+ timestamp1 = stream->fps_stats.frm1_timestamp;
	8516	+ spin_unlock_irqrestore(&stream->fps_lock, fps_flags);
	8517	+
	8518	+ fps = timestamp0 > timestamp1 ?
	8519	+ timestamp0 - timestamp1 : timestamp1 - timestamp0;
	8520	+ fps = div_u64(fps, 1000);
	8521	+ } else {
	8522	+ numerator = dev->terminal_sensor.fi.interval.numerator;
	8523	+ denominator = dev->terminal_sensor.fi.interval.denominator;
	8524	+ fps = div_u64(1000000 * numerator, denominator);
	8525	+ }
	8526	+ spin_lock_irqsave(&timer->timer_lock, flags);
	8527	+
	8528	+ timer->frame_end_cycle_us = fps;
	8529	+
	8530	+ vblank = rkcif_get_sensor_vblank(dev);
	8531	+ timer->raw_height = raw_rect->height;
	8532	+ vts = timer->raw_height + vblank;
	8533	+ timer->vts = vts;
	8534	+
	8535	+ timer->line_end_cycle = div_u64(timer->frame_end_cycle_us, timer->vts);
	8536	+ fps = div_u64(timer->frame_end_cycle_us, 1000);
	8537	+ cycle = fps * timer->frm_num_of_monitor_cycle;
	8538	+ timer->cycle = msecs_to_jiffies(cycle);
	8539	+
	8540	+ timer->run_cnt = 0;
	8541	+ timer->is_running = true;
	8542	+ timer->is_buf_stop_update = false;
	8543	+ for (i = 0; i < dev->num_channels; i++) {
	8544	+ stream = &dev->stream[i];
	8545	+ if (stream->state == RKCIF_STATE_STREAMING)
	8546	+ timer->last_buf_wakeup_cnt[i] = stream->buf_wake_up_cnt;
	8547	+ }
	8548	+ /* in trigger mode, monitoring count is fps */
	8549	+ mode = timer->monitor_mode;
	8550	+ if (mode == RKCIF_MONITOR_MODE_CONTINUE \|\|
	8551	+ mode == RKCIF_MONITOR_MODE_HOTPLUG)
	8552	+ timer->max_run_cnt = 0xffffffff - CIF_TIMEOUT_FRAME_NUM;
	8553	+ else
	8554	+ timer->max_run_cnt = div_u64(1000, fps) * 1;
	8555	+
	8556	+ timer->timer.expires = jiffies + timer->cycle;
	8557	+ mod_timer(&timer->timer, timer->timer.expires);
	8558	+
	8559	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
	8560	+
	8561	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	8562	+ "%s:mode:%d, raw height:%d,vblank:%d, cycle:%ld, fps:%llu\n",
	8563	+ __func__, timer->monitor_mode, raw_rect->height,
	8564	+ vblank, timer->cycle, div_u64(1000, fps));
	8565	+ }
4997	8566	}
4998	8567
4999	8568	static void rkcif_rdbk_frame_end(struct rkcif_stream *stream)
..	..	@@ -5003,13 +8572,15 @@
5003	8572	u32 denominator, numerator;
5004	8573	u64 l_ts, m_ts, s_ts, time = 30000000LL;
5005	8574	int ret, fps = -1;
	8575	+ int i = 0;
	8576	+ unsigned long flags;
5006	8577
5007		- if (dev->hdr.mode == HDR_X2) {
	8578	+ if (dev->hdr.hdr_mode == HDR_X2) {
5008	8579	if (stream->id != RKCIF_STREAM_MIPI_ID1 \|\|
5009	8580	dev->stream[RKCIF_STREAM_MIPI_ID0].state != RKCIF_STATE_STREAMING \|\|
5010	8581	dev->stream[RKCIF_STREAM_MIPI_ID1].state != RKCIF_STATE_STREAMING)
5011	8582	return;
5012		- } else if (dev->hdr.mode == HDR_X3) {
	8583	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
5013	8584	if (stream->id != RKCIF_STREAM_MIPI_ID2 \|\|
5014	8585	dev->stream[RKCIF_STREAM_MIPI_ID0].state != RKCIF_STATE_STREAMING \|\|
5015	8586	dev->stream[RKCIF_STREAM_MIPI_ID1].state != RKCIF_STATE_STREAMING \|\|
..	..	@@ -5022,19 +8593,19 @@
5022	8593	if (denominator && numerator)
5023	8594	time = numerator * 1000 / denominator * 1000 * 1000;
5024	8595
5025		- if (dev->hdr.mode == HDR_X3) {
	8596	+ if (dev->hdr.hdr_mode == HDR_X3) {
5026	8597	if (dev->rdbk_buf[RDBK_L] &&
5027	8598	dev->rdbk_buf[RDBK_M] &&
5028	8599	dev->rdbk_buf[RDBK_S]) {
5029		- l_ts = dev->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
5030		- m_ts = dev->rdbk_buf[RDBK_M]->vb.vb2_buf.timestamp;
5031		- s_ts = dev->rdbk_buf[RDBK_S]->vb.vb2_buf.timestamp;
	8600	+ l_ts = dev->rdbk_buf[RDBK_L]->fe_timestamp;
	8601	+ m_ts = dev->rdbk_buf[RDBK_M]->fe_timestamp;
	8602	+ s_ts = dev->rdbk_buf[RDBK_S]->fe_timestamp;
5032	8603
5033	8604	if (m_ts < l_ts \|\| s_ts < m_ts) {
5034	8605	v4l2_err(&dev->v4l2_dev,
5035	8606	"s/m/l frame err, timestamp s:%lld m:%lld l:%lld\n",
5036	8607	s_ts, m_ts, l_ts);
5037		- goto RDBK_FRM_UNMATCH;
	8608	+ return;
5038	8609	}
5039	8610
5040	8611	if ((m_ts - l_ts) > time \|\| (s_ts - m_ts) > time) {
..	..	@@ -5055,17 +8626,28 @@
5055	8626	v4l2_err(&dev->v4l2_dev,
5056	8627	"timestamp no match, s:%lld m:%lld l:%lld, fps:%d\n",
5057	8628	s_ts, m_ts, l_ts, fps);
5058		- goto RDBK_FRM_UNMATCH;
	8629	+ return;
5059	8630	}
5060	8631	}
5061		- dev->rdbk_buf[RDBK_L]->vb.sequence = dev->rdbk_buf[RDBK_S]->vb.sequence;
5062		- dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_S]->vb.sequence;
5063		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID0],
5064		- &dev->rdbk_buf[RDBK_L]->vb);
5065		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID1],
5066		- &dev->rdbk_buf[RDBK_M]->vb);
5067		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID2],
5068		- &dev->rdbk_buf[RDBK_S]->vb);
	8632	+ dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
	8633	+ dev->rdbk_buf[RDBK_S]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
	8634	+ if (dev->is_support_tools &&
	8635	+ dev->stream[RKCIF_STREAM_MIPI_ID0].tools_vdev->state == RKCIF_STATE_STREAMING &&
	8636	+ dev->stream[RKCIF_STREAM_MIPI_ID1].tools_vdev->state == RKCIF_STATE_STREAMING &&
	8637	+ dev->stream[RKCIF_STREAM_MIPI_ID2].tools_vdev->state == RKCIF_STATE_STREAMING) {
	8638	+ for (i = 0; i < 3; i++) {
	8639	+ spin_lock_irqsave(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8640	+ list_add_tail(&dev->rdbk_buf[i]->queue,
	8641	+ &dev->stream[i].tools_vdev->buf_done_head);
	8642	+ if (!work_busy(&dev->stream[i].tools_vdev->work))
	8643	+ schedule_work(&dev->stream[i].tools_vdev->work);
	8644	+ spin_unlock_irqrestore(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8645	+ }
	8646	+ } else {
	8647	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID0], dev->rdbk_buf[RDBK_L]);
	8648	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID1], dev->rdbk_buf[RDBK_M]);
	8649	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID2], dev->rdbk_buf[RDBK_S]);
	8650	+ }
5069	8651	} else {
5070	8652	if (!dev->rdbk_buf[RDBK_L])
5071	8653	v4l2_err(&dev->v4l2_dev, "lost long frames\n");
..	..	@@ -5073,18 +8655,18 @@
5073	8655	v4l2_err(&dev->v4l2_dev, "lost medium frames\n");
5074	8656	if (!dev->rdbk_buf[RDBK_S])
5075	8657	v4l2_err(&dev->v4l2_dev, "lost short frames\n");
5076		- goto RDBK_FRM_UNMATCH;
	8658	+ return;
5077	8659	}
5078		- } else if (dev->hdr.mode == HDR_X2) {
	8660	+ } else if (dev->hdr.hdr_mode == HDR_X2) {
5079	8661	if (dev->rdbk_buf[RDBK_L] && dev->rdbk_buf[RDBK_M]) {
5080		- l_ts = dev->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
5081		- s_ts = dev->rdbk_buf[RDBK_M]->vb.vb2_buf.timestamp;
	8662	+ l_ts = dev->rdbk_buf[RDBK_L]->fe_timestamp;
	8663	+ s_ts = dev->rdbk_buf[RDBK_M]->fe_timestamp;
5082	8664
5083	8665	if (s_ts < l_ts) {
5084	8666	v4l2_err(&dev->v4l2_dev,
5085	8667	"s/l frame err, timestamp s:%lld l:%lld\n",
5086	8668	s_ts, l_ts);
5087		- goto RDBK_FRM_UNMATCH;
	8669	+ return;
5088	8670	}
5089	8671
5090	8672	if ((s_ts - l_ts) > time) {
..	..	@@ -5104,42 +8686,32 @@
5104	8686	v4l2_err(&dev->v4l2_dev,
5105	8687	"timestamp no match, s:%lld l:%lld, fps:%d\n",
5106	8688	s_ts, l_ts, fps);
5107		- goto RDBK_FRM_UNMATCH;
	8689	+ return;
5108	8690	}
5109	8691	}
5110		- dev->rdbk_buf[RDBK_L]->vb.sequence = dev->rdbk_buf[RDBK_M]->vb.sequence;
5111		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID0],
5112		- &dev->rdbk_buf[RDBK_L]->vb);
5113		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID1],
5114		- &dev->rdbk_buf[RDBK_M]->vb);
	8692	+ dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
	8693	+ if (dev->is_support_tools &&
	8694	+ dev->stream[RKCIF_STREAM_MIPI_ID0].tools_vdev->state == RKCIF_STATE_STREAMING &&
	8695	+ dev->stream[RKCIF_STREAM_MIPI_ID1].tools_vdev->state == RKCIF_STATE_STREAMING) {
	8696	+ for (i = 0; i < 2; i++) {
	8697	+ spin_lock_irqsave(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8698	+ list_add_tail(&dev->rdbk_buf[i]->queue,
	8699	+ &dev->stream[i].tools_vdev->buf_done_head);
	8700	+ if (!work_busy(&dev->stream[i].tools_vdev->work))
	8701	+ schedule_work(&dev->stream[i].tools_vdev->work);
	8702	+ spin_unlock_irqrestore(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8703	+ }
	8704	+ } else {
	8705	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID0], dev->rdbk_buf[RDBK_L]);
	8706	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID1], dev->rdbk_buf[RDBK_M]);
	8707	+ }
5115	8708	} else {
5116	8709	if (!dev->rdbk_buf[RDBK_L])
5117	8710	v4l2_err(&dev->v4l2_dev, "lost long frames\n");
5118	8711	if (!dev->rdbk_buf[RDBK_M])
5119	8712	v4l2_err(&dev->v4l2_dev, "lost short frames\n");
5120		- goto RDBK_FRM_UNMATCH;
	8713	+ return;
5121	8714	}
5122		- } else {
5123		- rkcif_vb_done_oneframe(stream, &dev->rdbk_buf[RDBK_S]->vb);
5124		- }
5125		-
5126		- dev->rdbk_buf[RDBK_L] = NULL;
5127		- dev->rdbk_buf[RDBK_M] = NULL;
5128		- dev->rdbk_buf[RDBK_S] = NULL;
5129		- return;
5130		-
5131		-RDBK_FRM_UNMATCH:
5132		- if (dev->rdbk_buf[RDBK_L]) {
5133		- dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5134		- rkcif_buf_queue(&dev->rdbk_buf[RDBK_L]->vb.vb2_buf);
5135		- }
5136		- if (dev->rdbk_buf[RDBK_M]) {
5137		- dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5138		- rkcif_buf_queue(&dev->rdbk_buf[RDBK_M]->vb.vb2_buf);
5139		- }
5140		- if (dev->rdbk_buf[RDBK_S]) {
5141		- dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5142		- rkcif_buf_queue(&dev->rdbk_buf[RDBK_S]->vb.vb2_buf);
5143	8715	}
5144	8716
5145	8717	dev->rdbk_buf[RDBK_L] = NULL;
..	..	@@ -5147,10 +8719,26 @@
5147	8719	dev->rdbk_buf[RDBK_S] = NULL;
5148	8720	}
5149	8721
	8722	+static void rkcif_buf_done_with_tools(struct rkcif_stream *stream,
	8723	+ struct rkcif_buffer *active_buf)
	8724	+{
	8725	+ unsigned long flags;
	8726	+
	8727	+ spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
	8728	+ if (stream->tools_vdev->state == RKCIF_STATE_STREAMING) {
	8729	+ list_add_tail(&active_buf->queue, &stream->tools_vdev->buf_done_head);
	8730	+ if (!work_busy(&stream->tools_vdev->work))
	8731	+ schedule_work(&stream->tools_vdev->work);
	8732	+ } else {
	8733	+ rkcif_vb_done_tasklet(stream, active_buf);
	8734	+ }
	8735	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	8736	+}
	8737	+
5150	8738	static void rkcif_buf_done_prepare(struct rkcif_stream *stream,
5151		- struct rkcif_buffer *active_buf,
5152		- int mipi_id,
5153		- u32 mode)
	8739	+ struct rkcif_buffer *active_buf,
	8740	+ int mipi_id,
	8741	+ u32 mode)
5154	8742	{
5155	8743	unsigned long flags;
5156	8744	struct vb2_v4l2_buffer *vb_done = NULL;
..	..	@@ -5158,8 +8746,13 @@
5158	8746
5159	8747	if (active_buf) {
5160	8748	vb_done = &active_buf->vb;
5161		- vb_done->vb2_buf.timestamp = ktime_get_ns();
5162		- vb_done->sequence = stream->frame_idx;
	8749	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	8750	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656)
	8751	+ vb_done->vb2_buf.timestamp = stream->readout.fe_timestamp;
	8752	+ else
	8753	+ vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
	8754	+ vb_done->sequence = stream->frame_idx - 1;
	8755	+ active_buf->fe_timestamp = rkcif_time_get_ns(cif_dev);
5163	8756	if (stream->is_line_wake_up) {
5164	8757	spin_lock_irqsave(&stream->fps_lock, flags);
5165	8758	if (mode)
..	..	@@ -5171,58 +8764,83 @@
5171	8764	}
5172	8765	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED)
5173	8766	vb_done->sequence /= 2;
	8767	+ if (stream->cur_skip_frame) {
	8768	+ rkcif_buf_queue(&active_buf->vb.vb2_buf);
	8769	+ return;
	8770	+ }
	8771	+ } else if (cif_dev->rdbk_buf[stream->id]) {
	8772	+ vb_done = &cif_dev->rdbk_buf[stream->id]->vb;
	8773	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	8774	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656)
	8775	+ vb_done->vb2_buf.timestamp = stream->readout.fe_timestamp;
	8776	+ else
	8777	+ vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
	8778	+ vb_done->sequence = stream->frame_idx - 1;
	8779	+ cif_dev->rdbk_buf[stream->id]->fe_timestamp = rkcif_time_get_ns(cif_dev);
5174	8780	}
5175	8781
5176		- if (cif_dev->hdr.mode == NO_HDR) {
	8782	+ if (cif_dev->hdr.hdr_mode == NO_HDR \|\| cif_dev->hdr.hdr_mode == HDR_COMPR) {
5177	8783	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
5178		- if (stream->frame_phase == CIF_CSI_FRAME1_READY && active_buf)
5179		- rkcif_vb_done_oneframe(stream, vb_done);
	8784	+ if (stream->frame_phase == CIF_CSI_FRAME1_READY && active_buf) {
	8785	+
	8786	+ if (cif_dev->is_support_tools && stream->tools_vdev)
	8787	+ rkcif_buf_done_with_tools(stream, active_buf);
	8788	+ else
	8789	+ rkcif_vb_done_tasklet(stream, active_buf);
	8790	+ }
5180	8791	} else {
5181		- if (active_buf)
5182		- rkcif_vb_done_oneframe(stream, vb_done);
	8792	+ if (active_buf) {
	8793	+ if (cif_dev->is_support_tools && stream->tools_vdev)
	8794	+ rkcif_buf_done_with_tools(stream, active_buf);
	8795	+ else
	8796	+ rkcif_vb_done_tasklet(stream, active_buf);
	8797	+ }
5183	8798	}
5184	8799	} else {
5185	8800	if (cif_dev->is_start_hdr) {
5186	8801	spin_lock_irqsave(&cif_dev->hdr_lock, flags);
5187	8802	if (mipi_id == RKCIF_STREAM_MIPI_ID0) {
5188		- if (cif_dev->rdbk_buf[RDBK_L]) {
	8803	+ if (cif_dev->rdbk_buf[RDBK_L] && active_buf) {
5189	8804	v4l2_err(&cif_dev->v4l2_dev,
5190	8805	"multiple long data in %s frame,frm_idx:%d,state:0x%x\n",
5191		- cif_dev->hdr.mode == HDR_X2 ? "hdr_x2" : "hdr_x3",
	8806	+ cif_dev->hdr.hdr_mode == HDR_X2 ? "hdr_x2" : "hdr_x3",
5192	8807	stream->frame_idx,
5193	8808	cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state);
5194	8809	cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5195	8810	rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf);
	8811	+ cif_dev->rdbk_buf[RDBK_L] = NULL;
5196	8812	}
5197	8813	if (active_buf)
5198	8814	cif_dev->rdbk_buf[RDBK_L] = active_buf;
5199	8815	} else if (mipi_id == RKCIF_STREAM_MIPI_ID1) {
5200		- if (cif_dev->rdbk_buf[RDBK_M]) {
	8816	+ if (cif_dev->rdbk_buf[RDBK_M] && active_buf) {
5201	8817	v4l2_err(&cif_dev->v4l2_dev,
5202	8818	"multiple %s frame,frm_idx:%d,state:0x%x\n",
5203		- cif_dev->hdr.mode == HDR_X2 ? "short data in hdr_x2" : "medium data in hdr_x3",
	8819	+ cif_dev->hdr.hdr_mode == HDR_X2 ? "short data in hdr_x2" : "medium data in hdr_x3",
5204	8820	stream->frame_idx,
5205	8821	cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state);
5206	8822	cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5207	8823	rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf);
	8824	+ cif_dev->rdbk_buf[RDBK_M] = NULL;
5208	8825	}
5209	8826	if (active_buf)
5210	8827	cif_dev->rdbk_buf[RDBK_M] = active_buf;
5211		- if (cif_dev->hdr.mode == HDR_X2)
	8828	+ if (cif_dev->hdr.hdr_mode == HDR_X2)
5212	8829	rkcif_rdbk_frame_end(stream);
5213	8830	} else if (mipi_id == RKCIF_STREAM_MIPI_ID2) {
5214		- if (cif_dev->rdbk_buf[RDBK_S]) {
	8831	+ if (cif_dev->rdbk_buf[RDBK_S] && active_buf) {
5215	8832	v4l2_err(&cif_dev->v4l2_dev,
5216	8833	"multiple %s frame, frm_idx:%d,state:0x%x\n",
5217		- cif_dev->hdr.mode == HDR_X2 ? "err short data in hdr_x3" : "short data in hdr_x3",
	8834	+ cif_dev->hdr.hdr_mode == HDR_X2 ? "err short data in hdr_x3" : "short data in hdr_x3",
5218	8835	stream->frame_idx,
5219	8836	cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state);
5220	8837	cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5221	8838	rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf);
	8839	+ cif_dev->rdbk_buf[RDBK_S] = NULL;
5222	8840	}
5223	8841	if (active_buf)
5224	8842	cif_dev->rdbk_buf[RDBK_S] = active_buf;
5225		- if (cif_dev->hdr.mode == HDR_X3)
	8843	+ if (cif_dev->hdr.hdr_mode == HDR_X3)
5226	8844	rkcif_rdbk_frame_end(stream);
5227	8845	}
5228	8846	spin_unlock_irqrestore(&cif_dev->hdr_lock, flags);
..	..	@@ -5265,12 +8883,129 @@
5265	8883	}
5266	8884	ret = rkcif_get_new_buffer_wake_up_mode(stream);
5267	8885	if (ret)
5268		- goto end_wake_up;
5269		-
	8886	+ return;
5270	8887	rkcif_buf_done_prepare(stream, active_buf, mipi_id, mode);
5271		-end_wake_up:
5272		- stream->frame_idx++;
	8888	+}
5273	8889
	8890	+static void rkcif_store_last_buf_for_online(struct rkcif_stream *stream,
	8891	+ struct rkcif_rx_buffer *buf)
	8892	+{
	8893	+ struct rkcif_device *dev = stream->cifdev;
	8894	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	8895	+ u32 frm0_addr_y, frm1_addr_y;
	8896	+
	8897	+ INIT_LIST_HEAD(&stream->rx_buf_head);
	8898	+ stream->curr_buf_toisp = buf;
	8899	+ stream->next_buf_toisp = buf;
	8900	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	8901	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	8902	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	8903	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(stream->id);
	8904	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(stream->id);
	8905	+ } else {
	8906	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(stream->id);
	8907	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(stream->id);
	8908	+ }
	8909	+ rkcif_write_register(dev, frm0_addr_y,
	8910	+ buf->dummy.dma_addr);
	8911	+ rkcif_write_register(dev, frm1_addr_y,
	8912	+ buf->dummy.dma_addr);
	8913	+}
	8914	+
	8915	+static void rkcif_release_unnecessary_buf_for_online(struct rkcif_stream *stream,
	8916	+ struct rkcif_rx_buffer *buf)
	8917	+{
	8918	+ struct rkcif_device *dev = stream->cifdev;
	8919	+ struct sditf_priv *priv = dev->sditf[0];
	8920	+ struct rkcif_rx_buffer *rx_buf = NULL;
	8921	+ unsigned long flags;
	8922	+ int i = 0;
	8923	+
	8924	+ spin_lock_irqsave(&priv->cif_dev->buffree_lock, flags);
	8925	+ for (i = 0; i < priv->buf_num; i++) {
	8926	+ rx_buf = &stream->rx_buf[i];
	8927	+ if (rx_buf && (!rx_buf->dummy.is_free) && rx_buf != buf) {
	8928	+ list_add_tail(&rx_buf->list_free, &priv->buf_free_list);
	8929	+ stream->total_buf_num--;
	8930	+ }
	8931	+ }
	8932	+ spin_unlock_irqrestore(&priv->cif_dev->buffree_lock, flags);
	8933	+ schedule_work(&priv->buffree_work.work);
	8934	+}
	8935	+
	8936	+static void rkcif_line_wake_up_rdbk(struct rkcif_stream *stream, int mipi_id)
	8937	+{
	8938	+ u32 mode;
	8939	+ struct rkcif_rx_buffer *active_buf = NULL;
	8940	+ struct sditf_priv *priv = NULL;
	8941	+ unsigned long flags;
	8942	+ int ret = 0;
	8943	+
	8944	+ mode = stream->line_int_cnt % 2;
	8945	+ if (mode) {
	8946	+ if (stream->curr_buf_toisp)
	8947	+ active_buf = stream->curr_buf_toisp;
	8948	+ stream->frame_phase = CIF_CSI_FRAME0_READY;
	8949	+ } else {
	8950	+ if (stream->next_buf_toisp)
	8951	+ active_buf = stream->next_buf_toisp;
	8952	+ stream->frame_phase = CIF_CSI_FRAME1_READY;
	8953	+ }
	8954	+
	8955	+ if (!active_buf) {
	8956	+ v4l2_err(&stream->cifdev->v4l2_dev,
	8957	+ "err buffer state in %s\n",
	8958	+ __func__);
	8959	+ return;
	8960	+ }
	8961	+
	8962	+ if (stream->stopping) {
	8963	+ stream->is_can_stop = true;
	8964	+ return;
	8965	+ }
	8966	+ ret = rkcif_get_new_buffer_wake_up_mode_rdbk(stream);
	8967	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	8968	+ "%d frame_idx %d, last_rx_buf_idx %d cur dma buf %x\n",
	8969	+ __LINE__, stream->frame_idx, stream->last_rx_buf_idx,
	8970	+ (u32)active_buf->dummy.dma_addr);
	8971	+ if (!ret) {
	8972	+ priv = stream->cifdev->sditf[0];
	8973	+ if (stream->cur_stream_mode & RKCIF_STREAM_MODE_TOISP_RDBK) {
	8974	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	8975	+ if (stream->cifdev->is_thunderboot &&
	8976	+ (stream->frame_idx - 1) == stream->last_rx_buf_idx &&
	8977	+ stream->cifdev->is_rdbk_to_online) {
	8978	+ stream->cur_stream_mode &= ~RKCIF_STREAM_MODE_TOISP_RDBK;
	8979	+ stream->cur_stream_mode \|= RKCIF_STREAM_MODE_TOISP;
	8980	+ stream->cifdev->wait_line = 0;
	8981	+ stream->is_line_wake_up = false;
	8982	+ if (stream->cifdev->hdr.hdr_mode == NO_HDR \|\|
	8983	+ (priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	8984	+ (priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id == 2)) {
	8985	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	8986	+ rkcif_stop_dma_capture(stream);
	8987	+ }
	8988	+ active_buf->dbufs.is_switch = true;
	8989	+ if ((priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id != 1) \|\|
	8990	+ (priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id != 2)) {
	8991	+ rkcif_store_last_buf_for_online(stream, active_buf);
	8992	+ stream->is_change_toisp = true;
	8993	+ }
	8994	+ }
	8995	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	8996	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	8997	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	8998	+ active_buf->fe_timestamp = rkcif_time_get_ns(stream->cifdev);
	8999	+ stream->last_frame_idx = stream->frame_idx;
	9000	+ if (stream->cifdev->hdr.hdr_mode == NO_HDR) {
	9001	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	9002	+ if (stream->cifdev->is_support_tools && stream->tools_vdev)
	9003	+ rkcif_rdbk_with_tools(stream, active_buf);
	9004	+ } else {
	9005	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	9006	+ }
	9007	+ }
	9008	+ }
5274	9009	}
5275	9010
5276	9011	static void rkcif_deal_readout_time(struct rkcif_stream *stream)
..	..	@@ -5280,18 +9015,25 @@
5280	9015	unsigned long flags;
5281	9016
5282	9017	spin_lock_irqsave(&stream->fps_lock, flags);
5283		- stream->readout.fe_timestamp = ktime_get_ns();
	9018	+ stream->readout.fe_timestamp = rkcif_time_get_ns(cif_dev);
	9019	+
	9020	+ if (cif_dev->inf_id == RKCIF_DVP) {
	9021	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	9022	+ return;
	9023	+ }
	9024	+
5284	9025	if (stream->id == RKCIF_STREAM_MIPI_ID0)
5285	9026	detect_stream->readout.readout_time = stream->readout.fe_timestamp - stream->readout.fs_timestamp;
5286	9027
5287		- if ((cif_dev->hdr.mode == NO_HDR) && (stream->id == RKCIF_STREAM_MIPI_ID0)) {
	9028	+ if ((cif_dev->hdr.hdr_mode == NO_HDR \|\| cif_dev->hdr.hdr_mode == HDR_COMPR) &&
	9029	+ (stream->id == RKCIF_STREAM_MIPI_ID0)) {
5288	9030	detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
5289	9031
5290		- } else if ((cif_dev->hdr.mode == HDR_X2) && (stream->id == RKCIF_STREAM_MIPI_ID1)) {
	9032	+ } else if ((cif_dev->hdr.hdr_mode == HDR_X2) && (stream->id == RKCIF_STREAM_MIPI_ID1)) {
5291	9033	detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
5292	9034	detect_stream->readout.total_time = stream->readout.fe_timestamp - detect_stream->readout.fe_timestamp;
5293	9035	detect_stream->readout.total_time += detect_stream->readout.readout_time;
5294		- } else if ((cif_dev->hdr.mode == HDR_X3) && (stream->id == RKCIF_STREAM_MIPI_ID2)) {
	9036	+ } else if ((cif_dev->hdr.hdr_mode == HDR_X3) && (stream->id == RKCIF_STREAM_MIPI_ID2)) {
5295	9037	detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
5296	9038	detect_stream->readout.total_time = stream->readout.fe_timestamp - detect_stream->readout.fe_timestamp;
5297	9039	detect_stream->readout.total_time += detect_stream->readout.readout_time;
..	..	@@ -5310,11 +9052,8 @@
5310	9052	int ret = 0;
5311	9053
5312	9054	if (stream->frame_phase == (CIF_CSI_FRAME0_READY \| CIF_CSI_FRAME1_READY)) {
5313		-
5314		- v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
5315		- stream->id, stream->frame_idx);
5316		-
5317		- stream->frame_idx++;
	9055	+ cif_dev->err_state \|= (RKCIF_ERR_ID0_TRIG_SIMULT << stream->id);
	9056	+ cif_dev->irq_stats.trig_simult_cnt[stream->id]++;
5318	9057	return;
5319	9058	}
5320	9059	if (!stream->is_line_wake_up) {
..	..	@@ -5323,11 +9062,93 @@
5323	9062	if (stream->frame_phase & CIF_CSI_FRAME0_READY) {
5324	9063	if (stream->curr_buf)
5325	9064	active_buf = stream->curr_buf;
5326		- stream->fps_stats.frm0_timestamp = ktime_get_ns();
	9065	+ stream->fps_stats.frm0_timestamp = rkcif_time_get_ns(cif_dev);
5327	9066	} else if (stream->frame_phase & CIF_CSI_FRAME1_READY) {
5328	9067	if (stream->next_buf)
5329	9068	active_buf = stream->next_buf;
5330		- stream->fps_stats.frm1_timestamp = ktime_get_ns();
	9069	+ stream->fps_stats.frm1_timestamp = rkcif_time_get_ns(cif_dev);
	9070	+ }
	9071	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	9072	+ }
	9073	+
	9074	+ rkcif_deal_readout_time(stream);
	9075	+
	9076	+ if (!stream->is_line_wake_up) {
	9077	+ ret = rkcif_assign_new_buffer_pingpong(stream,
	9078	+ RKCIF_YUV_ADDR_STATE_UPDATE,
	9079	+ mipi_id);
	9080	+ if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
	9081	+ return;
	9082	+ } else {
	9083	+ ret = rkcif_update_new_buffer_wake_up_mode(stream);
	9084	+ if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
	9085	+ return;
	9086	+ }
	9087	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	9088	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656 &&
	9089	+ stream->id != 0)
	9090	+ stream->frame_idx++;
	9091	+ if (!stream->is_line_wake_up)
	9092	+ rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0);
	9093	+
	9094	+ if (cif_dev->chip_id == CHIP_RV1126_CIF \|\|
	9095	+ cif_dev->chip_id == CHIP_RV1126_CIF_LITE \|\|
	9096	+ cif_dev->chip_id == CHIP_RK3568_CIF)
	9097	+ rkcif_luma_isr(&cif_dev->luma_vdev, mipi_id, cif_dev->stream[0].frame_idx - 1);
	9098	+}
	9099	+
	9100	+static void rkcif_update_stream_toisp(struct rkcif_device *cif_dev,
	9101	+ struct rkcif_stream *stream,
	9102	+ int mipi_id)
	9103	+{
	9104	+ if (stream->frame_phase == (CIF_CSI_FRAME0_READY \| CIF_CSI_FRAME1_READY)) {
	9105	+
	9106	+ v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
	9107	+ stream->id, stream->frame_idx);
	9108	+ return;
	9109	+ }
	9110	+
	9111	+ spin_lock(&stream->fps_lock);
	9112	+ if (stream->frame_phase & CIF_CSI_FRAME0_READY)
	9113	+ stream->fps_stats.frm0_timestamp = rkcif_time_get_ns(cif_dev);
	9114	+ else if (stream->frame_phase & CIF_CSI_FRAME1_READY)
	9115	+ stream->fps_stats.frm1_timestamp = rkcif_time_get_ns(cif_dev);
	9116	+ spin_unlock(&stream->fps_lock);
	9117	+
	9118	+ if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
	9119	+ rkcif_deal_readout_time(stream);
	9120	+
	9121	+ if (!stream->is_line_wake_up)
	9122	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	9123	+ RKCIF_YUV_ADDR_STATE_UPDATE,
	9124	+ mipi_id);
	9125	+}
	9126	+
	9127	+static void rkcif_update_stream_rockit(struct rkcif_device *cif_dev,
	9128	+ struct rkcif_stream *stream,
	9129	+ int mipi_id)
	9130	+{
	9131	+ struct rkcif_buffer *active_buf = NULL;
	9132	+ unsigned long flags;
	9133	+ int ret = 0;
	9134	+
	9135	+ if (stream->frame_phase == (CIF_CSI_FRAME0_READY \| CIF_CSI_FRAME1_READY)) {
	9136	+
	9137	+ v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
	9138	+ stream->id, stream->frame_idx);
	9139	+ return;
	9140	+ }
	9141	+ if (!stream->is_line_wake_up) {
	9142	+
	9143	+ spin_lock_irqsave(&stream->fps_lock, flags);
	9144	+ if (stream->frame_phase & CIF_CSI_FRAME0_READY) {
	9145	+ if (stream->curr_buf_rockit)
	9146	+ active_buf = stream->curr_buf_rockit;
	9147	+ stream->fps_stats.frm0_timestamp = rkcif_time_get_ns(cif_dev);
	9148	+ } else if (stream->frame_phase & CIF_CSI_FRAME1_READY) {
	9149	+ if (stream->next_buf_rockit)
	9150	+ active_buf = stream->next_buf_rockit;
	9151	+ stream->fps_stats.frm1_timestamp = rkcif_time_get_ns(cif_dev);
5331	9152	}
5332	9153	spin_unlock_irqrestore(&stream->fps_lock, flags);
5333	9154	}
..	..	@@ -5335,96 +9156,105 @@
5335	9156	if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
5336	9157	rkcif_deal_readout_time(stream);
5337	9158
5338		- if (cif_dev->chip_id == CHIP_RV1126_CIF \|\|
5339		- cif_dev->chip_id == CHIP_RV1126_CIF_LITE \|\|
5340		- cif_dev->chip_id == CHIP_RK3568_CIF)
5341		- rkcif_luma_isr(&cif_dev->luma_vdev, mipi_id, stream->frame_idx);
	9159	+ ret = rkcif_assign_new_buffer_pingpong_rockit(stream,
	9160	+ RKCIF_YUV_ADDR_STATE_UPDATE,
	9161	+ mipi_id);
	9162	+ if (ret)
	9163	+ return;
5342	9164
5343		- if (!stream->is_line_wake_up) {
5344		- ret = rkcif_assign_new_buffer_pingpong(stream,
5345		- RKCIF_YUV_ADDR_STATE_UPDATE,
5346		- mipi_id);
5347		- if (ret)
5348		- goto end;
5349		- } else {
5350		- ret = rkcif_update_new_buffer_wake_up_mode(stream);
5351		- if (ret)
5352		- return;
	9165	+ if (active_buf) {
	9166	+ active_buf->vb.vb2_buf.timestamp = stream->readout.fs_timestamp;
	9167	+ active_buf->vb.sequence = stream->frame_idx - 1;
	9168	+ rkcif_rockit_buf_done(stream, active_buf);
5353	9169	}
5354		- if (!stream->is_line_wake_up)
5355		- rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0);
5356		-
5357		-end:
5358		- if (!stream->is_line_wake_up)
5359		- stream->frame_idx++;
5360	9170	}
5361	9171
5362		-u32 rkcif_get_sof(struct rkcif_device *cif_dev)
	9172	+static u32 rkcif_get_sof(struct rkcif_device *cif_dev)
5363	9173	{
5364	9174	u32 val = 0x0;
5365	9175	struct rkcif_sensor_info *sensor = cif_dev->active_sensor;
	9176	+ struct csi2_dev *csi;
5366	9177
5367		- if (sensor->mbus.type == V4L2_MBUS_CSI2)
5368		- val = rkcif_csi2_get_sof();
5369		- else if (sensor->mbus.type == V4L2_MBUS_CCP2)
	9178	+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	9179	+ sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
	9180	+ csi = container_of(sensor->sd, struct csi2_dev, sd);
	9181	+ val = rkcif_csi2_get_sof(csi);
	9182	+ } else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
5370	9183	val = rkcif_lvds_get_sof(cif_dev);
5371		- else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
5372		- sensor->mbus.type == V4L2_MBUS_BT656)
	9184	+ } else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
	9185	+ sensor->mbus.type == V4L2_MBUS_BT656) {
5373	9186	val = rkcif_dvp_get_sof(cif_dev);
5374		-
	9187	+ }
5375	9188	return val;
5376	9189	}
5377	9190
5378	9191	static void rkcif_set_sof(struct rkcif_device *cif_dev, u32 seq)
5379	9192	{
5380	9193	struct rkcif_sensor_info *sensor = cif_dev->active_sensor;
	9194	+ struct csi2_dev *csi;
5381	9195
5382		- if (sensor->mbus.type == V4L2_MBUS_CSI2)
5383		- rkcif_csi2_set_sof(seq);
5384		- else if (sensor->mbus.type == V4L2_MBUS_CCP2)
	9196	+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	9197	+ sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
	9198	+ csi = container_of(sensor->sd, struct csi2_dev, sd);
	9199	+ rkcif_csi2_set_sof(csi, seq);
	9200	+ } else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
5385	9201	rkcif_lvds_set_sof(cif_dev, seq);
5386		- else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
5387		- sensor->mbus.type == V4L2_MBUS_BT656)
	9202	+ } else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
	9203	+ sensor->mbus.type == V4L2_MBUS_BT656) {
5388	9204	rkcif_dvp_set_sof(cif_dev, seq);
	9205	+ }
5389	9206	}
5390	9207
5391		-static int rkcif_streamoff_in_reset(struct rkcif_device *cif_dev,
5392		- struct rkcif_stream *resume_stream[],
5393		- struct rkcif_resume_info *resume_info,
5394		- enum rkmodule_reset_src reset_src)
	9208	+static void rkcif_toisp_set_stream(struct rkcif_device *dev, int on)
5395	9209	{
5396		- struct rkcif_stream *stream = NULL;
	9210	+ struct v4l2_subdev *sd = get_rkisp_sd(dev->sditf[0]);
	9211	+
	9212	+ if (sd)
	9213	+ v4l2_subdev_call(sd, core, ioctl,
	9214	+ RKISP_VICAP_CMD_SET_STREAM, &on);
	9215	+}
	9216	+
	9217	+static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
	9218	+ enum rkmodule_reset_src reset_src)
	9219	+{
5397	9220	struct rkcif_pipeline *p = &cif_dev->pipe;
	9221	+ struct rkcif_stream *stream = NULL;
	9222	+ struct rkcif_stream *resume_stream[RKCIF_MAX_STREAM_MIPI] = { NULL };
5398	9223	struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
5399		- u32 on, sof_cnt;
	9224	+ struct rkcif_resume_info *resume_info = &cif_dev->reset_work.resume_info;
	9225	+ struct rkcif_timer *timer = &cif_dev->reset_watchdog_timer;
	9226	+ struct sditf_priv *priv = cif_dev->sditf[0];
5400	9227	int i, j, ret = 0;
5401		- int stream_off_cnt = 0;
	9228	+ u32 on, sof_cnt;
	9229	+ int capture_mode = 0;
	9230	+
	9231	+ mutex_lock(&cif_dev->stream_lock);
	9232	+ if (cif_dev->reset_work_cancel) {
	9233	+ ret = 0;
	9234	+ goto unlock_stream;
	9235	+ }
	9236	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset\n");
5402	9237
5403	9238	for (i = 0, j = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
5404	9239	stream = &cif_dev->stream[i];
5405		- mutex_lock(&cif_dev->stream_lock);
	9240	+
5406	9241	if (stream->state == RKCIF_STATE_STREAMING) {
5407		- stream_off_cnt++;
5408	9242
5409	9243	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5410	9244	"stream[%d] stopping\n", stream->id);
5411	9245
5412	9246	rkcif_stream_stop(stream);
5413	9247
5414		- atomic_dec(&p->stream_cnt);
5415		-
5416	9248	if (stream->id == RKCIF_STREAM_MIPI_ID0) {
5417	9249	sof_cnt = rkcif_get_sof(cif_dev);
5418		- v4l2_err(&cif_dev->v4l2_dev,
	9250	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5419	9251	"%s: stream[%d] sync frmid & csi_sof, frm_id:%d, csi_sof:%d\n",
5420	9252	__func__,
5421	9253	stream->id,
5422	9254	stream->frame_idx,
5423	9255	sof_cnt);
5424	9256
5425		- resume_info->frm_sync_seq = sof_cnt;
5426		- if (stream->frame_idx != sof_cnt)
5427		- stream->frame_idx = sof_cnt;
	9257	+ resume_info->frm_sync_seq = stream->frame_idx;
5428	9258	}
5429	9259
5430	9260	stream->state = RKCIF_STATE_RESET_IN_STREAMING;
..	..	@@ -5435,59 +9265,66 @@
5435	9265
5436	9266	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5437	9267	"%s stop stream[%d] in streaming, frm_id:%d, csi_sof:%d\n",
5438		- __func__, stream->id, stream->frame_idx, rkcif_csi2_get_sof());
	9268	+ __func__, stream->id, stream->frame_idx, rkcif_get_sof(cif_dev));
5439	9269
5440	9270	}
5441		- mutex_unlock(&cif_dev->stream_lock);
5442	9271	}
5443		- if (!stream_off_cnt)
5444		- return 0;
5445	9272
5446	9273	on = 0;
5447	9274	for (i = 0; i < p->num_subdevs; i++) {
5448	9275
5449	9276	if (p->subdevs[i] == terminal_sensor->sd) {
5450	9277
5451		- if (reset_src == RKCIF_RESET_SRC_ERR_CSI2 \|\|
5452		- reset_src == RKCIF_RESET_SRC_ERR_HOTPLUG \|\|
5453		- reset_src == RKICF_RESET_SRC_ERR_CUTOFF) {
5454		-
	9278	+ if (reset_src != RKCIF_RESET_SRC_ERR_APP) {
5455	9279	ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
5456	9280	RKMODULE_SET_QUICK_STREAM, &on);
5457	9281	if (ret)
5458		- v4l2_err(&cif_dev->v4l2_dev, "quick stream off subdev:%s failed\n",
	9282	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	9283	+ "quick stream off subdev:%s failed\n",
5459	9284	p->subdevs[i]->name);
5460	9285	}
	9286	+ } else {
	9287	+ ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
5461	9288	}
5462		-
5463	9289	if (ret)
5464		- v4l2_err(&cif_dev->v4l2_dev, "%s:stream %s subdev:%s failed\n",
	9290	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	9291	+ "%s:stream %s subdev:%s failed\n",
5465	9292	__func__, on ? "on" : "off", p->subdevs[i]->name);
5466		-
5467	9293	}
5468		- return ret;
5469		-}
5470	9294
5471		-static int rkcif_streamon_in_reset(struct rkcif_device *cif_dev,
5472		- struct rkcif_stream *resume_stream[],
5473		- struct rkcif_resume_info *resume_info,
5474		- enum rkmodule_reset_src reset_src)
5475		-{
5476		- struct rkcif_timer *timer = &cif_dev->reset_watchdog_timer;
5477		- struct rkcif_stream *stream = NULL;
5478		- struct rkcif_pipeline *p = &cif_dev->pipe;
5479		- struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
5480		- int i = 0;
5481		- int ret = 0;
5482		- int on = 0;
5483		- int stream_on_cnt = 0;
	9295	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	9296	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	9297	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	9298	+ ret = v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
	9299	+ RKMODULE_SET_QUICK_STREAM, &on);
	9300	+ }
	9301	+ }
5484	9302
5485		- for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	9303	+ rockchip_clear_system_status(SYS_STATUS_CIF0);
	9304	+
	9305	+ if (cif_dev->chip_id >= CHIP_RK3588_CIF) {
	9306	+ rkcif_do_soft_reset(cif_dev);
	9307	+ } else {
	9308	+
	9309	+ rkcif_do_cru_reset(cif_dev);
	9310	+
	9311	+ rkcif_disable_sys_clk(cif_dev->hw_dev);
	9312	+
	9313	+ udelay(5);
	9314	+
	9315	+ ret = rkcif_enable_sys_clk(cif_dev->hw_dev);
	9316	+
	9317	+ if (ret < 0) {
	9318	+ v4l2_err(&cif_dev->v4l2_dev, "%s:resume cif clk failed\n", __func__);
	9319	+ goto unlock_stream;
	9320	+ }
	9321	+ }
	9322	+
	9323	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	9324	+ rkcif_toisp_set_stream(cif_dev, 1);
	9325	+
	9326	+ for (i = 0; i < j; i++) {
5486	9327	stream = resume_stream[i];
5487		- if (stream == NULL \|\| stream->state != RKCIF_STATE_RESET_IN_STREAMING)
5488		- break;
5489		- mutex_lock(&cif_dev->stream_lock);
5490		- stream_on_cnt++;
5491	9328	stream->fs_cnt_in_single_frame = 0;
5492	9329	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
5493	9330	if (stream->curr_buf == stream->next_buf) {
..	..	@@ -5502,26 +9339,35 @@
5502	9339	stream->curr_buf = NULL;
5503	9340	stream->next_buf = NULL;
5504	9341	}
5505		- if (cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
5506		- cif_dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)
5507		- ret = rkcif_csi_stream_start(stream);
	9342	+ if (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AIQ)
	9343	+ capture_mode = RKCIF_STREAM_MODE_CAPTURE;
	9344	+ else {
	9345	+ if (cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	9346	+ capture_mode = RKCIF_STREAM_MODE_TOISP;
	9347	+ else
	9348	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	9349	+ }
	9350	+ if (cif_dev->active_sensor &&
	9351	+ (cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	9352	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	9353	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_CCP2))
	9354	+ ret = rkcif_csi_stream_start(stream, capture_mode);
5508	9355	else
5509		- ret = rkcif_stream_start(stream);
	9356	+ ret = rkcif_stream_start(stream, capture_mode);
5510	9357	if (ret) {
5511	9358	v4l2_err(&cif_dev->v4l2_dev, "%s:resume stream[%d] failed\n",
5512	9359	__func__, stream->id);
5513	9360	goto unlock_stream;
5514	9361	}
5515		- atomic_inc(&p->stream_cnt);
5516		- stream->streamon_timestamp = ktime_get_ns();
5517		- mutex_unlock(&cif_dev->stream_lock);
	9362	+
5518	9363	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5519	9364	"resume stream[%d], frm_idx:%d, csi_sof:%d\n",
5520	9365	stream->id, stream->frame_idx,
5521	9366	rkcif_get_sof(cif_dev));
5522	9367	}
5523		- if (!stream_on_cnt)
5524		- return 0;
	9368	+
	9369	+ rockchip_set_system_status(SYS_STATUS_CIF0);
	9370	+
5525	9371	on = 1;
5526	9372	for (i = 0; i < p->num_subdevs; i++) {
5527	9373
..	..	@@ -5529,9 +9375,7 @@
5529	9375
5530	9376	rkcif_set_sof(cif_dev, resume_info->frm_sync_seq);
5531	9377
5532		- if (reset_src == RKCIF_RESET_SRC_ERR_CSI2 \|\|
5533		- reset_src == RKCIF_RESET_SRC_ERR_HOTPLUG \|\|
5534		- reset_src == RKICF_RESET_SRC_ERR_CUTOFF) {
	9378	+ if (reset_src != RKCIF_RESET_SRC_ERR_APP) {
5535	9379	ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
5536	9380	RKMODULE_SET_QUICK_STREAM, &on);
5537	9381	if (ret)
..	..	@@ -5539,6 +9383,11 @@
5539	9383	"quick stream on subdev:%s failed\n",
5540	9384	p->subdevs[i]->name);
5541	9385	}
	9386	+ } else {
	9387	+ if (p->subdevs[i] == terminal_sensor->sd)
	9388	+ rkcif_set_sof(cif_dev, resume_info->frm_sync_seq);
	9389	+
	9390	+ ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
5542	9391	}
5543	9392
5544	9393	if (ret)
..	..	@@ -5546,71 +9395,28 @@
5546	9395	p->subdevs[i]->name);
5547	9396	}
5548	9397
5549		- rkcif_start_luma(&cif_dev->luma_vdev, resume_stream[0]->cif_fmt_in);
	9398	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	9399	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	9400	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	9401	+ v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
	9402	+ RKMODULE_SET_QUICK_STREAM, &on);
	9403	+ }
	9404	+ }
	9405	+
	9406	+ if (cif_dev->chip_id < CHIP_RK3588_CIF)
	9407	+ rkcif_start_luma(&cif_dev->luma_vdev,
	9408	+ cif_dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
5550	9409
5551	9410	timer->csi2_err_triggered_cnt = 0;
	9411	+ rkcif_monitor_reset_event(cif_dev);
5552	9412
5553	9413	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset successfully!\n");
5554		-
5555	9414	mutex_unlock(&cif_dev->stream_lock);
5556	9415	return 0;
5557	9416
5558	9417	unlock_stream:
5559	9418	mutex_unlock(&cif_dev->stream_lock);
5560	9419	return ret;
5561		-}
5562		-
5563		-static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
5564		- enum rkmodule_reset_src reset_src)
5565		-{
5566		- struct rkcif_stream *resume_stream[RKCIF_MAX_DEV][RKCIF_MAX_STREAM_MIPI] = {0};
5567		- struct rkcif_resume_info *resume_info[RKCIF_MAX_DEV];
5568		- struct rkcif_hw *hw = cif_dev->hw_dev;
5569		- struct rkcif_device *cifdev = NULL;
5570		- int i = 0;
5571		- int ret = 0;
5572		-
5573		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset\n");
5574		-
5575		- for (i = 0; i < hw->dev_num; i++) {
5576		- cifdev = hw->cif_dev[i];
5577		- resume_info[i] = &cifdev->reset_work.resume_info;
5578		- ret \|= rkcif_streamoff_in_reset(cifdev,
5579		- resume_stream[i],
5580		- resume_info[i],
5581		- reset_src);
5582		- }
5583		-
5584		- rockchip_clear_system_status(SYS_STATUS_CIF0);
5585		-
5586		- rkcif_do_cru_reset(cif_dev);
5587		-
5588		- rkcif_disable_sys_clk(cif_dev->hw_dev);
5589		-
5590		- udelay(5);
5591		-
5592		- ret \|= rkcif_enable_sys_clk(cif_dev->hw_dev);
5593		- if (ret < 0)
5594		- v4l2_err(&cif_dev->v4l2_dev, "%s:resume cif clk failed\n", __func__);
5595		-
5596		- for (i = 0; i < hw->dev_num; i++) {
5597		- cifdev = hw->cif_dev[i];
5598		- resume_info[i] = &cifdev->reset_work.resume_info;
5599		- ret \|= rkcif_streamon_in_reset(cifdev,
5600		- resume_stream[i],
5601		- resume_info[i],
5602		- reset_src);
5603		- }
5604		-
5605		- rockchip_set_system_status(SYS_STATUS_CIF0);
5606		-
5607		- hw->hw_timer.is_running = false;
5608		- rkcif_monitor_reset_event(cif_dev->hw_dev);
5609		-
5610		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset successfully!\n");
5611		-
5612		- return ret;
5613		-
5614	9420	}
5615	9421
5616	9422	void rkcif_reset_work(struct work_struct *work)
..	..	@@ -5628,128 +9434,193 @@
5628	9434	v4l2_info(&dev->v4l2_dev, "do reset work failed!\n");
5629	9435	}
5630	9436
5631		-static bool rkcif_is_stream_stop_output(struct rkcif_stream *stream)
	9437	+static bool rkcif_is_reduced_frame_rate(struct rkcif_device *dev)
5632	9438	{
5633		- struct rkcif_device *dev = stream->cifdev;
5634		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
5635		- struct rkcif_stream *tmp_stream = NULL;
	9439	+ struct rkcif_timer *timer = &dev->reset_watchdog_timer;
	9440	+ struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
5636	9441	struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
5637		- u64 fps, diff_time;
5638		- unsigned int i;
5639		- s64 vblank_def = 0;
5640		- s32 vblank = 0;
5641		- u64 numerator = 0;
5642		- u64 denominator = 0;
5643		- u64 cur_timestamp = 0;
	9442	+ u64 fps, timestamp0, timestamp1, diff_time;
	9443	+ unsigned long fps_flags;
	9444	+ unsigned int deviation = 1;
	9445	+ bool is_reduced = false;
	9446	+ u64 cur_time = 0;
	9447	+ u64 time_distance = 0;
5644	9448
5645		- if (dev->hdr.mode == HDR_X3) {
5646		- for (i = 0; i < 3; i++) {
5647		- tmp_stream = &dev->stream[i];
5648		- if (tmp_stream->state != RKCIF_STATE_STREAMING)
5649		- return false;
5650		- }
5651		- } else if (dev->hdr.mode == HDR_X2) {
5652		- for (i = 0; i < 2; i++) {
5653		- tmp_stream = &dev->stream[i];
5654		- if (tmp_stream->state != RKCIF_STATE_STREAMING)
5655		- return false;
5656		- }
5657		- }
	9449	+ spin_lock_irqsave(&stream->fps_lock, fps_flags);
	9450	+ timestamp0 = stream->fps_stats.frm0_timestamp;
	9451	+ timestamp1 = stream->fps_stats.frm1_timestamp;
	9452	+ spin_unlock_irqrestore(&stream->fps_lock, fps_flags);
5658	9453
5659		- vblank_def = rkcif_get_sensor_vblank_def(dev);
5660		- vblank = rkcif_get_sensor_vblank(dev);
5661		- numerator = dev->terminal_sensor.fi.interval.numerator;
5662		- denominator = dev->terminal_sensor.fi.interval.denominator;
5663		- fps = div_u64(1000 * numerator, denominator);
5664		- fps *= (raw_rect->height + vblank);
5665		- fps = div_u64((raw_rect->height + vblank_def), fps);
	9454	+ fps = timestamp0 > timestamp1 ?
	9455	+ timestamp0 - timestamp1 : timestamp1 - timestamp0;
	9456	+ fps = div_u64(fps, 1000);
	9457	+ diff_time = fps > timer->frame_end_cycle_us ?
	9458	+ fps - timer->frame_end_cycle_us : 0;
	9459	+ deviation = DIV_ROUND_UP(timer->vts, 100);
5666	9460
5667		- if (fps > hw_timer->monitor_cycle) {
5668		- v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "camera work in long expsure, not to check stream loss\n");
	9461	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "diff_time:%lld,devi_t:%ld,devi_h:%d\n",
	9462	+ diff_time, timer->line_end_cycle * deviation, deviation);
	9463	+
	9464	+ cur_time = rkcif_time_get_ns(dev);
	9465	+ time_distance = timestamp0 > timestamp1 ?
	9466	+ cur_time - timestamp0 : cur_time - timestamp1;
	9467	+ time_distance = div_u64(time_distance, 1000);
	9468	+ if (time_distance > fps * 2)
5669	9469	return false;
	9470	+
	9471	+ if (diff_time > timer->line_end_cycle * deviation) {
	9472	+ s32 vblank = 0;
	9473	+ unsigned int vts;
	9474	+
	9475	+ is_reduced = true;
	9476	+ vblank = rkcif_get_sensor_vblank(dev);
	9477	+ vts = vblank + timer->raw_height;
	9478	+
	9479	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "old vts:%d,new vts:%d\n", timer->vts, vts);
	9480	+
	9481	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	9482	+ "reduce frame rate,vblank:%d, height(raw output):%d, fps:%lld, frm_end_t:%ld, line_t:%ld, diff:%lld\n",
	9483	+ rkcif_get_sensor_vblank(dev),
	9484	+ raw_rect->height,
	9485	+ fps,
	9486	+ timer->frame_end_cycle_us,
	9487	+ timer->line_end_cycle,
	9488	+ diff_time);
	9489	+
	9490	+ timer->vts = vts;
	9491	+ timer->frame_end_cycle_us = fps;
	9492	+ timer->line_end_cycle = div_u64(timer->frame_end_cycle_us, timer->vts);
	9493	+ } else {
	9494	+ is_reduced = false;
5670	9495	}
5671	9496
5672		- cur_timestamp = ktime_get_ns();
5673		- diff_time = cur_timestamp - stream->streamon_timestamp;
5674		- diff_time = div_u64(diff_time, 1000000);
5675		- if (diff_time > hw_timer->monitor_cycle + 10)
5676		- return true;
	9497	+ timer->frame_end_cycle_us = fps;
5677	9498
5678		- return false;
	9499	+ fps = div_u64(fps, 1000);
	9500	+ fps = fps * timer->frm_num_of_monitor_cycle;
	9501	+ timer->cycle = msecs_to_jiffies(fps);
	9502	+ timer->timer.expires = jiffies + timer->cycle;
	9503	+
	9504	+ return is_reduced;
	9505	+
5679	9506	}
5680	9507
5681		-static void rkcif_init_reset_work(struct rkcif_hw_timer *hw_timer)
	9508	+static void rkcif_dvp_event_reset_pipe(struct rkcif_device *dev, int reset_src)
5682	9509	{
5683		- struct rkcif_hw *hw = container_of(hw_timer,
5684		- struct rkcif_hw,
5685		- hw_timer);
5686		- struct rkcif_device *dev = NULL;
	9510	+ struct rkcif_dvp_sof_subdev *subdev = &dev->dvp_sof_subdev;
	9511	+
	9512	+ if (subdev) {
	9513	+ struct v4l2_event event = {
	9514	+ .type = V4L2_EVENT_RESET_DEV,
	9515	+ .reserved[0] = reset_src,
	9516	+ };
	9517	+ v4l2_event_queue(subdev->sd.devnode, &event);
	9518	+ }
	9519	+}
	9520	+
	9521	+static void rkcif_lvds_event_reset_pipe(struct rkcif_device *dev, int reset_src)
	9522	+{
	9523	+ struct rkcif_lvds_subdev *subdev = &dev->lvds_subdev;
	9524	+
	9525	+ if (subdev) {
	9526	+ struct v4l2_event event = {
	9527	+ .type = V4L2_EVENT_RESET_DEV,
	9528	+ .reserved[0] = reset_src,
	9529	+ };
	9530	+ v4l2_event_queue(subdev->sd.devnode, &event);
	9531	+ }
	9532	+}
	9533	+
	9534	+static void rkcif_send_reset_event(struct rkcif_device *cif_dev, int reset_src)
	9535	+{
	9536	+ struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
	9537	+ struct csi2_dev *csi;
	9538	+
	9539	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	9540	+ mbus->type == V4L2_MBUS_CSI2_CPHY) {
	9541	+ csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
	9542	+ rkcif_csi2_event_reset_pipe(csi, reset_src);
	9543	+ } else if (mbus->type == V4L2_MBUS_CCP2) {
	9544	+ rkcif_lvds_event_reset_pipe(cif_dev, reset_src);
	9545	+ } else {
	9546	+ rkcif_dvp_event_reset_pipe(cif_dev, reset_src);
	9547	+ }
	9548	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	9549	+ "send reset event,bus type 0x%x\n",
	9550	+ mbus->type);
	9551	+}
	9552	+
	9553	+static void rkcif_init_reset_work(struct rkcif_timer *timer)
	9554	+{
	9555	+ struct rkcif_device *dev = container_of(timer,
	9556	+ struct rkcif_device,
	9557	+ reset_watchdog_timer);
5687	9558	struct rkcif_stream *stream = NULL;
5688		- struct rkcif_timer *timer;
5689	9559	unsigned long flags;
5690		- int i = 0, j = 0;
	9560	+ int i = 0;
5691	9561
5692	9562	v4l2_info(&dev->v4l2_dev,
5693	9563	"do reset work schedule, run_cnt:%d, reset source:%d\n",
5694		- hw_timer->run_cnt, hw_timer->reset_src);
	9564	+ timer->run_cnt, timer->reset_src);
5695	9565
5696		- for (j = 0; j < hw->dev_num; j++) {
5697		- dev = hw->cif_dev[j];
5698		- timer = &dev->reset_watchdog_timer;
5699		- spin_lock_irqsave(&timer->csi2_err_lock, flags);
5700		- timer->is_triggered = false;
5701		- timer->csi2_err_cnt_odd = 0;
5702		- timer->csi2_err_cnt_even = 0;
5703		- timer->csi2_err_fs_fe_cnt = 0;
5704		- timer->notifer_called_cnt = 0;
5705		- for (i = 0; i < dev->num_channels; i++) {
5706		- stream = &dev->stream[i];
5707		- if (stream->state == RKCIF_STATE_STREAMING)
5708		- timer->last_buf_wakeup_cnt[stream->id] = stream->frame_idx;
5709		- }
5710		- spin_unlock_irqrestore(&timer->csi2_err_lock, flags);
	9566	+ spin_lock_irqsave(&timer->timer_lock, flags);
	9567	+ timer->is_running = false;
	9568	+ timer->is_triggered = false;
	9569	+ timer->csi2_err_cnt_odd = 0;
	9570	+ timer->csi2_err_cnt_even = 0;
	9571	+ timer->csi2_err_fs_fe_cnt = 0;
	9572	+ timer->notifer_called_cnt = 0;
	9573	+ dev->is_toisp_reset = false;
	9574	+ for (i = 0; i < dev->num_channels; i++) {
	9575	+ stream = &dev->stream[i];
	9576	+ if (stream->state == RKCIF_STATE_STREAMING)
	9577	+ timer->last_buf_wakeup_cnt[stream->id] = stream->buf_wake_up_cnt;
5711	9578	}
5712		- if (hw_timer->is_reset_by_user) {
5713		- hw->reset_info.is_need_reset = 1;
5714		- hw->reset_info.reset_src = hw_timer->reset_src;
	9579	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
	9580	+ if (timer->is_ctrl_by_user) {
	9581	+ rkcif_send_reset_event(dev, timer->reset_src);
5715	9582	} else {
5716		- dev->reset_work.reset_src = hw_timer->reset_src;
5717		- if (schedule_work(&dev->reset_work.work)) {
	9583	+ dev->reset_work.reset_src = timer->reset_src;
	9584	+ if (!schedule_work(&dev->reset_work.work))
5718	9585	v4l2_info(&dev->v4l2_dev,
5719		- "schedule reset work successfully\n");
5720		- } else {
5721		- v4l2_info(&dev->v4l2_dev,
5722		- "schedule reset work failed\n");
5723		- }
	9586	+ "schedule reset work failed\n");
5724	9587	}
5725	9588	}
5726	9589
5727	9590	static int rkcif_detect_reset_event(struct rkcif_stream *stream,
5728	9591	struct rkcif_timer *timer,
5729		- int *check_cnt,
	9592	+ int check_cnt,
5730	9593	bool *is_mod_timer)
5731	9594	{
5732	9595	struct rkcif_device *dev = stream->cifdev;
5733	9596	struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
5734		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
	9597	+ unsigned long flags;
5735	9598	int ret, is_reset = 0;
5736	9599	struct rkmodule_vicap_reset_info rst_info;
5737	9600
5738		- v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
5739		- "info: frame end still update(%d, %d), detect cnt: %d, mode:%d check_cnt:%d\n",
5740		- timer->last_buf_wakeup_cnt[stream->id], stream->frame_idx,
5741		- hw_timer->run_cnt, hw_timer->monitor_mode, *check_cnt);
	9601	+ if (dev->is_toisp_reset) {
	9602	+ is_reset = 1;
	9603	+ timer->reset_src = RKCIF_RESET_SRC_ERR_ISP;
	9604	+ }
	9605	+ if (is_reset) {
	9606	+ rkcif_init_reset_work(timer);
	9607	+ return is_reset;
	9608	+ }
5742	9609
5743		- if (timer->last_buf_wakeup_cnt[stream->id] < stream->frame_idx) {
5744		- *check_cnt += 1;
	9610	+ if (timer->last_buf_wakeup_cnt[stream->id] < stream->buf_wake_up_cnt &&
	9611	+ check_cnt == 0) {
	9612	+
5745	9613	v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
5746		- "info: frame end still update(%d, %d), detect cnt: %d, mode:%d\n",
	9614	+ "info: frame end still update(%d, %d) in detecting cnt:%d, mode:%d\n",
5747	9615	timer->last_buf_wakeup_cnt[stream->id], stream->frame_idx,
5748		- hw_timer->run_cnt, hw_timer->monitor_mode);
	9616	+ timer->run_cnt, timer->monitor_mode);
5749	9617
5750		- timer->last_buf_wakeup_cnt[stream->id] = stream->frame_idx;
	9618	+ timer->last_buf_wakeup_cnt[stream->id] = stream->buf_wake_up_cnt;
5751	9619
5752		- if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
	9620	+ if (stream->frame_idx > 2)
	9621	+ rkcif_is_reduced_frame_rate(dev);
	9622	+
	9623	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
5753	9624	ret = v4l2_subdev_call(terminal_sensor->sd,
5754	9625	core, ioctl,
5755	9626	RKMODULE_GET_VICAP_RST_INFO,
..	..	@@ -5759,144 +9630,139 @@
5759	9630	else
5760	9631	is_reset = rst_info.is_reset;
5761	9632	rst_info.is_reset = 0;
5762		- hw_timer->reset_src = RKCIF_RESET_SRC_ERR_HOTPLUG;
	9633	+ if (is_reset)
	9634	+ timer->reset_src = RKCIF_RESET_SRC_ERR_HOTPLUG;
5763	9635	v4l2_subdev_call(terminal_sensor->sd, core, ioctl,
5764	9636	RKMODULE_SET_VICAP_RST_INFO, &rst_info);
5765		- if (!is_reset && stream->cifdev->inf_id == RKCIF_MIPI_LVDS)
	9637	+ if (!is_reset) {
5766	9638	is_reset = rkcif_is_csi2_err_trigger_reset(timer);
5767		- } else if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE) {
5768		- if (stream->cifdev->inf_id == RKCIF_MIPI_LVDS)
5769		- is_reset = rkcif_is_csi2_err_trigger_reset(timer);
5770		- } else if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
5771		- if (stream->cifdev->inf_id == RKCIF_MIPI_LVDS) {
5772		- is_reset = timer->is_csi2_err_occurred;
5773	9639	if (is_reset)
5774		- hw_timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
5775		- timer->is_csi2_err_occurred = false;
	9640	+ timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
5776	9641	}
	9642	+ } else if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE) {
	9643	+ is_reset = rkcif_is_csi2_err_trigger_reset(timer);
	9644	+ } else if (timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
	9645	+ is_reset = timer->is_csi2_err_occurred;
	9646	+ if (is_reset)
	9647	+ timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
	9648	+ timer->is_csi2_err_occurred = false;
5777	9649	}
5778	9650
5779	9651	if (is_reset) {
5780		- rkcif_init_reset_work(hw_timer);
	9652	+ rkcif_init_reset_work(timer);
5781	9653	return is_reset;
5782	9654	}
5783		- *is_mod_timer = true;
5784		- } else if (timer->last_buf_wakeup_cnt[stream->id] == stream->frame_idx) {
5785		- bool is_loss_stream = false;
5786	9655
5787		- *check_cnt += 1;
5788		- if (hw_timer->run_cnt > 4)
5789		- is_loss_stream = rkcif_is_stream_stop_output(stream);
5790		-
5791		- if (is_loss_stream) {
5792		- v4l2_info(&dev->v4l2_dev,
5793		- "do reset work due to frame end is stopped, run_cnt:%d\n",
5794		- hw_timer->run_cnt);
5795		-
5796		- hw_timer->reset_src = RKICF_RESET_SRC_ERR_CUTOFF;
5797		- is_reset = true;
5798		- rkcif_init_reset_work(hw_timer);
	9656	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE \|\|
	9657	+ timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
	9658	+ if (timer->run_cnt == timer->max_run_cnt)
	9659	+ timer->run_cnt = 0x0;
	9660	+ *is_mod_timer = true;
5799	9661	} else {
	9662	+ if (timer->run_cnt <= timer->max_run_cnt) {
	9663	+ *is_mod_timer = true;
	9664	+ } else {
	9665	+ spin_lock_irqsave(&timer->timer_lock, flags);
	9666	+ timer->is_triggered = false;
	9667	+ timer->is_running = false;
	9668	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
	9669	+ v4l2_info(&dev->v4l2_dev, "stop reset detecting!\n");
	9670	+ }
	9671	+ }
	9672	+ } else if (timer->last_buf_wakeup_cnt[stream->id] == stream->buf_wake_up_cnt) {
	9673	+
	9674	+ bool is_reduced = false;
	9675	+
	9676	+ if (stream->frame_idx > 2)
	9677	+ is_reduced = rkcif_is_reduced_frame_rate(dev);
	9678	+ else if (timer->run_cnt < 20)
	9679	+ is_reduced = true;
	9680	+
	9681	+ if (is_reduced) {
5800	9682	*is_mod_timer = true;
5801	9683	v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s fps is reduced\n", __func__);
	9684	+ } else {
	9685	+
	9686	+ v4l2_info(&dev->v4l2_dev,
	9687	+ "do reset work due to frame end is stopped, run_cnt:%d\n",
	9688	+ timer->run_cnt);
	9689	+
	9690	+ timer->reset_src = RKICF_RESET_SRC_ERR_CUTOFF;
	9691	+ rkcif_init_reset_work(timer);
	9692	+ is_reset = true;
5802	9693	}
5803	9694	}
5804	9695
5805		- return is_reset;
5806		-
5807		-}
5808		-
5809		-static int rkcif_dvp_err_trigger_reset(struct rkcif_device *dev)
5810		-{
5811		- int is_reset = 0;
5812		-
5813		- if (dev->irq_stats.dvp_overflow_cnt) {
5814		- dev->irq_stats.dvp_overflow_cnt = 0;
5815		- is_reset = 1;
5816		- }
5817		- return is_reset;
5818		-}
5819		-
5820		-static int rkcif_detect_reset_event_all_dev(struct rkcif_device *dev,
5821		- int *check_cnt,
5822		- bool *is_mod_timer)
5823		-{
5824		- struct rkcif_timer *timer = &dev->reset_watchdog_timer;
5825		- struct rkcif_stream *stream = NULL;
5826		- int i = 0;
5827		- int is_reset = 0;
5828		- int check_cnt_local = 0;
5829		-
5830		- for (i = 0; i < dev->num_channels; i++) {
5831		- stream = &dev->stream[i];
5832		- if (stream->state == RKCIF_STATE_STREAMING) {
5833		- is_reset = rkcif_detect_reset_event(stream,
5834		- timer,
5835		- &check_cnt_local,
5836		- is_mod_timer);
5837		- if (is_reset)
5838		- break;
5839		- }
5840		- }
5841		- if (!is_reset && dev->inf_id == RKCIF_DVP)
5842		- is_reset = rkcif_dvp_err_trigger_reset(dev);
5843		-
5844		- if (check_cnt_local)
5845		- *check_cnt += 1;
5846	9696	return is_reset;
5847	9697
5848	9698	}
5849	9699
5850	9700	void rkcif_reset_watchdog_timer_handler(struct timer_list *t)
5851	9701	{
5852		- struct rkcif_hw_timer *hw_timer = container_of(t, struct rkcif_hw_timer, timer);
5853		- struct rkcif_hw *hw = container_of(hw_timer,
5854		- struct rkcif_hw,
5855		- hw_timer);
5856		- struct rkcif_device *dev = NULL;
	9702	+ struct rkcif_timer *timer = container_of(t, struct rkcif_timer, timer);
	9703	+ struct rkcif_device *dev = container_of(timer,
	9704	+ struct rkcif_device,
	9705	+ reset_watchdog_timer);
	9706	+ struct rkcif_stream *stream = NULL;
5857	9707	unsigned long flags;
5858	9708	unsigned int i;
5859	9709	int is_reset = 0;
5860	9710	int check_cnt = 0;
5861	9711	bool is_mod_timer = false;
5862	9712
5863		- for (i = 0; i < hw->dev_num; i++) {
5864		- dev = hw->cif_dev[i];
5865		- is_reset = rkcif_detect_reset_event_all_dev(dev,
5866		- &check_cnt,
	9713	+ for (i = 0; i < dev->num_channels; i++) {
	9714	+ stream = &dev->stream[i];
	9715	+ if (stream->state == RKCIF_STATE_STREAMING) {
	9716	+ is_reset = rkcif_detect_reset_event(stream,
	9717	+ timer,
	9718	+ check_cnt,
5867	9719	&is_mod_timer);
5868		- if (is_reset)
5869		- break;
5870		-
	9720	+ check_cnt++;
	9721	+ if (is_reset)
	9722	+ break;
	9723	+ }
5871	9724	}
5872		-
5873	9725	if (!is_reset && is_mod_timer)
5874		- mod_timer(&hw_timer->timer, jiffies + hw_timer->cycle_jif);
	9726	+ mod_timer(&timer->timer, jiffies + timer->cycle);
5875	9727
5876		- hw_timer->run_cnt += 1;
	9728	+ timer->run_cnt += 1;
5877	9729
5878		- if (!check_cnt && !is_reset) {
5879		- spin_lock_irqsave(&hw_timer->timer_lock, flags);
5880		- hw_timer->is_running = false;
5881		- spin_unlock_irqrestore(&hw_timer->timer_lock, flags);
	9730	+ if (!check_cnt) {
	9731	+ spin_lock_irqsave(&timer->timer_lock, flags);
	9732	+ timer->is_triggered = false;
	9733	+ timer->is_running = false;
	9734	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
5882	9735
5883		- dev_info(hw->dev,
5884		- "all stream is stopped, stop reset detect!\n");
	9736	+ v4l2_info(&dev->v4l2_dev,
	9737	+ "all stream is stopped, stop reset detect!\n");
5885	9738	}
5886	9739	}
5887	9740
5888	9741	int rkcif_reset_notifier(struct notifier_block *nb,
5889	9742	unsigned long action, void *data)
5890	9743	{
5891		- struct rkcif_device *dev = container_of(nb, struct rkcif_device, reset_notifier);
5892		- struct rkcif_timer *timer = &dev->reset_watchdog_timer;
5893		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
	9744	+ struct rkcif_hw *hw = container_of(nb, struct rkcif_hw, reset_notifier);
	9745	+ struct rkcif_device *dev = NULL;
	9746	+ struct rkcif_timer *timer = NULL;
5894	9747	unsigned long flags, val;
	9748	+ u32 *csi_idx = data;
	9749	+ int i = 0;
	9750	+ bool is_match_dev = false;
5895	9751
5896		- if (hw_timer->is_running) {
	9752	+ for (i = 0; i < hw->dev_num; i++) {
	9753	+ dev = hw->cif_dev[i];
	9754	+ if (*csi_idx == dev->csi_host_idx) {
	9755	+ is_match_dev = true;
	9756	+ break;
	9757	+ }
	9758	+ }
	9759	+ if (!is_match_dev)
	9760	+ return -EINVAL;
	9761	+ timer = &dev->reset_watchdog_timer;
	9762	+ if (timer->is_running) {
5897	9763	val = action & CSI2_ERR_COUNT_ALL_MASK;
5898	9764	spin_lock_irqsave(&timer->csi2_err_lock, flags);
5899		- if ((val % hw_timer->err_ref_cnt) == 0) {
	9765	+ if ((val % timer->csi2_err_ref_cnt) == 0) {
5900	9766	timer->notifer_called_cnt++;
5901	9767	if ((timer->notifer_called_cnt % 2) == 0)
5902	9768	timer->csi2_err_cnt_even = val;
..	..	@@ -5914,7 +9780,12 @@
5914	9780	static void rkcif_modify_line_int(struct rkcif_stream *stream, bool en)
5915	9781	{
5916	9782	struct rkcif_device *cif_dev = stream->cifdev;
	9783	+ u32 line_intr_en = 0;
5917	9784
	9785	+ if (cif_dev->chip_id >= CHIP_RK3588_CIF)
	9786	+ line_intr_en = CSI_LINE_INTEN_RK3588(stream->id);
	9787	+ else
	9788	+ line_intr_en = CSI_LINE_INTEN(stream->id);
5918	9789	if (en) {
5919	9790	if (cif_dev->wait_line_bak != cif_dev->wait_line) {
5920	9791	cif_dev->wait_line_bak = cif_dev->wait_line;
..	..	@@ -5924,44 +9795,73 @@
5924	9795	cif_dev->wait_line << 16 \| cif_dev->wait_line);
5925	9796	}
5926	9797	rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
5927		- CSI_LINE_INTEN(stream->id));
	9798	+ line_intr_en);
	9799	+ stream->is_line_inten = true;
5928	9800	} else {
5929	9801	rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
5930		- ~(CSI_LINE_INTEN(stream->id)));
	9802	+ ~line_intr_en);
5931	9803	}
5932	9804	}
5933	9805
5934	9806	static void rkcif_detect_wake_up_mode_change(struct rkcif_stream *stream)
5935	9807	{
5936	9808	struct rkcif_device *cif_dev = stream->cifdev;
	9809	+ struct sditf_priv *priv = cif_dev->sditf[0];
	9810	+ bool is_change = false;
	9811	+ int ch = 0;
	9812	+ int i = 0;
	9813	+
	9814	+ if (!priv \|\| priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	9815	+ return;
	9816	+
	9817	+ if ((cif_dev->hdr.hdr_mode == NO_HDR \|\| cif_dev->hdr.hdr_mode == HDR_COMPR) &&
	9818	+ stream->id == RKCIF_STREAM_MIPI_ID0) {
	9819	+ if (cif_dev->wait_line != cif_dev->wait_line_cache)
	9820	+ cif_dev->wait_line = cif_dev->wait_line_cache;
	9821	+ } else if (cif_dev->hdr.hdr_mode == HDR_X2 && stream->id == RKCIF_STREAM_MIPI_ID1) {
	9822	+ if (cif_dev->wait_line != cif_dev->wait_line_cache)
	9823	+ cif_dev->wait_line = cif_dev->wait_line_cache;
	9824	+ } else if (cif_dev->hdr.hdr_mode == HDR_X3 && stream->id == RKCIF_STREAM_MIPI_ID2) {
	9825	+ if (cif_dev->wait_line != cif_dev->wait_line_cache)
	9826	+ cif_dev->wait_line = cif_dev->wait_line_cache;
	9827	+ }
5937	9828
5938	9829	if (cif_dev->wait_line && (!stream->is_line_wake_up)) {
	9830	+ is_change = true;
5939	9831	stream->is_line_wake_up = true;
5940	9832	if (stream->frame_phase == CIF_CSI_FRAME0_READY)
5941	9833	stream->line_int_cnt = 1;
5942	9834	else if (stream->frame_phase == CIF_CSI_FRAME1_READY)
5943	9835	stream->line_int_cnt = 0;
	9836	+ if (cif_dev->hdr.hdr_mode == HDR_X2) {
	9837	+ cif_dev->stream[0].is_line_wake_up = true;
	9838	+ cif_dev->stream[0].line_int_cnt = stream->line_int_cnt;
	9839	+ } else if (cif_dev->hdr.hdr_mode == HDR_X3) {
	9840	+ cif_dev->stream[0].is_line_wake_up = true;
	9841	+ cif_dev->stream[1].is_line_wake_up = true;
	9842	+ cif_dev->stream[0].line_int_cnt = stream->line_int_cnt;
	9843	+ cif_dev->stream[1].line_int_cnt = stream->line_int_cnt;
	9844	+ }
5944	9845	} else if ((cif_dev->wait_line == 0) && stream->is_line_wake_up) {
5945	9846	stream->is_line_wake_up = false;
5946	9847	}
5947	9848	if (stream->is_line_wake_up) {
5948		- rkcif_modify_line_int(stream, true);
5949		- stream->is_line_inten = true;
5950		- }
5951		-
5952		- if (cif_dev->hdr.mode == NO_HDR && stream->id == RKCIF_STREAM_MIPI_ID0) {
5953		- if (cif_dev->wait_line != cif_dev->wait_line_cache)
5954		- cif_dev->wait_line = cif_dev->wait_line_cache;
5955		- } else if (cif_dev->hdr.mode == HDR_X2 && stream->id == RKCIF_STREAM_MIPI_ID1) {
5956		- if (cif_dev->wait_line != cif_dev->wait_line_cache)
5957		- cif_dev->wait_line = cif_dev->wait_line_cache;
5958		- } else if (cif_dev->hdr.mode == HDR_X3 && stream->id == RKCIF_STREAM_MIPI_ID2) {
5959		- if (cif_dev->wait_line != cif_dev->wait_line_cache)
5960		- cif_dev->wait_line = cif_dev->wait_line_cache;
	9849	+ if (is_change) {
	9850	+ if (cif_dev->hdr.hdr_mode == HDR_X2)
	9851	+ ch = 2;
	9852	+ else if (cif_dev->hdr.hdr_mode == HDR_X3)
	9853	+ ch = 3;
	9854	+ else
	9855	+ ch = 1;
	9856	+ for (i = 0; i < ch; i++)
	9857	+ rkcif_modify_line_int(&cif_dev->stream[i], true);
	9858	+ } else {
	9859	+ rkcif_modify_line_int(stream, true);
	9860	+ }
5961	9861	}
5962	9862	}
5963	9863
5964		-static u32 rkisp_mbus_pixelcode_to_v4l2(u32 pixelcode)
	9864	+u32 rkcif_mbus_pixelcode_to_v4l2(u32 pixelcode)
5965	9865	{
5966	9866	u32 pixelformat;
5967	9867
..	..	@@ -6050,13 +9950,14 @@
6050	9950	v4l2_subdev_call(cif_dev->terminal_sensor.sd, pad, get_fmt, NULL, &fmt);
6051	9951
6052	9952	memset(&pixm, 0, sizeof(pixm));
6053		- pixm.pixelformat = rkisp_mbus_pixelcode_to_v4l2(fmt.format.code);
	9953	+ pixm.pixelformat = rkcif_mbus_pixelcode_to_v4l2(fmt.format.code);
6054	9954	pixm.width = fmt.format.width;
6055	9955	pixm.height = fmt.format.height;
6056	9956
6057	9957	memset(&input_sel, 0, sizeof(input_sel));
6058	9958	input_sel.pad = i;
6059	9959	input_sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
	9960	+ input_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
6060	9961	ret = v4l2_subdev_call(cif_dev->terminal_sensor.sd,
6061	9962	pad, get_selection, NULL,
6062	9963	&input_sel);
..	..	@@ -6069,12 +9970,1403 @@
6069	9970	}
6070	9971	}
6071	9972
	9973	+void rkcif_enable_dma_capture(struct rkcif_stream *stream, bool is_only_enable)
	9974	+{
	9975	+ struct rkcif_device *cif_dev = stream->cifdev;
	9976	+ struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
	9977	+ struct csi_channel_info *channel = &cif_dev->channels[stream->id];
	9978	+ u32 val = 0;
	9979	+
	9980	+ if (stream->buf_owner == RKCIF_DMAEN_BY_ISP)
	9981	+ stream->buf_owner = RKCIF_DMAEN_BY_ISP_TO_VICAP;
	9982	+
	9983	+ atomic_dec(&cif_dev->streamoff_cnt);
	9984	+ if (stream->dma_en) {
	9985	+ stream->dma_en \|= stream->to_en_dma;
	9986	+ stream->to_en_dma = 0;
	9987	+ return;
	9988	+ }
	9989	+
	9990	+ stream->dma_en \|= stream->to_en_dma;
	9991	+ if (!is_only_enable) {
	9992	+ if (stream->to_en_dma == RKCIF_DMAEN_BY_VICAP) {
	9993	+ rkcif_assign_new_buffer_pingpong(stream,
	9994	+ RKCIF_YUV_ADDR_STATE_INIT,
	9995	+ stream->id);
	9996	+ rkcif_write_register(cif_dev, get_reg_index_of_frm0_y_vlw(stream->id),
	9997	+ channel->virtual_width);
	9998	+ } else if (stream->to_en_dma == RKCIF_DMAEN_BY_ISP) {
	9999	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	10000	+ RKCIF_YUV_ADDR_STATE_INIT,
	10001	+ stream->id);
	10002	+ }
	10003	+ }
	10004	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	10005	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
	10006	+ rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_CTRL, 0x00010000);
	10007	+ else
	10008	+ rkcif_write_register_or(cif_dev, CIF_REG_DVP_CTRL, 0x00010000);
	10009	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	10010	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY) {
	10011	+ val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
	10012	+ if (!stream->is_compact)
	10013	+ val \|= CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	10014	+ else
	10015	+ val &= ~CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	10016	+ val \|= CSI_DMA_ENABLE;
	10017	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
	10018	+ } else if (mbus_cfg->type == V4L2_MBUS_CCP2) {
	10019	+ val = rkcif_read_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id));
	10020	+ if (!stream->is_compact)
	10021	+ val \|= CSI_WRDDR_TYPE_RAW_UNCOMPACT << 17;
	10022	+ else
	10023	+ val &= ~(CSI_WRDDR_TYPE_RAW_UNCOMPACT << 17);
	10024	+ val \|= LVDS_DMAEN_RV1106;
	10025	+ rkcif_write_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id), val);
	10026	+ } else {
	10027	+ val = rkcif_read_register(cif_dev, CIF_REG_DVP_FOR);
	10028	+ if (!stream->is_compact)
	10029	+ val \|= CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
	10030	+ else
	10031	+ val &= ~(CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11);
	10032	+ rkcif_write_register(cif_dev, CIF_REG_DVP_FOR, val);
	10033	+ val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
	10034	+ if (cif_dev->chip_id == CHIP_RK3588_CIF)
	10035	+ val \|= DVP_DMA_EN;
	10036	+ else if (cif_dev->chip_id == CHIP_RV1106_CIF)
	10037	+ val \|= DVP_SW_DMA_EN(stream->id);
	10038	+ rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
	10039	+ }
	10040	+
	10041	+ stream->to_en_dma = 0;
	10042	+}
	10043	+
	10044	+static int rkcif_stop_dma_capture(struct rkcif_stream *stream)
	10045	+{
	10046	+ struct rkcif_device *cif_dev = stream->cifdev;
	10047	+ struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
	10048	+ u32 val = 0;
	10049	+
	10050	+ if (stream->buf_replace_cnt)
	10051	+ return -EINVAL;
	10052	+
	10053	+ stream->dma_en &= ~stream->to_stop_dma;
	10054	+ atomic_inc(&cif_dev->streamoff_cnt);
	10055	+ if (stream->dma_en != 0) {
	10056	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
	10057	+ stream->buf_owner = RKCIF_DMAEN_BY_ISP;
	10058	+ stream->to_stop_dma = 0;
	10059	+ return 0;
	10060	+ }
	10061	+
	10062	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	10063	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY) {
	10064	+ val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
	10065	+ val &= ~CSI_DMA_ENABLE;
	10066	+ if (stream->is_stop_capture) {
	10067	+ val &= ~CSI_ENABLE_CAPTURE;
	10068	+ stream->is_stop_capture = false;
	10069	+ }
	10070	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
	10071	+ } else if (mbus_cfg->type == V4L2_MBUS_CCP2) {
	10072	+ val = rkcif_read_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id));
	10073	+ val &= ~LVDS_DMAEN_RV1106;
	10074	+ if (stream->is_stop_capture) {
	10075	+ val &= ~ENABLE_CAPTURE;
	10076	+ stream->is_stop_capture = false;
	10077	+ }
	10078	+ rkcif_write_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id), val);
	10079	+ } else {
	10080	+ val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
	10081	+ if (cif_dev->chip_id == CHIP_RK3588_CIF)
	10082	+ val &= ~DVP_DMA_EN;
	10083	+ else if (cif_dev->chip_id == CHIP_RV1106_CIF)
	10084	+ val &= ~(DVP_SW_DMA_EN(stream->id));
	10085	+ if (stream->is_stop_capture) {
	10086	+ val &= ~ENABLE_CAPTURE;
	10087	+ stream->is_stop_capture = false;
	10088	+ }
	10089	+ rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
	10090	+ }
	10091	+ stream->to_stop_dma = 0;
	10092	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	10093	+ "stream[%d] replace_cnt %d, y_addr 0x%x, 0x%x\n",
	10094	+ stream->id, stream->buf_replace_cnt,
	10095	+ rkcif_read_register(cif_dev, get_reg_index_of_frm0_y_addr(stream->id)),
	10096	+ rkcif_read_register(cif_dev, get_reg_index_of_frm1_y_addr(stream->id)));
	10097	+ return 0;
	10098	+}
	10099	+
	10100	+static void rkcif_send_sof(struct rkcif_device *cif_dev)
	10101	+{
	10102	+ struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
	10103	+ struct csi2_dev *csi;
	10104	+
	10105	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	10106	+ mbus->type == V4L2_MBUS_CSI2_CPHY) {
	10107	+ csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
	10108	+ rkcif_csi2_event_inc_sof(csi);
	10109	+ } else if (mbus->type == V4L2_MBUS_CCP2) {
	10110	+ rkcif_lvds_event_inc_sof(cif_dev);
	10111	+ } else {
	10112	+ rkcif_dvp_event_inc_sof(cif_dev);
	10113	+ }
	10114	+}
	10115	+
	10116	+static int rkcif_g_toisp_ch(unsigned int intstat_glb, int index)
	10117	+{
	10118	+ if (intstat_glb & TOISP_END_CH0(index))
	10119	+ return RKCIF_TOISP_CH0;
	10120	+ if (intstat_glb & TOISP_END_CH1(index))
	10121	+ return RKCIF_TOISP_CH1;
	10122	+ if (intstat_glb & TOISP_END_CH2(index))
	10123	+ return RKCIF_TOISP_CH2;
	10124	+
	10125	+ return -EINVAL;
	10126	+}
	10127	+
	10128	+static int rkcif_g_toisp_fs(unsigned int intstat_glb, int index)
	10129	+{
	10130	+ if (intstat_glb & TOISP_FS_CH0(index))
	10131	+ return RKCIF_TOISP_CH0;
	10132	+ if (intstat_glb & TOISP_FS_CH1(index))
	10133	+ return RKCIF_TOISP_CH1;
	10134	+ if (intstat_glb & TOISP_FS_CH2(index))
	10135	+ return RKCIF_TOISP_CH2;
	10136	+
	10137	+ return -EINVAL;
	10138	+}
	10139	+
	10140	+static void rkcif_toisp_check_stop_status(struct sditf_priv *priv,
	10141	+ unsigned int intstat_glb,
	10142	+ int index)
	10143	+{
	10144	+ int ch = 0;
	10145	+ struct rkcif_stream *stream;
	10146	+ int src_id = 0;
	10147	+ int i = 0;
	10148	+ u32 val = 0;
	10149	+ u64 cur_time = 0;
	10150	+ int on = 0;
	10151	+
	10152	+ for (i = 0; i < TOISP_CH_MAX; i++) {
	10153	+ ch = rkcif_g_toisp_ch(intstat_glb, index);
	10154	+ if (ch >= 0) {
	10155	+ src_id = priv->toisp_inf.ch_info[ch].id;
	10156	+ if (src_id == 24)
	10157	+ stream = &priv->cif_dev->stream[0];
	10158	+ else
	10159	+ stream = &priv->cif_dev->stream[src_id % 4];
	10160	+ if (stream->stopping) {
	10161	+ v4l2_dbg(3, rkcif_debug, &priv->cif_dev->v4l2_dev,
	10162	+ "stream[%d] stop\n",
	10163	+ stream->id);
	10164	+ rkcif_stream_stop(stream);
	10165	+ stream->stopping = false;
	10166	+ wake_up(&stream->wq_stopped);
	10167	+ }
	10168	+ if (stream->cifdev->sensor_state_change) {
	10169	+ rkcif_dphy_quick_stream(stream->cifdev, on);
	10170	+ stream->cifdev->sensor_work.on = stream->cifdev->sensor_state;
	10171	+ schedule_work(&stream->cifdev->sensor_work.work);
	10172	+ stream->cifdev->sensor_state_change = false;
	10173	+ if (stream->is_wait_stop_complete) {
	10174	+ stream->is_wait_stop_complete = false;
	10175	+ complete(&stream->stop_complete);
	10176	+ }
	10177	+ }
	10178	+ if (stream->is_single_cap && (!stream->cur_skip_frame) &&
	10179	+ (stream->cifdev->hdr.hdr_mode == NO_HDR \|\|
	10180	+ (stream->cifdev->hdr.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	10181	+ (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 2))) {
	10182	+ rkcif_dphy_quick_stream(stream->cifdev, on);
	10183	+ stream->cifdev->sensor_work.on = 0;
	10184	+ schedule_work(&stream->cifdev->sensor_work.work);
	10185	+ stream->is_single_cap = false;
	10186	+ }
	10187	+ if (stream->cur_skip_frame &&
	10188	+ (stream->cifdev->hdr.hdr_mode == NO_HDR \|\|
	10189	+ (stream->cifdev->hdr.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	10190	+ (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 2)))
	10191	+ stream->cur_skip_frame--;
	10192	+ if (stream->cifdev->chip_id >= CHIP_RV1106_CIF)
	10193	+ rkcif_modify_frame_skip_config(stream);
	10194	+ if (stream->cifdev->rdbk_debug &&
	10195	+ stream->frame_idx < 15)
	10196	+ v4l2_info(&priv->cif_dev->v4l2_dev,
	10197	+ "stream[%d] toisp fe %d\n",
	10198	+ stream->id,
	10199	+ stream->frame_idx - 1);
	10200	+
	10201	+ switch (ch) {
	10202	+ case RKCIF_TOISP_CH0:
	10203	+ val = TOISP_END_CH0(index);
	10204	+ intstat_glb = intstat_glb & (~val);
	10205	+ break;
	10206	+ case RKCIF_TOISP_CH1:
	10207	+ val = TOISP_END_CH1(index);
	10208	+ intstat_glb = intstat_glb & (~val);
	10209	+ break;
	10210	+ case RKCIF_TOISP_CH2:
	10211	+ val = TOISP_END_CH2(index);
	10212	+ intstat_glb = intstat_glb & (~val);
	10213	+ break;
	10214	+ default:
	10215	+ break;
	10216	+ }
	10217	+ }
	10218	+ ch = rkcif_g_toisp_fs(intstat_glb, index);
	10219	+ if (ch >= 0) {
	10220	+ src_id = priv->toisp_inf.ch_info[ch].id;
	10221	+ if (src_id == 24)
	10222	+ stream = &priv->cif_dev->stream[0];
	10223	+ else
	10224	+ stream = &priv->cif_dev->stream[src_id % 4];
	10225	+ if (stream->id == 0)
	10226	+ rkcif_send_sof(stream->cifdev);
	10227	+ stream->frame_idx++;
	10228	+ cur_time = rkcif_time_get_ns(stream->cifdev);
	10229	+ stream->readout.readout_time = cur_time - stream->readout.fs_timestamp;
	10230	+ stream->readout.fs_timestamp = cur_time;
	10231	+ stream->buf_wake_up_cnt++;
	10232	+ if (stream->frame_idx % 2)
	10233	+ stream->fps_stats.frm0_timestamp = rkcif_time_get_ns(stream->cifdev);
	10234	+ else
	10235	+ stream->fps_stats.frm1_timestamp = rkcif_time_get_ns(stream->cifdev);
	10236	+ if (stream->cifdev->rdbk_debug &&
	10237	+ stream->frame_idx < 15)
	10238	+ v4l2_info(&priv->cif_dev->v4l2_dev,
	10239	+ "stream[%d] toisp sof seq %d\n",
	10240	+ stream->id,
	10241	+ stream->frame_idx - 1);
	10242	+ if (stream->to_en_dma)
	10243	+ rkcif_enable_dma_capture(stream, false);
	10244	+ if (stream->to_en_scale) {
	10245	+ stream->to_en_scale = false;
	10246	+ rkcif_scale_start(stream->scale_vdev);
	10247	+ }
	10248	+ switch (ch) {
	10249	+ case RKCIF_TOISP_CH0:
	10250	+ val = TOISP_FS_CH0(index);
	10251	+ intstat_glb = intstat_glb & (~val);
	10252	+ break;
	10253	+ case RKCIF_TOISP_CH1:
	10254	+ val = TOISP_FS_CH1(index);
	10255	+ intstat_glb = intstat_glb & (~val);
	10256	+ break;
	10257	+ case RKCIF_TOISP_CH2:
	10258	+ val = TOISP_FS_CH2(index);
	10259	+ intstat_glb = intstat_glb & (~val);
	10260	+ break;
	10261	+ default:
	10262	+ break;
	10263	+ }
	10264	+ }
	10265	+ }
	10266	+}
	10267	+
	10268	+void rkcif_irq_handle_toisp(struct rkcif_device *cif_dev, unsigned int intstat_glb)
	10269	+{
	10270	+ int i = 0;
	10271	+ bool to_check = false;
	10272	+ struct sditf_priv *priv = cif_dev->sditf[0];
	10273	+
	10274	+ if (!priv \|\| priv->mode.rdbk_mode != RKISP_VICAP_ONLINE)
	10275	+ return;
	10276	+
	10277	+ for (i = 0; i < 2; i++) {
	10278	+ if (priv->toisp_inf.link_mode == TOISP0 &&
	10279	+ i == 0) {
	10280	+ to_check = true;
	10281	+ } else if (priv->toisp_inf.link_mode == TOISP1 &&
	10282	+ i == 1) {
	10283	+ to_check = true;
	10284	+ } else if (priv->toisp_inf.link_mode == TOISP_UNITE &&
	10285	+ i == 1) {
	10286	+ to_check = true;
	10287	+ }
	10288	+ if (to_check)
	10289	+ rkcif_toisp_check_stop_status(priv, intstat_glb, i);
	10290	+ }
	10291	+}
	10292	+
	10293	+static int rkcif_check_group_sync_state(struct rkcif_device *cif_dev)
	10294	+{
	10295	+ struct rkcif_stream *detect_stream = &cif_dev->stream[0];
	10296	+ struct rkcif_stream *next_stream = NULL;
	10297	+ struct rkcif_hw *hw = cif_dev->hw_dev;
	10298	+ u64 fs_interval = 0;
	10299	+ int i = 0;
	10300	+ int ret = 0;
	10301	+ struct rkcif_multi_sync_config *sync_config;
	10302	+
	10303	+ sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
	10304	+ sync_config->sync_code \|= BIT(cif_dev->csi_host_idx);
	10305	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	10306	+ "sync code 0x%x, mask 0x%x, update 0x%x, cache 0x%x, timestamp %llu\n",
	10307	+ sync_config->sync_code,
	10308	+ sync_config->sync_mask,
	10309	+ sync_config->update_code,
	10310	+ sync_config->update_cache,
	10311	+ detect_stream->readout.fs_timestamp);
	10312	+
	10313	+ if (sync_config->sync_code != sync_config->sync_mask)
	10314	+ return -EINVAL;
	10315	+
	10316	+ for (i = 0; i < sync_config->dev_cnt; i++) {
	10317	+ if (sync_config->mode == RKCIF_MASTER_MASTER) {
	10318	+ if (i < sync_config->ext_master.count)
	10319	+ next_stream = &sync_config->ext_master.cif_dev[i]->stream
	10320	+ [0];
	10321	+ else
	10322	+ next_stream = &sync_config->int_master.cif_dev[0]->stream
	10323	+ [0];
	10324	+ } else if (sync_config->mode == RKCIF_MASTER_SLAVE) {
	10325	+ if (i < sync_config->slave.count)
	10326	+ next_stream = &sync_config->slave.cif_dev[i]->stream
	10327	+ [0];
	10328	+ else
	10329	+ next_stream = &sync_config->int_master.cif_dev[0]->stream
	10330	+ [0];
	10331	+ } else {
	10332	+ v4l2_err(&cif_dev->v4l2_dev,
	10333	+ "ERROR: invalid group sync mode\n");
	10334	+ ret = -EINVAL;
	10335	+ break;
	10336	+ }
	10337	+ if (detect_stream == next_stream)
	10338	+ continue;
	10339	+ fs_interval = abs(detect_stream->readout.fs_timestamp - next_stream->readout.fs_timestamp);
	10340	+ if (fs_interval > RKCIF_MAX_INTERVAL_NS) {
	10341	+ ret = -EINVAL;
	10342	+ break;
	10343	+ }
	10344	+ }
	10345	+ return ret;
	10346	+}
	10347	+
	10348	+static void rkcif_deal_sof(struct rkcif_device *cif_dev)
	10349	+{
	10350	+ struct rkcif_stream *detect_stream = &cif_dev->stream[0];
	10351	+ struct rkcif_hw *hw = cif_dev->hw_dev;
	10352	+ struct rkcif_device *tmp_dev = NULL;
	10353	+ unsigned long flags;
	10354	+ int i = 0;
	10355	+ int ret = 0;
	10356	+
	10357	+ if (cif_dev->chip_id < CHIP_RK3588_CIF)
	10358	+ detect_stream->fs_cnt_in_single_frame++;
	10359	+ spin_lock_irqsave(&detect_stream->fps_lock, flags);
	10360	+ detect_stream->readout.fs_timestamp = rkcif_time_get_ns(cif_dev);
	10361	+ spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
	10362	+
	10363	+ if (cif_dev->sync_cfg.type != RKCIF_NOSYNC_MODE) {
	10364	+ struct rkcif_multi_sync_config *sync_config;
	10365	+
	10366	+ sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
	10367	+ ret = rkcif_check_group_sync_state(cif_dev);
	10368	+ if (!ret) {
	10369	+ sync_config->sync_code = 0;
	10370	+ sync_config->frame_idx++;
	10371	+ spin_lock_irqsave(&hw->group_lock, flags);
	10372	+ sync_config->update_cache = sync_config->sync_mask;
	10373	+ if (!sync_config->update_code) {
	10374	+ sync_config->update_code = sync_config->update_cache;
	10375	+ sync_config->update_cache = 0;
	10376	+ }
	10377	+ spin_unlock_irqrestore(&hw->group_lock, flags);
	10378	+ for (i = 0; i < sync_config->dev_cnt; i++) {
	10379	+ if (sync_config->mode == RKCIF_MASTER_MASTER) {
	10380	+ if (i < sync_config->ext_master.count)
	10381	+ tmp_dev = sync_config->ext_master.cif_dev[i];
	10382	+ else
	10383	+ tmp_dev = sync_config->int_master.cif_dev[0];
	10384	+ } else if (sync_config->mode == RKCIF_MASTER_SLAVE) {
	10385	+ if (i < sync_config->slave.count)
	10386	+ tmp_dev = sync_config->slave.cif_dev[i];
	10387	+ else
	10388	+ tmp_dev = sync_config->int_master.cif_dev[0];
	10389	+ } else {
	10390	+ v4l2_err(&cif_dev->v4l2_dev,
	10391	+ "ERROR: invalid group sync mode\n");
	10392	+ }
	10393	+ if (tmp_dev) {
	10394	+ rkcif_send_sof(tmp_dev);
	10395	+ tmp_dev->stream[0].frame_idx = sync_config->frame_idx;
	10396	+ }
	10397	+ }
	10398	+ }
	10399	+ } else {
	10400	+ if (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode) {
	10401	+ rkcif_send_sof(cif_dev);
	10402	+ detect_stream->frame_idx++;
	10403	+ }
	10404	+ if (detect_stream->cifdev->rdbk_debug &&
	10405	+ detect_stream->frame_idx < 15 &&
	10406	+ (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode))
	10407	+ v4l2_info(&cif_dev->v4l2_dev,
	10408	+ "stream[%d] sof %d %lld\n",
	10409	+ detect_stream->id,
	10410	+ detect_stream->frame_idx - 1,
	10411	+ rkcif_time_get_ns(cif_dev));
	10412	+ }
	10413	+}
	10414	+
	10415	+unsigned int rkcif_irq_global(struct rkcif_device *cif_dev)
	10416	+{
	10417	+ unsigned int intstat_glb = 0;
	10418	+
	10419	+ intstat_glb = rkcif_read_register(cif_dev, CIF_REG_GLB_INTST);
	10420	+ if (intstat_glb)
	10421	+ v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
	10422	+ "intstat_glb 0x%x\n",
	10423	+ intstat_glb);
	10424	+ else
	10425	+ return intstat_glb;
	10426	+
	10427	+ if (intstat_glb & SCALE_TOISP_AXI0_ERR) {
	10428	+ v4l2_err(&cif_dev->v4l2_dev,
	10429	+ "ERROR: scale channel, AXI0 bus err intstat_glb:0x%x !!\n",
	10430	+ intstat_glb);
	10431	+ return 0;
	10432	+ }
	10433	+ if (intstat_glb & SCALE_TOISP_AXI1_ERR) {
	10434	+ v4l2_err(&cif_dev->v4l2_dev,
	10435	+ "ERROR: scale channel, AXI1 bus err intstat_glb:0x%x !!\n",
	10436	+ intstat_glb);
	10437	+ return 0;
	10438	+ }
	10439	+ rkcif_irq_handle_scale(cif_dev, intstat_glb);
	10440	+ return intstat_glb;
	10441	+}
	10442	+
	10443	+static bool rkcif_check_buffer_prepare(struct rkcif_stream *stream)
	10444	+{
	10445	+ struct rkcif_device *cif_dev = stream->cifdev;
	10446	+ unsigned long flags;
	10447	+ bool is_update = false;
	10448	+ struct rkcif_multi_sync_config *sync_config;
	10449	+
	10450	+ spin_lock_irqsave(&cif_dev->hw_dev->group_lock, flags);
	10451	+ sync_config = &cif_dev->hw_dev->sync_config[cif_dev->sync_cfg.group];
	10452	+ if (stream->id == 0 &&
	10453	+ sync_config->update_code & BIT(cif_dev->csi_host_idx)) {
	10454	+ is_update = true;
	10455	+ sync_config->update_code &= ~(BIT(cif_dev->csi_host_idx));
	10456	+ if (!sync_config->update_code &&
	10457	+ sync_config->update_cache) {
	10458	+ sync_config->update_code = sync_config->update_cache;
	10459	+ sync_config->update_cache = 0;
	10460	+ }
	10461	+ } else {
	10462	+ if (cif_dev->rdbk_buf[RDBK_L])
	10463	+ is_update = true;
	10464	+ }
	10465	+
	10466	+ spin_unlock_irqrestore(&cif_dev->hw_dev->group_lock, flags);
	10467	+ return is_update;
	10468	+}
	10469	+
	10470	+static bool rkcif_check_single_dev_stream_on(struct rkcif_hw *hw)
	10471	+{
	10472	+ struct rkcif_device *cif_dev = NULL;
	10473	+ struct rkcif_stream *stream = NULL;
	10474	+ int i = 0, j = 0;
	10475	+ int stream_cnt = 0;
	10476	+
	10477	+ if (hw->dev_num == 1)
	10478	+ return true;
	10479	+ for (i = 0; i < hw->dev_num; i++) {
	10480	+ cif_dev = hw->cif_dev[i];
	10481	+ for (j = 0; j < RKCIF_MAX_STREAM_MIPI; j++) {
	10482	+ stream = &cif_dev->stream[j];
	10483	+ if (stream->state == RKCIF_STATE_STREAMING \|\|
	10484	+ stream->state == RKCIF_STATE_RESET_IN_STREAMING) {
	10485	+ stream_cnt++;
	10486	+ break;
	10487	+ }
	10488	+ }
	10489	+ }
	10490	+ if (stream_cnt > 1)
	10491	+ return false;
	10492	+ return true;
	10493	+}
	10494	+
	10495	+static void rkcif_get_resmem_head(struct rkcif_device *cif_dev)
	10496	+{
	10497	+ void *resmem_va = phys_to_virt(cif_dev->resmem_pa);
	10498	+ struct rkisp_thunderboot_resmem_head *head = NULL;
	10499	+ int size = 0;
	10500	+ int offset = 0;
	10501	+ int ret = 0;
	10502	+ int cam_idx = 0;
	10503	+ char cam_idx_str[3] = {0};
	10504	+
	10505	+ if (!cif_dev->is_rtt_suspend)
	10506	+ return;
	10507	+ strscpy(cam_idx_str, cif_dev->terminal_sensor.sd->name + 1, 2);
	10508	+ cam_idx_str[2] = '\0';
	10509	+ ret = kstrtoint(cam_idx_str, 0, &cam_idx);
	10510	+ if (ret) {
	10511	+ v4l2_err(&cif_dev->v4l2_dev,
	10512	+ "get camera index fail\n");
	10513	+ return;
	10514	+ }
	10515	+
	10516	+ if (cif_dev->chip_id == CHIP_RV1106_CIF) {
	10517	+ size = sizeof(struct rkisp32_thunderboot_resmem_head);
	10518	+ offset = size * cam_idx;
	10519	+ }
	10520	+ /* currently, thunderboot with mcu only run one camera */
	10521	+ offset = 0;
	10522	+
	10523	+ if (size && size < cif_dev->resmem_size) {
	10524	+ dma_sync_single_for_cpu(cif_dev->dev, cif_dev->resmem_addr + offset,
	10525	+ size, DMA_FROM_DEVICE);
	10526	+ if (cif_dev->chip_id == CHIP_RV1106_CIF) {
	10527	+ struct rkisp32_thunderboot_resmem_head *tmp = resmem_va + offset;
	10528	+
	10529	+ head = &tmp->head;
	10530	+ cif_dev->resume_mode = head->rtt_mode;
	10531	+ cif_dev->nr_buf_size = head->nr_buf_size;
	10532	+ cif_dev->share_mem_size = head->share_mem_size;
	10533	+ cif_dev->thunderboot_sensor_num = head->camera_num;
	10534	+ }
	10535	+ }
	10536	+ v4l2_err(&cif_dev->v4l2_dev,
	10537	+ "get camera index %02x, resume_mode 0x%x, nr_buf_size %d\n",
	10538	+ cam_idx, cif_dev->resume_mode, cif_dev->nr_buf_size);
	10539	+}
	10540	+
	10541	+static int rkcif_subdevs_set_power(struct rkcif_device *cif_dev, int on)
	10542	+{
	10543	+ struct sditf_priv *priv = cif_dev->sditf[0];
	10544	+ int ret = 0;
	10545	+ int i = 0;
	10546	+
	10547	+ if (cif_dev->terminal_sensor.sd)
	10548	+ ret = v4l2_subdev_call(cif_dev->terminal_sensor.sd,
	10549	+ core, s_power, on);
	10550	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	10551	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	10552	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	10553	+ v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core,
	10554	+ s_power, on);
	10555	+ }
	10556	+ }
	10557	+ return ret;
	10558	+}
	10559	+
	10560	+static void rkcif_sensor_quick_streaming_cb(void *data)
	10561	+{
	10562	+ struct v4l2_subdev subdevs = (struct v4l2_subdev )data;
	10563	+ int on = 1;
	10564	+
	10565	+ v4l2_subdev_call(subdevs, core, ioctl,
	10566	+ RKMODULE_SET_QUICK_STREAM, &on);
	10567	+}
	10568	+
	10569	+static int rkcif_subdevs_set_stream(struct rkcif_device *cif_dev, int on)
	10570	+{
	10571	+ struct rkcif_pipeline *p = &cif_dev->pipe;
	10572	+ struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
	10573	+ struct sditf_priv *priv = cif_dev->sditf[0];
	10574	+ int i = 0;
	10575	+ int ret = 0;
	10576	+
	10577	+ for (i = 0; i < p->num_subdevs; i++) {
	10578	+ if (p->subdevs[i] == terminal_sensor->sd && on)
	10579	+ rkcif_set_sof(cif_dev, cif_dev->stream[0].frame_idx);
	10580	+ if (p->subdevs[i] == terminal_sensor->sd &&
	10581	+ cif_dev->chip_id == CHIP_RV1106_CIF) {
	10582	+ if (!rk_tb_mcu_is_done() && on) {
	10583	+ cif_dev->tb_client.data = p->subdevs[i];
	10584	+ cif_dev->tb_client.cb = rkcif_sensor_quick_streaming_cb;
	10585	+ rk_tb_client_register_cb(&cif_dev->tb_client);
	10586	+ } else {
	10587	+ ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
	10588	+ RKMODULE_SET_QUICK_STREAM, &on);
	10589	+ if (ret)
	10590	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10591	+ "%s:quick stream %s subdev:%s failed\n",
	10592	+ __func__, on ? "on" : "off",
	10593	+ p->subdevs[i]->name);
	10594	+ }
	10595	+ } else {
	10596	+ ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
	10597	+ if (ret)
	10598	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10599	+ "%s:stream %s subdev:%s failed\n",
	10600	+ __func__, on ? "on" : "off", p->subdevs[i]->name);
	10601	+ }
	10602	+ }
	10603	+
	10604	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	10605	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	10606	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd) {
	10607	+ ret = v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, video, s_stream, on);
	10608	+ if (ret)
	10609	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10610	+ "%s:stream %s subdev:%s failed\n",
	10611	+ __func__, on ? "on" : "off",
	10612	+ cif_dev->sditf[i]->sensor_sd->name);
	10613	+ }
	10614	+ }
	10615	+ }
	10616	+ return ret;
	10617	+}
	10618	+
	10619	+int rkcif_stream_suspend(struct rkcif_device *cif_dev, int mode)
	10620	+{
	10621	+ struct rkcif_stream *stream = NULL;
	10622	+ struct rkcif_resume_info *resume_info = &cif_dev->reset_work.resume_info;
	10623	+ struct sditf_priv *priv = cif_dev->sditf[0];
	10624	+ int ret = 0;
	10625	+ int i = 0;
	10626	+ int sof_cnt = 0;
	10627	+ int on = 0;
	10628	+ int suspend_cnt = 0;
	10629	+
	10630	+ mutex_lock(&cif_dev->stream_lock);
	10631	+
	10632	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE && mode == RKCIF_RESUME_CIF)
	10633	+ goto out_suspend;
	10634	+
	10635	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	10636	+ stream = &cif_dev->stream[i];
	10637	+
	10638	+ if (stream->state == RKCIF_STATE_STREAMING) {
	10639	+ suspend_cnt++;
	10640	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10641	+ "stream[%d] stopping\n", stream->id);
	10642	+ if (stream->dma_en) {
	10643	+ stream->stopping = true;
	10644	+ ret = wait_event_timeout(stream->wq_stopped,
	10645	+ stream->state != RKCIF_STATE_STREAMING,
	10646	+ msecs_to_jiffies(500));
	10647	+ if (!ret) {
	10648	+ rkcif_stream_stop(stream);
	10649	+ stream->stopping = false;
	10650	+ }
	10651	+ } else {
	10652	+ rkcif_stream_stop(stream);
	10653	+ }
	10654	+
	10655	+ if (stream->id == RKCIF_STREAM_MIPI_ID0) {
	10656	+ sof_cnt = rkcif_get_sof(cif_dev);
	10657	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10658	+ "%s: stream[%d] sync frmid & csi_sof, frm_id:%d, csi_sof:%d\n",
	10659	+ __func__,
	10660	+ stream->id,
	10661	+ stream->frame_idx,
	10662	+ sof_cnt);
	10663	+
	10664	+ resume_info->frm_sync_seq = stream->frame_idx;
	10665	+ }
	10666	+
	10667	+ stream->state = RKCIF_STATE_RESET_IN_STREAMING;
	10668	+ stream->is_fs_fe_not_paired = false;
	10669	+ stream->fs_cnt_in_single_frame = 0;
	10670	+
	10671	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10672	+ "%s stop stream[%d] in streaming, frm_id:%d, csi_sof:%d\n",
	10673	+ __func__, stream->id, stream->frame_idx, rkcif_get_sof(cif_dev));
	10674	+
	10675	+ }
	10676	+ }
	10677	+
	10678	+ if (suspend_cnt == 0)
	10679	+ goto out_suspend;
	10680	+
	10681	+ if (!cif_dev->resume_mode)
	10682	+ rkcif_subdevs_set_power(cif_dev, on);
	10683	+
	10684	+ rkcif_subdevs_set_stream(cif_dev, on);
	10685	+
	10686	+out_suspend:
	10687	+ mutex_unlock(&cif_dev->stream_lock);
	10688	+ return 0;
	10689	+}
	10690	+
	10691	+int rkcif_stream_resume(struct rkcif_device *cif_dev, int mode)
	10692	+{
	10693	+ struct rkcif_stream *stream = NULL;
	10694	+ struct sditf_priv *priv = cif_dev->sditf[0];
	10695	+ struct v4l2_subdev *sd = NULL;
	10696	+ int ret = 0;
	10697	+ int i = 0;
	10698	+ u32 capture_mode = 0;
	10699	+ int on = 1;
	10700	+ int resume_cnt = 0;
	10701	+ unsigned long flags;
	10702	+ bool is_single_dev = false;
	10703	+ bool is_can_be_online = false;
	10704	+ struct rkisp_vicap_mode vicap_mode;
	10705	+
	10706	+ mutex_lock(&cif_dev->stream_lock);
	10707	+
	10708	+ rkcif_get_resmem_head(cif_dev);
	10709	+ is_single_dev = rkcif_check_single_dev_stream_on(cif_dev->hw_dev);
	10710	+ is_can_be_online = rkcif_check_can_be_online(cif_dev);
	10711	+ if (cif_dev->resume_mode == RKISP_RTT_MODE_ONE_FRAME) {
	10712	+ if (cif_dev->is_rtt_suspend) {
	10713	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	10714	+ if (priv)
	10715	+ priv->mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO;
	10716	+ } else {
	10717	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE) {
	10718	+ if (cif_dev->chip_id == CHIP_RV1106_CIF) {
	10719	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	10720	+ priv->mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO;
	10721	+ } else {
	10722	+ capture_mode = RKCIF_STREAM_MODE_TOISP;
	10723	+ }
	10724	+ } else if (priv &&
	10725	+ (priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO \|\|
	10726	+ priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME)) {
	10727	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	10728	+ } else {
	10729	+ capture_mode = RKCIF_STREAM_MODE_CAPTURE;
	10730	+ }
	10731	+ }
	10732	+ } else if (cif_dev->resume_mode == RKISP_RTT_MODE_MULTI_FRAME) {
	10733	+ if (is_single_dev && is_can_be_online) {
	10734	+ capture_mode = RKCIF_STREAM_MODE_TOISP;
	10735	+ if (priv)
	10736	+ priv->mode.rdbk_mode = RKISP_VICAP_ONLINE;
	10737	+ } else {
	10738	+ if (cif_dev->is_thunderboot) {
	10739	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	10740	+ if (priv)
	10741	+ priv->mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO;
	10742	+ } else {
	10743	+ capture_mode = RKCIF_STREAM_MODE_CAPTURE;
	10744	+ if (priv)
	10745	+ priv->mode.rdbk_mode = RKISP_VICAP_RDBK_AIQ;
	10746	+ }
	10747	+ }
	10748	+ } else {
	10749	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	10750	+ capture_mode = RKCIF_STREAM_MODE_TOISP;
	10751	+ else if (priv &&
	10752	+ (priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO \|\|
	10753	+ priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME))
	10754	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	10755	+ else
	10756	+ capture_mode = RKCIF_STREAM_MODE_CAPTURE;
	10757	+ }
	10758	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE && mode == RKCIF_RESUME_CIF)
	10759	+ goto out_resume;
	10760	+
	10761	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	10762	+ stream = &cif_dev->stream[i];
	10763	+ if (stream->state != RKCIF_STATE_RESET_IN_STREAMING)
	10764	+ continue;
	10765	+
	10766	+ stream->fs_cnt_in_single_frame = 0;
	10767	+ if (cif_dev->resume_mode == RKISP_RTT_MODE_ONE_FRAME)
	10768	+ stream->is_single_cap = true;
	10769	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	10770	+ if (!priv \|\| priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AIQ) {
	10771	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	10772	+ if (stream->curr_buf == stream->next_buf) {
	10773	+ if (stream->curr_buf)
	10774	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	10775	+ } else {
	10776	+ if (stream->curr_buf)
	10777	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	10778	+ if (stream->next_buf)
	10779	+ list_add_tail(&stream->next_buf->queue, &stream->buf_head);
	10780	+ }
	10781	+ stream->curr_buf = NULL;
	10782	+ stream->next_buf = NULL;
	10783	+ }
	10784	+ } else {
	10785	+ if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE) {
	10786	+ if (stream->curr_buf_toisp == stream->next_buf_toisp) {
	10787	+ if (stream->curr_buf_toisp)
	10788	+ list_add_tail(&stream->curr_buf_toisp->list, &stream->rx_buf_head);
	10789	+ } else {
	10790	+ if (stream->curr_buf_toisp)
	10791	+ list_add_tail(&stream->curr_buf_toisp->list, &stream->rx_buf_head);
	10792	+ if (stream->next_buf_toisp)
	10793	+ list_add_tail(&stream->next_buf_toisp->list, &stream->rx_buf_head);
	10794	+ }
	10795	+ stream->curr_buf_toisp = NULL;
	10796	+ stream->next_buf_toisp = NULL;
	10797	+ } else {
	10798	+ if (stream->curr_buf_toisp == stream->next_buf_toisp) {
	10799	+ if (stream->curr_buf_toisp)
	10800	+ list_add_tail(&stream->curr_buf_toisp->list, &stream->rx_buf_head);
	10801	+ } else {
	10802	+ if (stream->curr_buf_toisp)
	10803	+ list_add_tail(&stream->curr_buf_toisp->list, &stream->rx_buf_head);
	10804	+ if (stream->next_buf_toisp)
	10805	+ list_add_tail(&stream->next_buf_toisp->list, &stream->rx_buf_head);
	10806	+ }
	10807	+ stream->curr_buf_toisp = NULL;
	10808	+ stream->next_buf_toisp = NULL;
	10809	+ }
	10810	+ }
	10811	+
	10812	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	10813	+
	10814	+ if (priv) {
	10815	+ if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE) {
	10816	+ sditf_change_to_online(priv);
	10817	+ if (cif_dev->resume_mode == RKISP_RTT_MODE_MULTI_FRAME &&
	10818	+ stream->rx_buf_num &&
	10819	+ (priv->hdr_cfg.hdr_mode == NO_HDR \|\|
	10820	+ (priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	10821	+ (priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id == 2)))
	10822	+ rkcif_free_rx_buf(stream, priv->buf_num);
	10823	+ else if (!stream->rx_buf_num &&
	10824	+ ((priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 0) \|\|
	10825	+ (priv->hdr_cfg.hdr_mode == HDR_X3 && (stream->id == 0 \|\| stream->id == 1))))
	10826	+ rkcif_init_rx_buf(stream, 1);
	10827	+ } else {
	10828	+ if (stream->is_single_cap && stream->id == 0) {
	10829	+ vicap_mode = priv->mode;
	10830	+ vicap_mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO_ONE_FRAME;
	10831	+ sd = get_rkisp_sd(priv);
	10832	+ if (sd) {
	10833	+ ret = v4l2_subdev_call(sd, core, ioctl,
	10834	+ RKISP_VICAP_CMD_MODE, &vicap_mode);
	10835	+ if (ret)
	10836	+ v4l2_err(&cif_dev->v4l2_dev,
	10837	+ "set isp work mode rdbk aotu oneframe fail\n");
	10838	+
	10839	+ }
	10840	+ }
	10841	+ sditf_disable_immediately(priv);
	10842	+ if (!stream->rx_buf_num &&
	10843	+ capture_mode == RKCIF_STREAM_MODE_TOISP_RDBK) {
	10844	+ if (cif_dev->resume_mode == RKISP_RTT_MODE_ONE_FRAME)
	10845	+ rkcif_init_rx_buf(stream, 1);
	10846	+ else
	10847	+ rkcif_init_rx_buf(stream, priv->buf_num);
	10848	+ }
	10849	+ }
	10850	+ }
	10851	+
	10852	+ stream->lack_buf_cnt = 0;
	10853	+ if (cif_dev->active_sensor &&
	10854	+ (cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	10855	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	10856	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_CCP2))
	10857	+ ret = rkcif_csi_stream_start(stream, capture_mode);
	10858	+ else
	10859	+ ret = rkcif_stream_start(stream, capture_mode);
	10860	+ if (ret)
	10861	+ v4l2_err(&cif_dev->v4l2_dev, "%s:resume stream[%d] failed\n",
	10862	+ __func__, stream->id);
	10863	+
	10864	+ resume_cnt++;
	10865	+ stream->cur_skip_frame = stream->skip_frame;
	10866	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10867	+ "resume stream[%d], frm_idx:%d, csi_sof:%d\n",
	10868	+ stream->id, stream->frame_idx,
	10869	+ rkcif_get_sof(cif_dev));
	10870	+ }
	10871	+
	10872	+ if (resume_cnt == 0)
	10873	+ goto out_resume;
	10874	+
	10875	+ if (!cif_dev->resume_mode)
	10876	+ rkcif_subdevs_set_power(cif_dev, on);
	10877	+
	10878	+ atomic_set(&cif_dev->streamoff_cnt, 0);
	10879	+ rkcif_subdevs_set_stream(cif_dev, on);
	10880	+
	10881	+ if (cif_dev->chip_id < CHIP_RK3588_CIF)
	10882	+ rkcif_start_luma(&cif_dev->luma_vdev,
	10883	+ cif_dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
	10884	+out_resume:
	10885	+ mutex_unlock(&cif_dev->stream_lock);
	10886	+ return 0;
	10887	+}
	10888	+
	10889	+void rkcif_err_print_work(struct work_struct *work)
	10890	+{
	10891	+ struct rkcif_err_state_work *err_state_work = container_of(work,
	10892	+ struct rkcif_err_state_work,
	10893	+ work);
	10894	+ struct rkcif_device *dev = container_of(err_state_work,
	10895	+ struct rkcif_device,
	10896	+ err_state_work);
	10897	+ u32 err_state = 0;
	10898	+ int intstat = 0;
	10899	+ int lastline = 0;
	10900	+ int lastpixel = 0;
	10901	+ u64 cur_time = 0;
	10902	+ bool is_print = false;
	10903	+
	10904	+ cur_time = rkcif_time_get_ns(dev);
	10905	+ if (err_state_work->last_timestamp == 0) {
	10906	+ is_print = true;
	10907	+ } else {
	10908	+ if (cur_time - err_state_work->last_timestamp > 500000000)
	10909	+ is_print = true;
	10910	+ }
	10911	+ err_state_work->last_timestamp = cur_time;
	10912	+ err_state = err_state_work->err_state;
	10913	+ intstat = err_state_work->intstat;
	10914	+ lastline = err_state_work->lastline;
	10915	+ lastpixel = err_state_work->lastpixel;
	10916	+ if (err_state & RKCIF_ERR_ID0_NOT_BUF && is_print)
	10917	+ v4l2_err(&dev->v4l2_dev,
	10918	+ "stream[0] not active buffer, frame num %d, cnt %llu\n",
	10919	+ dev->stream[0].frame_idx, dev->irq_stats.not_active_buf_cnt[0]);
	10920	+ if (err_state & RKCIF_ERR_ID1_NOT_BUF && is_print)
	10921	+ v4l2_err(&dev->v4l2_dev,
	10922	+ "stream[1] not active buffer, frame num %d, cnt %llu\n",
	10923	+ dev->stream[1].frame_idx, dev->irq_stats.not_active_buf_cnt[1]);
	10924	+ if (err_state & RKCIF_ERR_ID2_NOT_BUF && is_print)
	10925	+ v4l2_err(&dev->v4l2_dev,
	10926	+ "stream[2] not active buffer, frame num %d, cnt %llu\n",
	10927	+ dev->stream[2].frame_idx, dev->irq_stats.not_active_buf_cnt[2]);
	10928	+ if (err_state & RKCIF_ERR_ID3_NOT_BUF && is_print)
	10929	+ v4l2_err(&dev->v4l2_dev,
	10930	+ "stream[3] not active buffer, frame num %d, cnt %llu\n",
	10931	+ dev->stream[3].frame_idx, dev->irq_stats.not_active_buf_cnt[3]);
	10932	+ if (err_state & RKCIF_ERR_ID0_TRIG_SIMULT && is_print)
	10933	+ v4l2_err(&dev->v4l2_dev,
	10934	+ "stream[0], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	10935	+ dev->stream[0].frame_idx, dev->irq_stats.trig_simult_cnt[0]);
	10936	+ if (err_state & RKCIF_ERR_ID1_TRIG_SIMULT && is_print)
	10937	+ v4l2_err(&dev->v4l2_dev,
	10938	+ "stream[1], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	10939	+ dev->stream[1].frame_idx, dev->irq_stats.trig_simult_cnt[1]);
	10940	+ if (err_state & RKCIF_ERR_ID2_TRIG_SIMULT && is_print)
	10941	+ v4l2_err(&dev->v4l2_dev,
	10942	+ "stream[2], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	10943	+ dev->stream[2].frame_idx, dev->irq_stats.trig_simult_cnt[2]);
	10944	+ if (err_state & RKCIF_ERR_ID3_TRIG_SIMULT && is_print)
	10945	+ v4l2_err(&dev->v4l2_dev,
	10946	+ "stream[3], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	10947	+ dev->stream[3].frame_idx, dev->irq_stats.trig_simult_cnt[3]);
	10948	+ if (err_state & RKCIF_ERR_SIZE) {
	10949	+ if (dev->chip_id >= CHIP_RK3588_CIF)
	10950	+ v4l2_err(&dev->v4l2_dev,
	10951	+ "ERROR: csi size err, intstat:0x%x, size:0x%x,0x%x,0x%x,0x%x, cnt %llu\n",
	10952	+ intstat, err_state_work->size_id0, err_state_work->size_id1,
	10953	+ err_state_work->size_id2, err_state_work->size_id3,
	10954	+ dev->irq_stats.csi_size_err_cnt);
	10955	+ else
	10956	+ v4l2_err(&dev->v4l2_dev,
	10957	+ "ERROR: csi size err, intstat:0x%x, lastline:0x%x, cnt %llu\n",
	10958	+ intstat, lastline, dev->irq_stats.csi_size_err_cnt);
	10959	+ }
	10960	+ if (err_state & RKCIF_ERR_OVERFLOW)
	10961	+ v4l2_err(&dev->v4l2_dev,
	10962	+ "ERROR: csi fifo overflow, intstat:0x%x, lastline:0x%x, cnt %llu\n",
	10963	+ intstat, lastline, dev->irq_stats.csi_overflow_cnt);
	10964	+ if (err_state & RKCIF_ERR_BANDWIDTH_LACK)
	10965	+ v4l2_err(&dev->v4l2_dev,
	10966	+ "ERROR: csi bandwidth lack, intstat:0x%x, lastline:0x%x, cnt %llu\n",
	10967	+ intstat, lastline, dev->irq_stats.csi_bwidth_lack_cnt);
	10968	+ if (err_state & RKCIF_ERR_ID0_MULTI_FS)
	10969	+ v4l2_err(&dev->v4l2_dev,
	10970	+ "ERR: multi fs in oneframe in id0, fs_num:%u\n",
	10971	+ dev->stream[0].fs_cnt_in_single_frame);
	10972	+ if (err_state & RKCIF_ERR_BUS)
	10973	+ v4l2_err(&dev->v4l2_dev, "dvp bus err, intstat 0x%x, last line 0x%x\n",
	10974	+ intstat, lastline);
	10975	+ if (err_state & RKCIF_ERR_PIXEL)
	10976	+ v4l2_err(&dev->v4l2_dev, "dvp pix err, intstat 0x%x, last pixel 0x%x\n",
	10977	+ intstat, lastpixel);
	10978	+ if (err_state & RKCIF_ERR_LINE)
	10979	+ v4l2_err(&dev->v4l2_dev, "dvp line err, intstat 0x%x, last line 0x%x\n",
	10980	+ intstat, lastline);
	10981	+}
	10982	+
	10983	+/* pingpong irq for rk3588 and next */
	10984	+void rkcif_irq_pingpong_v1(struct rkcif_device *cif_dev)
	10985	+{
	10986	+ struct rkcif_stream *stream;
	10987	+ struct rkcif_stream *detect_stream = &cif_dev->stream[0];
	10988	+ struct v4l2_mbus_config *mbus;
	10989	+ unsigned int intstat, i = 0xff;
	10990	+ unsigned long flags;
	10991	+ bool is_update = false;
	10992	+ int ret = 0;
	10993	+ int on = 0;
	10994	+
	10995	+ if (!cif_dev->active_sensor)
	10996	+ return;
	10997	+
	10998	+ mbus = &cif_dev->active_sensor->mbus;
	10999	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	11000	+ mbus->type == V4L2_MBUS_CSI2_CPHY \|\|
	11001	+ mbus->type == V4L2_MBUS_CCP2) {
	11002	+ int mipi_id;
	11003	+ u32 lastline = 0;
	11004	+
	11005	+ intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
	11006	+ lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
	11007	+ cif_dev->err_state_work.lastline = lastline;
	11008	+ cif_dev->err_state_work.intstat = intstat;
	11009	+
	11010	+ /* clear all interrupts that has been triggered */
	11011	+ if (intstat) {
	11012	+ rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
	11013	+ v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
	11014	+ "intstat 0x%x\n", intstat);
	11015	+ } else {
	11016	+ return;
	11017	+ }
	11018	+
	11019	+ if (intstat & CSI_SIZE_ERR) {
	11020	+ if (cif_dev->chip_id >= CHIP_RK3588_CIF) {
	11021	+ cif_dev->err_state_work.size_id0 = rkcif_read_register(cif_dev,
	11022	+ CIF_REG_MIPI_FRAME_SIZE_ID0);
	11023	+ cif_dev->err_state_work.size_id1 = rkcif_read_register(cif_dev,
	11024	+ CIF_REG_MIPI_FRAME_SIZE_ID1);
	11025	+ cif_dev->err_state_work.size_id2 = rkcif_read_register(cif_dev,
	11026	+ CIF_REG_MIPI_FRAME_SIZE_ID2);
	11027	+ cif_dev->err_state_work.size_id3 = rkcif_read_register(cif_dev,
	11028	+ CIF_REG_MIPI_FRAME_SIZE_ID3);
	11029	+ }
	11030	+ cif_dev->irq_stats.csi_size_err_cnt++;
	11031	+ cif_dev->err_state \|= RKCIF_ERR_SIZE;
	11032	+ rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
	11033	+ return;
	11034	+ }
	11035	+
	11036	+ if (intstat & CSI_FIFO_OVERFLOW_V1) {
	11037	+ cif_dev->irq_stats.csi_overflow_cnt++;
	11038	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
	11039	+ return;
	11040	+ }
	11041	+
	11042	+ if (intstat & CSI_BANDWIDTH_LACK_V1 &&
	11043	+ cif_dev->intr_mask & CSI_BANDWIDTH_LACK_V1) {
	11044	+ cif_dev->irq_stats.csi_bwidth_lack_cnt++;
	11045	+ cif_dev->err_state \|= RKCIF_ERR_BANDWIDTH_LACK;
	11046	+ if (cif_dev->irq_stats.csi_bwidth_lack_cnt > 10) {
	11047	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN, ~(CSI_BANDWIDTH_LACK_V1));
	11048	+ cif_dev->intr_mask &= ~(CSI_BANDWIDTH_LACK_V1);
	11049	+ schedule_delayed_work(&cif_dev->work_deal_err, msecs_to_jiffies(1000));
	11050	+ }
	11051	+ }
	11052	+
	11053	+ if (intstat & CSI_ALL_ERROR_INTEN_V1) {
	11054	+ cif_dev->irq_stats.all_err_cnt++;
	11055	+ return;
	11056	+ }
	11057	+
	11058	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	11059	+ mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
	11060	+ intstat);
	11061	+ if (mipi_id < 0)
	11062	+ continue;
	11063	+
	11064	+ stream = &cif_dev->stream[mipi_id];
	11065	+ if (!cif_dev->sditf[0] \|\|
	11066	+ cif_dev->sditf[0]->mode.rdbk_mode)
	11067	+ stream->buf_wake_up_cnt++;
	11068	+
	11069	+ if (stream->stopping && (!stream->dma_en)) {
	11070	+ rkcif_stream_stop(stream);
	11071	+ stream->stopping = false;
	11072	+ wake_up(&stream->wq_stopped);
	11073	+ continue;
	11074	+ }
	11075	+
	11076	+ if (stream->state != RKCIF_STATE_STREAMING)
	11077	+ continue;
	11078	+ stream->is_in_vblank = true;
	11079	+ switch (mipi_id) {
	11080	+ case RKCIF_STREAM_MIPI_ID0:
	11081	+ stream->frame_phase = SW_FRM_END_ID0(intstat);
	11082	+ intstat &= ~CSI_FRAME_END_ID0;
	11083	+ break;
	11084	+ case RKCIF_STREAM_MIPI_ID1:
	11085	+ stream->frame_phase = SW_FRM_END_ID1(intstat);
	11086	+ intstat &= ~CSI_FRAME_END_ID1;
	11087	+ break;
	11088	+ case RKCIF_STREAM_MIPI_ID2:
	11089	+ stream->frame_phase = SW_FRM_END_ID2(intstat);
	11090	+ intstat &= ~CSI_FRAME_END_ID2;
	11091	+ break;
	11092	+ case RKCIF_STREAM_MIPI_ID3:
	11093	+ stream->frame_phase = SW_FRM_END_ID3(intstat);
	11094	+ intstat &= ~CSI_FRAME_END_ID3;
	11095	+ break;
	11096	+ }
	11097	+ if (stream->cifdev->rdbk_debug &&
	11098	+ stream->frame_idx < 15 &&
	11099	+ (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode))
	11100	+ v4l2_info(&cif_dev->v4l2_dev,
	11101	+ "stream[%d] fe %d, phase %d, %lld\n",
	11102	+ stream->id,
	11103	+ stream->frame_idx - 1,
	11104	+ stream->frame_phase,
	11105	+ rkcif_time_get_ns(cif_dev));
	11106	+ if (stream->is_finish_stop_dma && stream->is_wait_dma_stop) {
	11107	+ stream->is_wait_dma_stop = false;
	11108	+ wake_up(&stream->wq_stopped);
	11109	+ stream->is_finish_stop_dma = false;
	11110	+ continue;
	11111	+ }
	11112	+
	11113	+ if (stream->is_finish_stop_dma && stream->is_wait_stop_complete) {
	11114	+ stream->is_finish_stop_dma = false;
	11115	+ stream->is_wait_stop_complete = false;
	11116	+ complete(&stream->stop_complete);
	11117	+ }
	11118	+
	11119	+ if (stream->crop_dyn_en)
	11120	+ rkcif_dynamic_crop(stream);
	11121	+
	11122	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	11123	+ if (cif_dev->sync_cfg.type == RKCIF_NOSYNC_MODE)
	11124	+ is_update = true;
	11125	+ else
	11126	+ is_update = rkcif_check_buffer_prepare(stream);
	11127	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	11128	+ "dma capture by vicap, is_updata %d, group mode %d, dma_en %d\n",
	11129	+ is_update, cif_dev->sync_cfg.type, stream->dma_en);
	11130	+ if (is_update)
	11131	+ rkcif_update_stream(cif_dev, stream, mipi_id);
	11132	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	11133	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	11134	+ "dma capture by isp, dma_en 0x%x\n",
	11135	+ stream->dma_en);
	11136	+ rkcif_update_stream_toisp(cif_dev, stream, mipi_id);
	11137	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT) {
	11138	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	11139	+ "dma capture by rockit, dma_en 0x%x\n",
	11140	+ stream->dma_en);
	11141	+ rkcif_update_stream_rockit(cif_dev, stream, mipi_id);
	11142	+ }
	11143	+ if (stream->is_single_cap && !stream->cur_skip_frame) {
	11144	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
	11145	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	11146	+ else if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
	11147	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	11148	+ else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT)
	11149	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ROCKIT;
	11150	+ rkcif_stop_dma_capture(stream);
	11151	+ stream->is_single_cap = false;
	11152	+ if ((cif_dev->hdr.hdr_mode == NO_HDR && atomic_read(&cif_dev->streamoff_cnt) == 1) \|\|
	11153	+ (cif_dev->hdr.hdr_mode == HDR_X2 && atomic_read(&cif_dev->streamoff_cnt) == 2) \|\|
	11154	+ (cif_dev->hdr.hdr_mode == HDR_X3 && atomic_read(&cif_dev->streamoff_cnt) == 3)) {
	11155	+ rkcif_dphy_quick_stream(stream->cifdev, on);
	11156	+ cif_dev->sensor_work.on = 0;
	11157	+ schedule_work(&cif_dev->sensor_work.work);
	11158	+ }
	11159	+ }
	11160	+
	11161	+ if (stream->cur_skip_frame)
	11162	+ stream->cur_skip_frame--;
	11163	+
	11164	+ if (cif_dev->chip_id >= CHIP_RV1106_CIF)
	11165	+ rkcif_modify_frame_skip_config(stream);
	11166	+ if (stream->is_change_toisp) {
	11167	+ stream->is_change_toisp = false;
	11168	+ if ((cif_dev->hdr.hdr_mode == HDR_X2 && stream->id != 1) \|\|
	11169	+ (cif_dev->hdr.hdr_mode == HDR_X3 && stream->id != 2))
	11170	+ rkcif_release_unnecessary_buf_for_online(stream,
	11171	+ stream->curr_buf_toisp);
	11172	+ else
	11173	+ sditf_change_to_online(cif_dev->sditf[0]);
	11174	+ }
	11175	+
	11176	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	11177	+ if (!(stream->cur_stream_mode & RKCIF_STREAM_MODE_TOISP) &&
	11178	+ stream->lack_buf_cnt == 2) {
	11179	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	11180	+ rkcif_stop_dma_capture(stream);
	11181	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	11182	+ "stream[%d] to stop dma, lack_buf_cnt %d\n",
	11183	+ stream->id, stream->lack_buf_cnt);
	11184	+ }
	11185	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	11186	+ if (stream->to_en_scale) {
	11187	+ stream->to_en_scale = false;
	11188	+ rkcif_scale_start(stream->scale_vdev);
	11189	+ }
	11190	+ rkcif_detect_wake_up_mode_change(stream);
	11191	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	11192	+ mipi_id == RKCIF_STREAM_MIPI_ID0) {
	11193	+ if ((intstat & (CSI_FRAME1_START_ID0 \| CSI_FRAME0_START_ID0)) == 0 &&
	11194	+ detect_stream->fs_cnt_in_single_frame > 1) {
	11195	+ cif_dev->err_state \|= RKCIF_ERR_ID0_MULTI_FS;
	11196	+ detect_stream->is_fs_fe_not_paired = true;
	11197	+ detect_stream->fs_cnt_in_single_frame = 0;
	11198	+ } else {
	11199	+ detect_stream->fs_cnt_in_single_frame--;
	11200	+ }
	11201	+ }
	11202	+ rkcif_monitor_reset_event(cif_dev);
	11203	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
	11204	+ }
	11205	+
	11206	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	11207	+ if (intstat & CSI_START_INTSTAT(i)) {
	11208	+ stream = &cif_dev->stream[i];
	11209	+ if (i == 0) {
	11210	+ if (!stream->cur_skip_frame)
	11211	+ rkcif_deal_sof(cif_dev);
	11212	+ } else {
	11213	+ spin_lock_irqsave(&stream->fps_lock, flags);
	11214	+ stream->readout.fs_timestamp = rkcif_time_get_ns(cif_dev);
	11215	+ stream->frame_idx++;
	11216	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	11217	+ }
	11218	+ stream->is_in_vblank = false;
	11219	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	11220	+ if (stream->stopping && stream->dma_en) {
	11221	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
	11222	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	11223	+ else if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
	11224	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	11225	+ stream->is_stop_capture = true;
	11226	+ }
	11227	+ if (stream->to_stop_dma) {
	11228	+ ret = rkcif_stop_dma_capture(stream);
	11229	+ if (!ret)
	11230	+ stream->is_finish_stop_dma = true;
	11231	+ }
	11232	+ if (stream->to_en_dma)
	11233	+ rkcif_enable_dma_capture(stream, false);
	11234	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	11235	+ }
	11236	+ if (intstat & CSI_LINE_INTSTAT_V1(i)) {
	11237	+ stream = &cif_dev->stream[i];
	11238	+ if (stream->is_line_inten) {
	11239	+ stream->line_int_cnt++;
	11240	+ if (cif_dev->rdbk_debug > 1 &&
	11241	+ stream->frame_idx < 15)
	11242	+ v4l2_info(&cif_dev->v4l2_dev,
	11243	+ "line int %lld\n",
	11244	+ stream->line_int_cnt);
	11245	+ if (cif_dev->sditf[0] && (cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO \|\|
	11246	+ cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME))
	11247	+ rkcif_line_wake_up_rdbk(stream, stream->id);
	11248	+ else
	11249	+ rkcif_line_wake_up(stream, stream->id);
	11250	+ rkcif_modify_line_int(stream, false);
	11251	+ stream->is_line_inten = false;
	11252	+ }
	11253	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	11254	+ "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
	11255	+ }
	11256	+ }
	11257	+ } else {
	11258	+ struct rkcif_stream *stream;
	11259	+ int ch_id;
	11260	+ int lastline;
	11261	+
	11262	+ intstat = rkcif_read_register(cif_dev, CIF_REG_DVP_INTSTAT);
	11263	+ if (intstat)
	11264	+ rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, intstat);
	11265	+ else
	11266	+ return;
	11267	+ lastline = rkcif_read_register(cif_dev, CIF_REG_DVP_LINE_CNT);
	11268	+ cif_dev->err_state_work.lastline = lastline;
	11269	+ cif_dev->err_state_work.intstat = intstat;
	11270	+ stream = &cif_dev->stream[RKCIF_STREAM_CIF];
	11271	+
	11272	+ if (intstat & DVP_SIZE_ERR) {
	11273	+ cif_dev->irq_stats.dvp_size_err_cnt++;
	11274	+ rkcif_write_register_or(cif_dev, CIF_REG_DVP_CTRL, 0x000A0000);
	11275	+ cif_dev->err_state \|= RKCIF_ERR_SIZE;
	11276	+ }
	11277	+
	11278	+ if (intstat & DVP_FIFO_OVERFLOW) {
	11279	+ cif_dev->irq_stats.dvp_overflow_cnt++;
	11280	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
	11281	+ }
	11282	+
	11283	+ if (intstat & DVP_BANDWIDTH_LACK) {
	11284	+ cif_dev->irq_stats.dvp_bwidth_lack_cnt++;
	11285	+ cif_dev->err_state \|= RKCIF_ERR_BANDWIDTH_LACK;
	11286	+ }
	11287	+
	11288	+ if (intstat & INTSTAT_ERR_RK3588) {
	11289	+ cif_dev->irq_stats.all_err_cnt++;
	11290	+ }
	11291	+
	11292	+ for (i = 0; i < RKCIF_MAX_STREAM_DVP; i++) {
	11293	+ ch_id = rkcif_dvp_g_ch_id_by_fe(&cif_dev->v4l2_dev, intstat);
	11294	+
	11295	+ if (ch_id < 0)
	11296	+ continue;
	11297	+
	11298	+ stream = &cif_dev->stream[ch_id];
	11299	+ if (!cif_dev->sditf[0] \|\|
	11300	+ cif_dev->sditf[0]->mode.rdbk_mode)
	11301	+ stream->buf_wake_up_cnt++;
	11302	+
	11303	+ if (stream->stopping) {
	11304	+ rkcif_stream_stop(stream);
	11305	+ stream->stopping = false;
	11306	+ wake_up(&stream->wq_stopped);
	11307	+ continue;
	11308	+ }
	11309	+
	11310	+ if (stream->state != RKCIF_STATE_STREAMING)
	11311	+ continue;
	11312	+ stream->is_in_vblank = true;
	11313	+ switch (ch_id) {
	11314	+ case RKCIF_STREAM_MIPI_ID0:
	11315	+ stream->frame_phase = SW_FRM_END_ID0(intstat);
	11316	+ intstat &= ~DVP_ALL_END_ID0;
	11317	+ break;
	11318	+ case RKCIF_STREAM_MIPI_ID1:
	11319	+ stream->frame_phase = SW_FRM_END_ID1(intstat);
	11320	+ intstat &= ~DVP_ALL_END_ID1;
	11321	+ break;
	11322	+ case RKCIF_STREAM_MIPI_ID2:
	11323	+ stream->frame_phase = SW_FRM_END_ID2(intstat);
	11324	+ intstat &= ~DVP_ALL_END_ID2;
	11325	+ break;
	11326	+ case RKCIF_STREAM_MIPI_ID3:
	11327	+ stream->frame_phase = SW_FRM_END_ID3(intstat);
	11328	+ intstat &= ~DVP_ALL_END_ID3;
	11329	+ break;
	11330	+ }
	11331	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	11332	+ if (cif_dev->sync_cfg.type == RKCIF_NOSYNC_MODE)
	11333	+ is_update = true;
	11334	+ else
	11335	+ is_update = rkcif_check_buffer_prepare(stream);
	11336	+ if (is_update)
	11337	+ rkcif_update_stream(cif_dev, stream, ch_id);
	11338	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	11339	+ rkcif_update_stream_toisp(cif_dev, stream, ch_id);
	11340	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT) {
	11341	+ rkcif_update_stream_rockit(cif_dev, stream, ch_id);
	11342	+ }
	11343	+
	11344	+ if (stream->to_en_dma)
	11345	+ rkcif_enable_dma_capture(stream, false);
	11346	+ if (stream->to_stop_dma) {
	11347	+ rkcif_stop_dma_capture(stream);
	11348	+ wake_up(&stream->wq_stopped);
	11349	+ }
	11350	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
	11351	+ }
	11352	+
	11353	+ if (intstat & DVP_FRAME0_START_ID0 \|\| intstat & DVP_FRAME1_START_ID0) {
	11354	+ stream->is_in_vblank = false;
	11355	+ if (!stream->cur_skip_frame)
	11356	+ rkcif_deal_sof(cif_dev);
	11357	+ }
	11358	+
	11359	+ if (stream->crop_dyn_en)
	11360	+ rkcif_dynamic_crop(stream);
	11361	+ }
	11362	+}
	11363	+
6072	11364	void rkcif_irq_pingpong(struct rkcif_device *cif_dev)
6073	11365	{
6074	11366	struct rkcif_stream *stream;
6075	11367	struct rkcif_stream *detect_stream = &cif_dev->stream[0];
6076	11368	struct v4l2_mbus_config *mbus;
6077		- unsigned int intstat = 0x0, i = 0xff, bak_intstat = 0x0;
	11369	+ unsigned int intstat = 0x0, i = 0xff;
6078	11370	unsigned long flags;
6079	11371	int ret = 0;
6080	11372
..	..	@@ -6082,7 +11374,8 @@
6082	11374	return;
6083	11375
6084	11376	mbus = &cif_dev->active_sensor->mbus;
6085		- if ((mbus->type == V4L2_MBUS_CSI2 \|\|
	11377	+ if ((mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	11378	+ mbus->type == V4L2_MBUS_CSI2_CPHY \|\|
6086	11379	mbus->type == V4L2_MBUS_CCP2) &&
6087	11380	(cif_dev->chip_id == CHIP_RK1808_CIF \|\|
6088	11381	cif_dev->chip_id == CHIP_RV1126_CIF \|\|
..	..	@@ -6092,78 +11385,27 @@
6092	11385
6093	11386	intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
6094	11387	lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
	11388	+ cif_dev->err_state_work.lastline = lastline;
	11389	+ cif_dev->err_state_work.intstat = intstat;
6095	11390
6096	11391	/* clear all interrupts that has been triggered */
6097	11392	rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
6098	11393
6099	11394	if (intstat & CSI_FIFO_OVERFLOW) {
6100	11395	cif_dev->irq_stats.csi_overflow_cnt++;
6101		- v4l2_err(&cif_dev->v4l2_dev,
6102		- "ERROR: csi fifo overflow, intstat:0x%x, lastline:%d!!\n",
6103		- intstat, lastline);
6104		- return;
	11396	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
6105	11397	}
6106	11398
6107	11399	if (intstat & CSI_BANDWIDTH_LACK) {
6108	11400	cif_dev->irq_stats.csi_bwidth_lack_cnt++;
6109		- v4l2_err(&cif_dev->v4l2_dev,
6110		- "ERROR: csi bandwidth lack, intstat:0x%x!!\n",
6111		- intstat);
	11401	+ cif_dev->err_state \|= RKCIF_ERR_BANDWIDTH_LACK;
6112	11402	return;
6113	11403	}
6114	11404
6115	11405	if (intstat & CSI_ALL_ERROR_INTEN) {
6116	11406	cif_dev->irq_stats.all_err_cnt++;
6117		- v4l2_err(&cif_dev->v4l2_dev,
6118		- "ERROR: CSI_ALL_ERROR_INTEN:0x%x!!\n", intstat);
6119	11407	return;
6120	11408	}
6121		-
6122		- if ((intstat & (CSI_FRAME0_START_ID0 \| CSI_FRAME1_START_ID0)) ==
6123		- (CSI_FRAME0_START_ID0 \| CSI_FRAME1_START_ID0)) {
6124		- v4l2_err(&cif_dev->v4l2_dev, "%s:ERR: double fs in one fs int\n",
6125		- __func__);
6126		- }
6127		-
6128		- if (intstat & CSI_FRAME0_START_ID0) {
6129		- if (mbus->type == V4L2_MBUS_CSI2)
6130		- rkcif_csi2_event_inc_sof();
6131		- else if (mbus->type == V4L2_MBUS_CCP2)
6132		- rkcif_lvds_event_inc_sof(cif_dev);
6133		- detect_stream->fs_cnt_in_single_frame++;
6134		- spin_lock_irqsave(&detect_stream->fps_lock, flags);
6135		- detect_stream->readout.fs_timestamp = ktime_get_ns();
6136		- spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
6137		- }
6138		-
6139		- if (intstat & CSI_FRAME1_START_ID0) {
6140		- if (mbus->type == V4L2_MBUS_CSI2)
6141		- rkcif_csi2_event_inc_sof();
6142		- else if (mbus->type == V4L2_MBUS_CCP2)
6143		- rkcif_lvds_event_inc_sof(cif_dev);
6144		- detect_stream->fs_cnt_in_single_frame++;
6145		- spin_lock_irqsave(&detect_stream->fps_lock, flags);
6146		- detect_stream->readout.fs_timestamp = ktime_get_ns();
6147		- spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
6148		- }
6149		- for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
6150		- if (intstat & CSI_LINE_INTSTAT(i)) {
6151		- stream = &cif_dev->stream[i];
6152		- if (stream->is_line_inten) {
6153		- stream->line_int_cnt++;
6154		- rkcif_line_wake_up(stream, stream->id);
6155		- rkcif_modify_line_int(stream, false);
6156		- stream->is_line_inten = false;
6157		- }
6158		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
6159		- "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
6160		- }
6161		- }
6162		-
6163		- /* if do not reach frame dma end, return irq */
6164		- mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev, intstat);
6165		- if (mipi_id < 0)
6166		- return;
6167	11409
6168	11410	for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
6169	11411	mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
..	..	@@ -6206,22 +11448,45 @@
6206	11448
6207	11449	rkcif_update_stream(cif_dev, stream, mipi_id);
6208	11450	rkcif_detect_wake_up_mode_change(stream);
	11451	+ rkcif_monitor_reset_event(cif_dev);
6209	11452	if (mipi_id == RKCIF_STREAM_MIPI_ID0) {
6210	11453	if ((intstat & (CSI_FRAME1_START_ID0 \| CSI_FRAME0_START_ID0)) == 0 &&
6211	11454	detect_stream->fs_cnt_in_single_frame > 1) {
6212		- v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
6213		- "%s ERR: multi fs in oneframe, bak_int:0x%x, fs_num:%u\n",
6214		- __func__,
6215		- bak_intstat,
6216		- detect_stream->fs_cnt_in_single_frame);
	11455	+ cif_dev->err_state \|= RKCIF_ERR_ID0_MULTI_FS;
6217	11456	detect_stream->is_fs_fe_not_paired = true;
6218	11457	detect_stream->fs_cnt_in_single_frame = 0;
6219	11458	} else {
6220	11459	detect_stream->fs_cnt_in_single_frame--;
6221	11460	}
6222	11461	}
	11462	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
6223	11463	}
6224		- cif_dev->irq_stats.all_frm_end_cnt++;
	11464	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	11465	+ if (intstat & CSI_START_INTSTAT(i)) {
	11466	+ stream = &cif_dev->stream[i];
	11467	+ if (i == 0) {
	11468	+ if (!stream->cur_skip_frame)
	11469	+ rkcif_deal_sof(cif_dev);
	11470	+ } else {
	11471	+ spin_lock_irqsave(&stream->fps_lock, flags);
	11472	+ stream->readout.fs_timestamp = rkcif_time_get_ns(cif_dev);
	11473	+ stream->frame_idx++;
	11474	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	11475	+ }
	11476	+ stream->is_in_vblank = false;
	11477	+ }
	11478	+ if (intstat & CSI_LINE_INTSTAT(i)) {
	11479	+ stream = &cif_dev->stream[i];
	11480	+ if (stream->is_line_inten) {
	11481	+ stream->line_int_cnt++;
	11482	+ rkcif_line_wake_up(stream, stream->id);
	11483	+ rkcif_modify_line_int(stream, false);
	11484	+ stream->is_line_inten = false;
	11485	+ }
	11486	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	11487	+ "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
	11488	+ }
	11489	+ }
6225	11490	} else {
6226	11491	u32 lastline, lastpix, ctl;
6227	11492	u32 cif_frmst, frmid, int_en;
..	..	@@ -6235,49 +11500,36 @@
6235	11500	lastpix = rkcif_read_register(cif_dev, CIF_REG_DVP_LAST_PIX);
6236	11501	lastpix = CIF_FETCH_Y_LAST_LINE(lastpix);
6237	11502	ctl = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
	11503	+ cif_dev->err_state_work.lastline = lastline;
	11504	+ cif_dev->err_state_work.lastpixel = lastpix;
	11505	+ cif_dev->err_state_work.intstat = intstat;
6238	11506
6239	11507	rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, intstat);
6240	11508
6241	11509	stream = &cif_dev->stream[RKCIF_STREAM_CIF];
6242	11510
6243		- if ((intstat & LINE_INT_END) && !(intstat & FRAME_END) &&
6244		- (cif_dev->dvp_sof_in_oneframe == 0)) {
6245		- if ((intstat & (PRE_INF_FRAME_END \| PST_INF_FRAME_END)) == 0x0) {
6246		- if ((intstat & INTSTAT_ERR) == 0x0) {
6247		- rkcif_dvp_event_inc_sof(cif_dev);
6248		- int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
6249		- int_en &= ~LINE_INT_EN;
6250		- rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
6251		- cif_dev->dvp_sof_in_oneframe = 1;
6252		- }
6253		- }
6254		- }
6255		-
6256	11511	if (intstat & BUS_ERR) {
6257	11512	cif_dev->irq_stats.dvp_bus_err_cnt++;
6258		- v4l2_info(&cif_dev->v4l2_dev, "dvp bus err\n");
	11513	+ cif_dev->err_state \|= RKCIF_ERR_BUS;
6259	11514	}
6260	11515
6261	11516	if (intstat & DVP_ALL_OVERFLOW) {
6262	11517	cif_dev->irq_stats.dvp_overflow_cnt++;
6263		- v4l2_info(&cif_dev->v4l2_dev, "dvp overflow err\n");
	11518	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
6264	11519	}
6265	11520
6266	11521	if (intstat & LINE_ERR) {
6267	11522	cif_dev->irq_stats.dvp_line_err_cnt++;
6268		- v4l2_info(&cif_dev->v4l2_dev, "dvp line err\n");
	11523	+ cif_dev->err_state \|= RKCIF_ERR_LINE;
6269	11524	}
6270	11525
6271	11526	if (intstat & PIX_ERR) {
6272	11527	cif_dev->irq_stats.dvp_pix_err_cnt++;
6273		- v4l2_info(&cif_dev->v4l2_dev, "dvp pix err\n");
	11528	+ cif_dev->err_state \|= RKCIF_ERR_PIXEL;
6274	11529	}
6275	11530
6276		- if (intstat & INTSTAT_ERR) {
	11531	+ if (intstat & INTSTAT_ERR)
6277	11532	cif_dev->irq_stats.all_err_cnt++;
6278		- v4l2_err(&cif_dev->v4l2_dev,
6279		- "ERROR: DVP_ALL_ERROR_INTEN:0x%x!!\n", intstat);
6280		- }
6281	11533
6282	11534	/* There are two irqs enabled:
6283	11535	* - PST_INF_FRAME_END: cif FIFO is ready,
..	..	@@ -6298,7 +11550,7 @@
6298	11550	stream = &cif_dev->stream[RKCIF_STREAM_CIF];
6299	11551
6300	11552	if ((intstat & FRAME_END)) {
6301		- struct vb2_v4l2_buffer *vb_done = NULL;
	11553	+ struct rkcif_buffer *active_buf = NULL;
6302	11554
6303	11555	int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
6304	11556	int_en \|= LINE_INT_EN;
..	..	@@ -6318,7 +11570,7 @@
6318	11570	v4l2_info(&cif_dev->v4l2_dev, "frmid:%d, frmstat:0x%x\n",
6319	11571	frmid, cif_frmst);
6320	11572	rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
6321		- cif_frmst & 0x3);
	11573	+ FRAME_STAT_CLS);
6322	11574	}
6323	11575
6324	11576	if (lastline != stream->pixm.height \|\|
..	..	@@ -6334,30 +11586,30 @@
6334	11586
6335	11587	if (cif_frmst & CIF_F0_READY) {
6336	11588	if (stream->curr_buf)
6337		- vb_done = &stream->curr_buf->vb;
	11589	+ active_buf = stream->curr_buf;
6338	11590	stream->frame_phase = CIF_CSI_FRAME0_READY;
6339	11591	} else if (cif_frmst & CIF_F1_READY) {
6340	11592	if (stream->next_buf)
6341		- vb_done = &stream->next_buf->vb;
	11593	+ active_buf = stream->next_buf;
6342	11594	stream->frame_phase = CIF_CSI_FRAME1_READY;
6343	11595	}
6344	11596
6345	11597	spin_lock_irqsave(&stream->fps_lock, flags);
6346	11598	if (stream->frame_phase & CIF_CSI_FRAME0_READY)
6347		- stream->fps_stats.frm0_timestamp = ktime_get_ns();
	11599	+ stream->fps_stats.frm0_timestamp = rkcif_time_get_ns(cif_dev);
6348	11600	else if (stream->frame_phase & CIF_CSI_FRAME1_READY)
6349		- stream->fps_stats.frm1_timestamp = ktime_get_ns();
	11601	+ stream->fps_stats.frm1_timestamp = rkcif_time_get_ns(cif_dev);
6350	11602	spin_unlock_irqrestore(&stream->fps_lock, flags);
6351	11603
6352	11604	ret = rkcif_assign_new_buffer_oneframe(stream,
6353	11605	RKCIF_YUV_ADDR_STATE_UPDATE);
6354	11606
6355		- if (vb_done && (!ret)) {
6356		- vb_done->sequence = stream->frame_idx;
6357		- rkcif_vb_done_oneframe(stream, vb_done);
	11607	+ if (active_buf && (!ret)) {
	11608	+ active_buf->vb.sequence = stream->frame_idx;
	11609	+ rkcif_vb_done_tasklet(stream, active_buf);
6358	11610	}
6359	11611	stream->frame_idx++;
6360		- cif_dev->irq_stats.all_frm_end_cnt++;
	11612	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
6361	11613	}
6362	11614	} else {
6363	11615	for (i = 0; i < RKCIF_MAX_STREAM_DVP; i++) {
..	..	@@ -6406,10 +11658,24 @@
6406	11658	v4l2_info(&cif_dev->v4l2_dev, "frmid:%d, frmstat:0x%x\n",
6407	11659	frmid, cif_frmst);
6408	11660	rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
6409		- cif_frmst & 0xffff);
	11661	+ FRAME_STAT_CLS);
6410	11662	}
6411	11663	rkcif_update_stream(cif_dev, stream, ch_id);
6412		- cif_dev->irq_stats.all_frm_end_cnt++;
	11664	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
	11665	+ }
	11666	+ }
	11667	+
	11668	+ if ((intstat & LINE_INT_END) && !(intstat & FRAME_END) &&
	11669	+ (cif_dev->dvp_sof_in_oneframe == 0)) {
	11670	+ if ((intstat & (PRE_INF_FRAME_END \| PST_INF_FRAME_END)) == 0x0) {
	11671	+ if ((intstat & INTSTAT_ERR) == 0x0) {
	11672	+ if (!stream->cur_skip_frame)
	11673	+ rkcif_deal_sof(cif_dev);
	11674	+ int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
	11675	+ int_en &= ~LINE_INT_EN;
	11676	+ rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
	11677	+ cif_dev->dvp_sof_in_oneframe = 1;
	11678	+ }
6413	11679	}
6414	11680	}
6415	11681
..	..	@@ -6431,6 +11697,8 @@
6431	11697
6432	11698	intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
6433	11699	lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1);
	11700	+ cif_dev->err_state_work.lastline = lastline;
	11701	+ cif_dev->err_state_work.intstat = intstat;
6434	11702
6435	11703	/* clear all interrupts that has been triggered */
6436	11704	rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
..	..	@@ -6454,18 +11722,6 @@
6454	11722	"ERROR: cif lite lvds all err:0x%x!!\n", intstat);
6455	11723	return;
6456	11724	}
6457		-
6458		- if (intstat & CSI_FRAME0_START_ID0)
6459		- rkcif_lvds_event_inc_sof(cif_dev);
6460		-
6461		-
6462		- if (intstat & CSI_FRAME1_START_ID0)
6463		- rkcif_lvds_event_inc_sof(cif_dev);
6464		-
6465		- /* if do not reach frame dma end, return irq */
6466		- mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev, intstat);
6467		- if (mipi_id < 0)
6468		- return;
6469	11725
6470	11726	for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
6471	11727	mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
..	..	@@ -6505,7 +11761,31 @@
6505	11761	}
6506	11762
6507	11763	rkcif_update_stream(cif_dev, stream, mipi_id);
	11764	+ rkcif_monitor_reset_event(cif_dev);
	11765	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
6508	11766	}
6509		- cif_dev->irq_stats.all_frm_end_cnt++;
	11767	+
	11768	+ if (intstat & CSI_FRAME0_START_ID0)
	11769	+ rkcif_lvds_event_inc_sof(cif_dev);
	11770	+
	11771	+ if (intstat & CSI_FRAME1_START_ID0)
	11772	+ rkcif_lvds_event_inc_sof(cif_dev);
6510	11773	}
6511	11774	}
	11775	+
	11776	+int rkcif_sditf_disconnect(struct video_device *vdev)
	11777	+{
	11778	+ struct rkcif_vdev_node *vnode = vdev_to_node(vdev);
	11779	+ struct rkcif_stream *stream = to_rkcif_stream(vnode);
	11780	+ struct rkcif_device *cifdev = stream->cifdev;
	11781	+ struct media_link *link;
	11782	+ int ret;
	11783	+
	11784	+ link = list_first_entry(&cifdev->sditf[0]->sd.entity.links, struct media_link, list);
	11785	+ ret = media_entity_setup_link(link, 0);
	11786	+ if (ret)
	11787	+ dev_err(cifdev->dev, "failed to disable link of sditf with isp");
	11788	+
	11789	+ return ret;
	11790	+}
	11791	+EXPORT_SYMBOL(rkcif_sditf_disconnect);