~hc/RK356X_SDK_RELEASE.git

..	..	@@ -18,8 +18,8 @@
18	18	#include <media/videobuf2-dma-contig.h>
19	19	#include <media/videobuf2-dma-sg.h>
20	20	#include <soc/rockchip/rockchip-system-status.h>
21		-#include <dt-bindings/soc/rockchip-system-status.h>
22	21	#include <soc/rockchip/rockchip_iommu.h>
	22	+#include <linux/rk-isp32-config.h>
23	23
24	24	#include "dev.h"
25	25	#include "mipi-csi2.h"
..	..	@@ -515,6 +515,10 @@
515	515	.csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
516	516	.field = V4L2_FIELD_NONE,
517	517	}, {
	518	+ .mbus_code = MEDIA_BUS_FMT_GBR888_1X24,
	519	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
	520	+ .field = V4L2_FIELD_NONE,
	521	+ }, {
518	522	.mbus_code = MEDIA_BUS_FMT_RGB565_1X16,
519	523	.csi_fmt_val = CSI_WRDDR_TYPE_RGB565,
520	524	.field = V4L2_FIELD_NONE,
..	..	@@ -611,6 +615,7 @@
611	615	break;
612	616	case MEDIA_BUS_FMT_RGB888_1X24:
613	617	case MEDIA_BUS_FMT_BGR888_1X24:
	618	+ case MEDIA_BUS_FMT_GBR888_1X24:
614	619	if (output_fmt->fourcc == V4L2_PIX_FMT_RGB24 \|\|
615	620	output_fmt->fourcc == V4L2_PIX_FMT_BGR24)
616	621	ret = 0;
..	..	@@ -671,7 +676,7 @@
671	676	break;
672	677	}
673	678	if (ret)
674		- v4l2_err(&stream->cifdev->v4l2_dev,
	679	+ v4l2_dbg(4, rkcif_debug, &stream->cifdev->v4l2_dev,
675	680	"input mbus_code 0x%x, can't transform to %c%c%c%c\n",
676	681	input_fmt->mbus_code,
677	682	output_fmt->fourcc & 0xff,
..	..	@@ -801,6 +806,7 @@
801	806	return 0x1e;
802	807	case MEDIA_BUS_FMT_RGB888_1X24:
803	808	case MEDIA_BUS_FMT_BGR888_1X24:
	809	+ case MEDIA_BUS_FMT_GBR888_1X24:
804	810	if (dsi_input) {
805	811	if (cmd_mode_en) /* dsi command mode*/
806	812	return 0x39;
..	..	@@ -847,11 +853,13 @@
847	853	}
848	854
849	855	const struct
850		-cif_input_fmt get_input_fmt(struct v4l2_subdev sd, struct v4l2_rect *rect,
	856	+cif_input_fmt rkcif_get_input_fmt(struct rkcif_device dev, struct v4l2_rect *rect,
851	857	u32 pad_id, struct csi_channel_info *csi_info)
852	858	{
853	859	struct v4l2_subdev_format fmt;
	860	+ struct v4l2_subdev *sd = dev->terminal_sensor.sd;
854	861	struct rkmodule_channel_info ch_info = {0};
	862	+ struct rkmodule_capture_info capture_info;
855	863	int ret;
856	864	u32 i;
857	865
..	..	@@ -909,7 +917,26 @@
909	917	rect->top = 0;
910	918	rect->width = fmt.format.width;
911	919	rect->height = fmt.format.height;
912		-
	920	+ ret = v4l2_subdev_call(sd,
	921	+ core, ioctl,
	922	+ RKMODULE_GET_CAPTURE_MODE,
	923	+ &capture_info);
	924	+ if (!ret) {
	925	+ if (capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	926	+ dev->hw_dev->is_rk3588s2) {
	927	+ for (i = 0; i < capture_info.multi_dev.dev_num; i++) {
	928	+ if (capture_info.multi_dev.dev_idx[i] == 0)
	929	+ capture_info.multi_dev.dev_idx[i] = 2;
	930	+ else if (capture_info.multi_dev.dev_idx[i] == 2)
	931	+ capture_info.multi_dev.dev_idx[i] = 4;
	932	+ else if (capture_info.multi_dev.dev_idx[i] == 3)
	933	+ capture_info.multi_dev.dev_idx[i] = 5;
	934	+ }
	935	+ }
	936	+ csi_info->capture_info = capture_info;
	937	+ } else {
	938	+ csi_info->capture_info.mode = RKMODULE_CAPTURE_MODE_NONE;
	939	+ }
913	940	for (i = 0; i < ARRAY_SIZE(in_fmts); i++)
914	941	if (fmt.format.code == in_fmts[i].mbus_code &&
915	942	fmt.format.field == in_fmts[i].field)
..	..	@@ -1587,25 +1614,29 @@
1587	1614	return ret;
1588	1615	}
1589	1616
1590		-static void rkcif_rx_buffer_free(struct rkcif_stream *stream)
	1617	+static struct v4l2_subdev get_rkisp_sd(struct sditf_priv priv)
1591	1618	{
1592	1619	struct media_pad *pad = NULL;
	1620	+
	1621	+ if (priv && priv->pads[0].entity->num_links) {
	1622	+ if (priv->is_combine_mode)
	1623	+ pad = media_entity_remote_pad(&priv->pads[1]);
	1624	+ else
	1625	+ pad = media_entity_remote_pad(&priv->pads[0]);
	1626	+ if (pad)
	1627	+ return media_entity_to_v4l2_subdev(pad->entity);
	1628	+ }
	1629	+ return NULL;
	1630	+}
	1631	+
	1632	+static void rkcif_rx_buffer_free(struct rkcif_stream *stream)
	1633	+{
1593	1634	struct v4l2_subdev *sd;
1594	1635	struct rkisp_rx_buf *dbufs;
1595	1636	struct rkcif_device *dev = stream->cifdev;
1596	1637
1597		- if (dev->sditf[0] && dev->sditf[0]->num_sensors != 0) {
1598		- if (dev->sditf[0]->is_combine_mode)
1599		- pad = media_entity_remote_pad(&dev->sditf[0]->pads[1]);
1600		- else
1601		- pad = media_entity_remote_pad(&dev->sditf[0]->pads[0]);
1602		- } else {
1603		- return;
1604		- }
1605		-
1606		- if (pad)
1607		- sd = media_entity_to_v4l2_subdev(pad->entity);
1608		- else
	1638	+ sd = get_rkisp_sd(dev->sditf[0]);
	1639	+ if (!sd)
1609	1640	return;
1610	1641
1611	1642	while (!list_empty(&stream->rx_buf_head_vicap)) {
..	..	@@ -1619,31 +1650,23 @@
1619	1650	}
1620	1651	}
1621	1652
1622		-static void rkcif_s_rx_buffer(struct rkcif_device dev, struct rkisp_rx_buf dbufs)
	1653	+static void rkcif_s_rx_buffer(struct rkcif_stream stream, struct rkisp_rx_buf dbufs)
1623	1654	{
1624		- struct media_pad *pad = NULL;
	1655	+ struct rkcif_device *dev = stream->cifdev;
1625	1656	struct v4l2_subdev *sd;
1626	1657	struct rkcif_rx_buffer *rx_buf = NULL;
1627	1658
1628		- if (dev->sditf[0]) {
1629		- if (dev->sditf[0]->is_combine_mode)
1630		- pad = media_entity_remote_pad(&dev->sditf[0]->pads[1]);
1631		- else
1632		- pad = media_entity_remote_pad(&dev->sditf[0]->pads[0]);
1633		- } else {
	1659	+ sd = get_rkisp_sd(dev->sditf[0]);
	1660	+ if (!sd)
1634	1661	return;
1635		- }
1636		- if (pad)
1637		- sd = media_entity_to_v4l2_subdev(pad->entity);
1638		- else
1639		- return;
1640		- if (dev->rdbk_debug &&
1641		- dbufs->sequence < 15) {
	1662	+ if ((dev->rdbk_debug &&
	1663	+ dbufs->sequence < 15) \|\|
	1664	+ rkcif_debug == 3) {
1642	1665	rx_buf = to_cif_rx_buf(dbufs);
1643	1666	v4l2_info(&dev->v4l2_dev,
1644	1667	"s_buf seq %d type %d, dma addr %x, %lld\n",
1645	1668	dbufs->sequence, dbufs->type, (u32)rx_buf->dummy.dma_addr,
1646		- ktime_get_ns());
	1669	+ rkcif_time_get_ns(dev));
1647	1670	}
1648	1671	v4l2_subdev_call(sd, video, s_rx_buffer, dbufs, NULL);
1649	1672	}
..	..	@@ -1668,6 +1691,20 @@
1668	1691	val &= ~(RKCIF_SKIP_EN(stream->id));
1669	1692	rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
1670	1693	stream->skip_info.skip_en = false;
	1694	+}
	1695	+
	1696	+static void rkcif_rdbk_with_tools(struct rkcif_stream *stream,
	1697	+ struct rkcif_rx_buffer *active_buf)
	1698	+{
	1699	+ unsigned long flags;
	1700	+
	1701	+ spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
	1702	+ if (stream->tools_vdev->state == RKCIF_STATE_STREAMING) {
	1703	+ list_add_tail(&active_buf->list, &stream->tools_vdev->buf_done_head);
	1704	+ if (!work_busy(&stream->tools_vdev->work))
	1705	+ schedule_work(&stream->tools_vdev->work);
	1706	+ }
	1707	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
1671	1708	}
1672	1709
1673	1710	static void rkcif_rdbk_frame_end_toisp(struct rkcif_stream *stream,
..	..	@@ -1731,9 +1768,15 @@
1731	1768	}
1732	1769	dev->rdbk_rx_buf[RDBK_M]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
1733	1770	dev->rdbk_rx_buf[RDBK_S]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
1734		- rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_L]->dbufs);
1735		- rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_M]->dbufs);
1736		- rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_S]->dbufs);
	1771	+ rkcif_s_rx_buffer(&dev->stream[RDBK_L], &dev->rdbk_rx_buf[RDBK_L]->dbufs);
	1772	+ rkcif_s_rx_buffer(&dev->stream[RDBK_M], &dev->rdbk_rx_buf[RDBK_M]->dbufs);
	1773	+ rkcif_s_rx_buffer(&dev->stream[RDBK_S], &dev->rdbk_rx_buf[RDBK_S]->dbufs);
	1774	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_L], dev->rdbk_rx_buf[RDBK_L]);
	1775	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_M], dev->rdbk_rx_buf[RDBK_M]);
	1776	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_S], dev->rdbk_rx_buf[RDBK_S]);
	1777	+ atomic_dec(&dev->stream[RDBK_L].buf_cnt);
	1778	+ atomic_dec(&dev->stream[RDBK_M].buf_cnt);
	1779	+ atomic_dec(&dev->stream[RDBK_S].buf_cnt);
1737	1780	dev->rdbk_rx_buf[RDBK_L] = NULL;
1738	1781	dev->rdbk_rx_buf[RDBK_M] = NULL;
1739	1782	dev->rdbk_rx_buf[RDBK_S] = NULL;
..	..	@@ -1770,8 +1813,12 @@
1770	1813	}
1771	1814	}
1772	1815	dev->rdbk_rx_buf[RDBK_M]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
1773		- rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_L]->dbufs);
1774		- rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_M]->dbufs);
	1816	+ rkcif_s_rx_buffer(&dev->stream[RDBK_L], &dev->rdbk_rx_buf[RDBK_L]->dbufs);
	1817	+ rkcif_s_rx_buffer(&dev->stream[RDBK_M], &dev->rdbk_rx_buf[RDBK_M]->dbufs);
	1818	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_L], dev->rdbk_rx_buf[RDBK_L]);
	1819	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_M], dev->rdbk_rx_buf[RDBK_M]);
	1820	+ atomic_dec(&dev->stream[RDBK_L].buf_cnt);
	1821	+ atomic_dec(&dev->stream[RDBK_M].buf_cnt);
1775	1822	dev->rdbk_rx_buf[RDBK_L] = NULL;
1776	1823	dev->rdbk_rx_buf[RDBK_M] = NULL;
1777	1824	}
..	..	@@ -1783,14 +1830,51 @@
1783	1830	spin_unlock_irqrestore(&dev->hdr_lock, flags);
1784	1831	}
1785	1832
	1833	+static void rkcif_write_buff_addr_multi_dev_combine(struct rkcif_stream *stream,
	1834	+ u32 frm_addr_y, u32 frm_addr_uv,
	1835	+ u32 buff_addr_y, u32 buff_addr_cbcr,
	1836	+ bool is_dummy_buf)
	1837	+{
	1838	+ struct rkcif_device *dev = stream->cifdev;
	1839	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
	1840	+ u32 addr_y, addr_cbcr;
	1841	+ int addr_offset = 0;
	1842	+ int i = 0;
	1843	+ int tmp_host_index = dev->csi_host_idx;
	1844	+
	1845	+ for (i = 0; i < capture_info->multi_dev.dev_num; i++) {
	1846	+ if (is_dummy_buf) {
	1847	+ addr_y = buff_addr_y;
	1848	+ } else {
	1849	+ addr_offset = dev->channels[stream->id].left_virtual_width;
	1850	+ addr_y = buff_addr_y + addr_offset * i;
	1851	+ }
	1852	+ dev->csi_host_idx = capture_info->multi_dev.dev_idx[i];
	1853	+ rkcif_write_register(dev, frm_addr_y, addr_y);
	1854	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW &&
	1855	+ frm_addr_uv && buff_addr_cbcr) {
	1856	+ if (is_dummy_buf) {
	1857	+ addr_cbcr = buff_addr_cbcr;
	1858	+ } else {
	1859	+ addr_offset = dev->channels[stream->id].left_virtual_width;
	1860	+ addr_cbcr = buff_addr_cbcr + addr_offset * i;
	1861	+ }
	1862	+ rkcif_write_register(dev, frm_addr_uv, addr_cbcr);
	1863	+ }
	1864	+ }
	1865	+ dev->csi_host_idx = tmp_host_index;
	1866	+}
	1867	+
1786	1868	static void rkcif_assign_new_buffer_init_toisp(struct rkcif_stream *stream,
1787	1869	int channel_id)
1788	1870	{
1789	1871	struct rkcif_device *dev = stream->cifdev;
1790	1872	struct rkcif_rx_buffer *rx_buf;
1791	1873	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	1874	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
1792	1875	u32 frm0_addr_y;
1793	1876	u32 frm1_addr_y;
	1877	+ u32 buff_addr_y;
1794	1878	unsigned long flags;
1795	1879
1796	1880	if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
..	..	@@ -1817,9 +1901,18 @@
1817	1901	}
1818	1902	}
1819	1903
1820		- if (stream->curr_buf_toisp)
1821		- rkcif_write_register(dev, frm0_addr_y,
1822		- stream->curr_buf_toisp->dummy.dma_addr);
	1904	+ if (stream->curr_buf_toisp) {
	1905	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	1906	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	1907	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm0_addr_y, 0,
	1908	+ buff_addr_y, 0, false);
	1909	+ } else {
	1910	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	1911	+ }
	1912	+ } else {
	1913	+ if (stream->lack_buf_cnt < 2)
	1914	+ stream->lack_buf_cnt++;
	1915	+ }
1823	1916
1824	1917	if (!stream->next_buf_toisp) {
1825	1918	if (!list_empty(&stream->rx_buf_head)) {
..	..	@@ -1836,12 +1929,41 @@
1836	1929	}
1837	1930	}
1838	1931
1839		- if (stream->next_buf_toisp)
1840		- rkcif_write_register(dev, frm1_addr_y,
1841		- stream->next_buf_toisp->dummy.dma_addr);
	1932	+ if (stream->next_buf_toisp) {
	1933	+ buff_addr_y = stream->next_buf_toisp->dummy.dma_addr;
	1934	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	1935	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm1_addr_y, 0,
	1936	+ buff_addr_y, 0, false);
	1937	+ } else {
	1938	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	1939	+ }
	1940	+ } else {
	1941	+ if (stream->lack_buf_cnt < 2)
	1942	+ stream->lack_buf_cnt++;
	1943	+ }
1842	1944
1843	1945	spin_unlock_irqrestore(&stream->vbq_lock, flags);
1844	1946	stream->buf_owner = RKCIF_DMAEN_BY_ISP;
	1947	+}
	1948	+
	1949	+static void rkcif_dphy_quick_stream(struct rkcif_device *dev, int on)
	1950	+{
	1951	+ struct rkcif_pipeline *p = NULL;
	1952	+ int j = 0;
	1953	+
	1954	+ if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	1955	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	1956	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) {
	1957	+ p = &dev->pipe;
	1958	+ for (j = 0; j < p->num_subdevs; j++) {
	1959	+ if (p->subdevs[j] != dev->terminal_sensor.sd &&
	1960	+ p->subdevs[j] != dev->active_sensor->sd) {
	1961	+ v4l2_subdev_call(p->subdevs[j], core, ioctl,
	1962	+ RKMODULE_SET_QUICK_STREAM, &on);
	1963	+ break;
	1964	+ }
	1965	+ }
	1966	+ }
1845	1967	}
1846	1968
1847	1969	static int rkcif_assign_new_buffer_update_toisp(struct rkcif_stream *stream,
..	..	@@ -1849,11 +1971,13 @@
1849	1971	{
1850	1972	struct rkcif_device *dev = stream->cifdev;
1851	1973	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	1974	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
1852	1975	struct rkcif_rx_buffer *buffer = NULL;
1853	1976	struct rkcif_rx_buffer *active_buf = NULL;
1854	1977	struct sditf_priv *priv = dev->sditf[0];
1855		- u32 frm_addr_y;
	1978	+ u32 frm_addr_y, buff_addr_y;
1856	1979	unsigned long flags;
	1980	+
1857	1981
1858	1982	if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
1859	1983	mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
..	..	@@ -1866,13 +1990,19 @@
1866	1990	get_dvp_reg_index_of_frm0_y_addr(channel_id) :
1867	1991	get_dvp_reg_index_of_frm1_y_addr(channel_id);
1868	1992	}
	1993	+
1869	1994	spin_lock_irqsave(&stream->vbq_lock, flags);
	1995	+ if (stream->cur_skip_frame)
	1996	+ goto out_get_buf;
	1997	+ memset(&stream->toisp_buf_state, 0, sizeof(stream->toisp_buf_state));
1870	1998	if (!list_empty(&stream->rx_buf_head)) {
	1999	+ if (stream->curr_buf_toisp && stream->next_buf_toisp &&
	2000	+ stream->curr_buf_toisp != stream->next_buf_toisp)
	2001	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_ROTATE;
	2002	+ else
	2003	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_LOSS;
1871	2004	if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1872		- if (stream->curr_buf_toisp == stream->next_buf_toisp)
1873		- active_buf = NULL;
1874		- else
1875		- active_buf = stream->curr_buf_toisp;
	2005	+ active_buf = stream->curr_buf_toisp;
1876	2006
1877	2007	buffer = list_first_entry(&stream->rx_buf_head,
1878	2008	struct rkcif_rx_buffer, list);
..	..	@@ -1887,22 +2017,24 @@
1887	2017	active_buf->dbufs.is_first = true;
1888	2018	active_buf->dbufs.sequence = stream->frame_idx - 1;
1889	2019	active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
1890		- active_buf->fe_timestamp = ktime_get_ns();
	2020	+ active_buf->fe_timestamp = rkcif_time_get_ns(dev);
1891	2021	stream->last_frame_idx = stream->frame_idx;
1892		- if (dev->hdr.hdr_mode == NO_HDR)
1893		- rkcif_s_rx_buffer(dev, &active_buf->dbufs);
1894		- else
	2022	+ if (dev->hdr.hdr_mode == NO_HDR) {
	2023	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	2024	+ if (dev->is_support_tools && stream->tools_vdev)
	2025	+ rkcif_rdbk_with_tools(stream, active_buf);
	2026	+ atomic_dec(&stream->buf_cnt);
	2027	+ } else {
1895	2028	rkcif_rdbk_frame_end_toisp(stream, active_buf);
1896		- stream->buf_num_toisp--;
	2029	+ }
1897	2030	} else {
1898		- rkcif_s_rx_buffer(dev, &stream->next_buf_toisp->dbufs);
1899		- stream->buf_num_toisp--;
	2031	+ if (active_buf)
	2032	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	2033	+ if (dev->is_support_tools && stream->tools_vdev)
	2034	+ rkcif_rdbk_with_tools(stream, active_buf);
1900	2035	}
1901	2036	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1902		- if (stream->curr_buf_toisp == stream->next_buf_toisp)
1903		- active_buf = NULL;
1904		- else
1905		- active_buf = stream->next_buf_toisp;
	2037	+ active_buf = stream->next_buf_toisp;
1906	2038	buffer = list_first_entry(&stream->rx_buf_head,
1907	2039	struct rkcif_rx_buffer, list);
1908	2040	if (buffer) {
..	..	@@ -1916,16 +2048,21 @@
1916	2048	active_buf->dbufs.is_first = true;
1917	2049	active_buf->dbufs.sequence = stream->frame_idx - 1;
1918	2050	active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
1919		- active_buf->fe_timestamp = ktime_get_ns();
	2051	+ active_buf->fe_timestamp = rkcif_time_get_ns(dev);
1920	2052	stream->last_frame_idx = stream->frame_idx;
1921		- if (dev->hdr.hdr_mode == NO_HDR)
1922		- rkcif_s_rx_buffer(dev, &active_buf->dbufs);
1923		- else
	2053	+ if (dev->hdr.hdr_mode == NO_HDR) {
	2054	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	2055	+ if (dev->is_support_tools && stream->tools_vdev)
	2056	+ rkcif_rdbk_with_tools(stream, active_buf);
	2057	+ atomic_dec(&stream->buf_cnt);
	2058	+ } else {
1924	2059	rkcif_rdbk_frame_end_toisp(stream, active_buf);
1925		- stream->buf_num_toisp--;
	2060	+ }
1926	2061	} else {
1927		- rkcif_s_rx_buffer(dev, &stream->curr_buf_toisp->dbufs);
1928		- stream->buf_num_toisp--;
	2062	+ if (active_buf)
	2063	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	2064	+ if (dev->is_support_tools && stream->tools_vdev)
	2065	+ rkcif_rdbk_with_tools(stream, active_buf);
1929	2066	}
1930	2067	}
1931	2068	if (stream->lack_buf_cnt)
..	..	@@ -1938,10 +2075,8 @@
1938	2075	if (dev->hw_dev->dummy_buf.vaddr) {
1939	2076	if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1940	2077	active_buf = stream->curr_buf_toisp;
1941		- stream->curr_buf_toisp = NULL;
1942	2078	} else {
1943	2079	active_buf = stream->next_buf_toisp;
1944		- stream->next_buf_toisp = NULL;
1945	2080	}
1946	2081	} else if (stream->curr_buf_toisp && stream->next_buf_toisp &&
1947	2082	stream->curr_buf_toisp != stream->next_buf_toisp) {
..	..	@@ -1954,23 +2089,34 @@
1954	2089	stream->next_buf_toisp = stream->curr_buf_toisp;
1955	2090	buffer = stream->curr_buf_toisp;
1956	2091	}
	2092	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_THESAME;
1957	2093	if (stream->cifdev->rdbk_debug)
1958	2094	v4l2_info(&stream->cifdev->v4l2_dev,
1959	2095	"stream[%d] hold buf %x\n",
1960	2096	stream->id,
1961	2097	(u32)stream->next_buf_toisp->dummy.dma_addr);
	2098	+ } else {
	2099	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_LOSS;
	2100	+ if (stream->is_single_cap) {
	2101	+ active_buf = stream->curr_buf_toisp;
	2102	+ stream->curr_buf_toisp = NULL;
	2103	+ stream->next_buf_toisp = NULL;
	2104	+ }
1962	2105	}
	2106	+
1963	2107	if (active_buf) {
1964	2108	if (stream->frame_idx == 1)
1965	2109	active_buf->dbufs.is_first = true;
1966	2110	active_buf->dbufs.sequence = stream->frame_idx - 1;
1967	2111	active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
1968		- active_buf->fe_timestamp = ktime_get_ns();
	2112	+ active_buf->fe_timestamp = rkcif_time_get_ns(dev);
1969	2113	stream->last_frame_idx = stream->frame_idx;
1970		- if (dev->hdr.hdr_mode == NO_HDR)
1971		- rkcif_s_rx_buffer(dev, &active_buf->dbufs);
1972		- else
	2114	+ if (dev->hdr.hdr_mode == NO_HDR) {
	2115	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	2116	+ atomic_dec(&stream->buf_cnt);
	2117	+ } else {
1973	2118	rkcif_rdbk_frame_end_toisp(stream, active_buf);
	2119	+ }
1974	2120	} else {
1975	2121	if (stream->cifdev->rdbk_debug && dev->hw_dev->dummy_buf.vaddr)
1976	2122	v4l2_info(&stream->cifdev->v4l2_dev,
..	..	@@ -1978,13 +2124,19 @@
1978	2124	stream->id,
1979	2125	stream->frame_idx - 1);
1980	2126	}
	2127	+ if (dev->is_support_tools && stream->tools_vdev && active_buf)
	2128	+ rkcif_rdbk_with_tools(stream, active_buf);
1981	2129	}
1982		-
1983	2130	out_get_buf:
1984	2131	stream->frame_phase_cache = stream->frame_phase;
1985	2132	if (buffer) {
1986		- rkcif_write_register(dev, frm_addr_y,
1987		- buffer->dummy.dma_addr);
	2133	+ buff_addr_y = buffer->dummy.dma_addr;
	2134	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2135	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2136	+ buff_addr_y, 0, false);
	2137	+ } else {
	2138	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2139	+ }
1988	2140	if (dev->rdbk_debug > 1 &&
1989	2141	stream->frame_idx < 15)
1990	2142	v4l2_info(&dev->v4l2_dev,
..	..	@@ -1994,8 +2146,13 @@
1994	2146	frm_addr_y, (u32)buffer->dummy.dma_addr);
1995	2147	} else if (dev->hw_dev->dummy_buf.vaddr && priv &&
1996	2148	priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
1997		- rkcif_write_register(dev, frm_addr_y,
1998		- dev->hw_dev->dummy_buf.dma_addr);
	2149	+ buff_addr_y = dev->hw_dev->dummy_buf.dma_addr;
	2150	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2151	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2152	+ buff_addr_y, 0, true);
	2153	+ } else {
	2154	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2155	+ }
1999	2156	}
2000	2157	spin_unlock_irqrestore(&stream->vbq_lock, flags);
2001	2158	return 0;
..	..	@@ -2018,16 +2175,20 @@
2018	2175	struct rkcif_device *dev = stream->cifdev;
2019	2176	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2020	2177	struct rkcif_rx_buffer *buffer = NULL;
	2178	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
2021	2179	struct rkcif_rx_buffer *active_buf = NULL;
2022		- u32 frm_addr_y;
	2180	+ u32 frm_addr_y, buff_addr_y;
2023	2181	u32 vblank = 0;
2024	2182	u32 vblank_ns = 0;
2025	2183	u64 cur_time = 0;
2026	2184	int frame_phase = 0;
2027	2185	int frame_phase_next = 0;
2028		- bool is_early_update = false;
2029	2186
2030		- if (stream->curr_buf_toisp != stream->next_buf_toisp) {
	2187	+ if (stream->toisp_buf_state.state == RKCIF_TOISP_BUF_ROTATE \|\|
	2188	+ (stream->toisp_buf_state.state == RKCIF_TOISP_BUF_THESAME &&
	2189	+ stream->toisp_buf_state.check_cnt >= 1) \|\|
	2190	+ (stream->toisp_buf_state.state == RKCIF_TOISP_BUF_LOSS &&
	2191	+ stream->toisp_buf_state.check_cnt >= 2)) {
2031	2192	if (dev->rdbk_debug > 2 &&
2032	2193	stream->frame_idx < 15)
2033	2194	v4l2_info(&dev->v4l2_dev,
..	..	@@ -2041,20 +2202,26 @@
2041	2202	dev->sensor_linetime = rkcif_get_linetime(stream);
2042	2203	vblank = rkcif_get_sensor_vblank(dev);
2043	2204	vblank_ns = vblank * dev->sensor_linetime;
2044		- cur_time = ktime_get_ns();
	2205	+ cur_time = rkcif_time_get_ns(dev);
2045	2206
2046		- if (dev->chip_id > CHIP_RK3568_CIF &&
2047		- dev->hdr.hdr_mode == NO_HDR &&
2048		- cur_time - stream->readout.fe_timestamp < (vblank_ns - 500000) &&
2049		- stream->lack_buf_cnt == 2 &&
2050		- stream->frame_idx > stream->last_frame_idx) {
2051		- is_early_update = true;
2052		- frame_phase = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2053		- CIF_CSI_FRAME1_READY : CIF_CSI_FRAME0_READY;
2054		- frame_phase_next = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2055		- CIF_CSI_FRAME0_READY : CIF_CSI_FRAME1_READY;
2056		- } else {
	2207	+ if (stream->toisp_buf_state.state == RKCIF_TOISP_BUF_THESAME) {
2057	2208	frame_phase = stream->frame_phase;
	2209	+ } else {
	2210	+ if (stream->toisp_buf_state.state == RKCIF_TOISP_BUF_LOSS &&
	2211	+ stream->toisp_buf_state.check_cnt == 0 &&
	2212	+ cur_time - stream->readout.fe_timestamp < (vblank_ns - 500000)) {
	2213	+ stream->toisp_buf_state.is_early_update = true;
	2214	+ frame_phase = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2215	+ CIF_CSI_FRAME1_READY : CIF_CSI_FRAME0_READY;
	2216	+ frame_phase_next = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2217	+ CIF_CSI_FRAME0_READY : CIF_CSI_FRAME1_READY;
	2218	+ } else {
	2219	+ if (stream->toisp_buf_state.check_cnt == 1 &&
	2220	+ (!stream->toisp_buf_state.is_early_update))
	2221	+ return;
	2222	+ frame_phase = stream->frame_phase;
	2223	+ stream->toisp_buf_state.is_early_update = false;
	2224	+ }
2058	2225	}
2059	2226	if (dev->rdbk_debug > 2 &&
2060	2227	stream->frame_idx < 15)
..	..	@@ -2082,8 +2249,15 @@
2082	2249	if (buffer) {
2083	2250	list_del(&buffer->list);
2084	2251	stream->curr_buf_toisp = buffer;
2085		- rkcif_write_register(dev, frm_addr_y,
2086		- stream->curr_buf_toisp->dummy.dma_addr);
	2252	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2253	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2254	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2255	+ frm_addr_y, 0,
	2256	+ buff_addr_y, 0,
	2257	+ false);
	2258	+ } else {
	2259	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2260	+ }
2087	2261	if (dev->rdbk_debug > 1 &&
2088	2262	stream->frame_idx < 15)
2089	2263	v4l2_info(&dev->v4l2_dev,
..	..	@@ -2091,7 +2265,6 @@
2091	2265	stream->id,
2092	2266	stream->frame_idx - 1, frm_addr_y,
2093	2267	(u32)stream->curr_buf_toisp->dummy.dma_addr);
2094		- stream->buf_num_toisp--;
2095	2268	}
2096	2269	} else if (frame_phase == CIF_CSI_FRAME1_READY) {
2097	2270	active_buf = stream->next_buf_toisp;
..	..	@@ -2100,8 +2273,15 @@
2100	2273	if (buffer) {
2101	2274	list_del(&buffer->list);
2102	2275	stream->next_buf_toisp = buffer;
2103		- rkcif_write_register(dev, frm_addr_y,
2104		- stream->next_buf_toisp->dummy.dma_addr);
	2276	+ buff_addr_y = stream->next_buf_toisp->dummy.dma_addr;
	2277	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2278	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2279	+ frm_addr_y, 0,
	2280	+ buff_addr_y, 0,
	2281	+ false);
	2282	+ } else {
	2283	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2284	+ }
2105	2285	if (dev->rdbk_debug > 1 &&
2106	2286	stream->frame_idx < 15)
2107	2287	v4l2_info(&dev->v4l2_dev,
..	..	@@ -2109,13 +2289,12 @@
2109	2289	stream->id,
2110	2290	stream->frame_idx - 1, frm_addr_y,
2111	2291	(u32)stream->next_buf_toisp->dummy.dma_addr);
2112		- stream->buf_num_toisp--;
2113	2292	}
2114	2293	}
2115	2294	if (stream->lack_buf_cnt)
2116	2295	stream->lack_buf_cnt--;
2117	2296	}
2118		- if (is_early_update) {
	2297	+ if (stream->toisp_buf_state.is_early_update) {
2119	2298	if (dev->rdbk_debug > 1 &&
2120	2299	stream->frame_idx < 15)
2121	2300	v4l2_info(&dev->v4l2_dev,
..	..	@@ -2131,7 +2310,7 @@
2131	2310	active_buf->dbufs.sequence = stream->frame_idx - 1;
2132	2311	active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
2133	2312	stream->last_frame_idx = stream->frame_idx;
2134		- rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	2313	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
2135	2314	}
2136	2315	if (dev->hw_dev->dummy_buf.vaddr)
2137	2316	return;
..	..	@@ -2150,9 +2329,15 @@
2150	2329	stream->next_buf_toisp = stream->curr_buf_toisp;
2151	2330	else
2152	2331	stream->curr_buf_toisp = stream->next_buf_toisp;
2153		- rkcif_write_register(dev, frm_addr_y,
2154		- stream->curr_buf_toisp->dummy.dma_addr);
	2332	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2333	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2334	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2335	+ buff_addr_y, 0, false);
	2336	+ } else {
	2337	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2338	+ }
2155	2339	}
	2340	+ stream->toisp_buf_state.check_cnt++;
2156	2341	}
2157	2342
2158	2343	static void rkcif_assign_new_buffer_init(struct rkcif_stream *stream,
..	..	@@ -2162,10 +2347,12 @@
2162	2347	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2163	2348	u32 frm0_addr_y, frm0_addr_uv;
2164	2349	u32 frm1_addr_y, frm1_addr_uv;
	2350	+ u32 buff_addr_y, buff_addr_cbcr;
2165	2351	unsigned long flags;
2166	2352	struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2167	2353	struct csi_channel_info *channel = &dev->channels[channel_id];
2168	2354
	2355	+ stream->lack_buf_cnt = 0;
2169	2356	if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
2170	2357	mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
2171	2358	mbus_cfg->type == V4L2_MBUS_CCP2) {
..	..	@@ -2187,21 +2374,45 @@
2187	2374	stream->curr_buf = list_first_entry(&stream->buf_head,
2188	2375	struct rkcif_buffer,
2189	2376	queue);
	2377	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev, "%s %d, stream[%d] buf idx %d\n",
	2378	+ __func__, __LINE__, stream->id, stream->curr_buf->vb.vb2_buf.index);
2190	2379	list_del(&stream->curr_buf->queue);
2191	2380	}
2192	2381	}
2193	2382
2194	2383	if (stream->curr_buf) {
2195		- rkcif_write_register(dev, frm0_addr_y,
2196		- stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
2197		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2198		- rkcif_write_register(dev, frm0_addr_uv,
2199		- stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
	2384	+ buff_addr_y = stream->curr_buf->buff_addr[RKCIF_PLANE_Y];
	2385	+ buff_addr_cbcr = stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR];
	2386	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2387	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2388	+ frm0_addr_y,
	2389	+ frm0_addr_uv,
	2390	+ buff_addr_y,
	2391	+ buff_addr_cbcr,
	2392	+ false);
	2393	+ } else {
	2394	+ rkcif_write_register(dev, frm0_addr_y,
	2395	+ stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
	2396	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2397	+ rkcif_write_register(dev, frm0_addr_uv,
	2398	+ stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
	2399	+ }
2200	2400	} else {
2201	2401	if (dummy_buf->vaddr) {
2202		- rkcif_write_register(dev, frm0_addr_y, dummy_buf->dma_addr);
2203		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2204		- rkcif_write_register(dev, frm0_addr_uv, dummy_buf->dma_addr);
	2402	+ buff_addr_y = dummy_buf->dma_addr;
	2403	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2404	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2405	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2406	+ frm0_addr_y,
	2407	+ frm0_addr_uv,
	2408	+ buff_addr_y,
	2409	+ buff_addr_cbcr,
	2410	+ true);
	2411	+ } else {
	2412	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	2413	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2414	+ rkcif_write_register(dev, frm0_addr_uv, buff_addr_cbcr);
	2415	+ }
2205	2416	} else {
2206	2417	if (stream->lack_buf_cnt < 2)
2207	2418	stream->lack_buf_cnt++;
..	..	@@ -2211,43 +2422,71 @@
2211	2422	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
2212	2423	stream->next_buf = stream->curr_buf;
2213	2424	if (stream->next_buf) {
2214		- rkcif_write_register(dev, frm1_addr_y,
2215		- stream->next_buf->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
2216		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2217		- rkcif_write_register(dev, frm1_addr_uv,
2218		- stream->next_buf->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	2425	+ buff_addr_y = stream->next_buf->buff_addr[RKCIF_PLANE_Y];
	2426	+ buff_addr_cbcr = stream->next_buf->buff_addr[RKCIF_PLANE_CBCR];
	2427	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2428	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2429	+ frm1_addr_y,
	2430	+ frm1_addr_uv,
	2431	+ buff_addr_y,
	2432	+ buff_addr_cbcr,
	2433	+ false);
	2434	+ } else {
	2435	+ rkcif_write_register(dev, frm1_addr_y,
	2436	+ buff_addr_y + (channel->virtual_width / 2));
	2437	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2438	+ rkcif_write_register(dev, frm1_addr_uv,
	2439	+ buff_addr_cbcr + (channel->virtual_width / 2));
	2440	+ }
2219	2441	}
2220	2442	} else {
2221	2443	if (!stream->next_buf) {
2222	2444	if (!list_empty(&stream->buf_head)) {
2223	2445	stream->next_buf = list_first_entry(&stream->buf_head,
2224	2446	struct rkcif_buffer, queue);
	2447	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev, "%s %d, stream[%d] buf idx %d\n",
	2448	+ __func__, __LINE__, stream->id, stream->next_buf->vb.vb2_buf.index);
2225	2449	list_del(&stream->next_buf->queue);
	2450	+ } else if (stream->curr_buf) {
	2451	+ stream->next_buf = stream->curr_buf;
2226	2452	}
2227	2453	}
2228	2454
2229		- if (stream->next_buf) {
2230		- rkcif_write_register(dev, frm1_addr_y,
2231		- stream->next_buf->buff_addr[RKCIF_PLANE_Y]);
2232		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2233		- rkcif_write_register(dev, frm1_addr_uv,
2234		- stream->next_buf->buff_addr[RKCIF_PLANE_CBCR]);
2235		- } else {
2236		- if (dummy_buf->vaddr) {
	2455	+ if (!stream->next_buf && dummy_buf->vaddr) {
	2456	+ buff_addr_y = dummy_buf->dma_addr;
	2457	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2458	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2459	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2460	+ frm1_addr_y,
	2461	+ frm1_addr_uv,
	2462	+ buff_addr_y,
	2463	+ buff_addr_cbcr,
	2464	+ true);
	2465	+ } else {
2237	2466	rkcif_write_register(dev, frm1_addr_y, dummy_buf->dma_addr);
2238	2467	if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2239	2468	rkcif_write_register(dev, frm1_addr_uv, dummy_buf->dma_addr);
	2469	+ }
	2470	+
	2471	+ } else if (!stream->next_buf && stream->curr_buf) {
	2472	+ stream->next_buf = stream->curr_buf;
	2473	+ if (stream->lack_buf_cnt < 2)
	2474	+ stream->lack_buf_cnt++;
	2475	+ }
	2476	+ if (stream->next_buf) {
	2477	+ buff_addr_y = stream->next_buf->buff_addr[RKCIF_PLANE_Y];
	2478	+ buff_addr_cbcr = stream->next_buf->buff_addr[RKCIF_PLANE_CBCR];
	2479	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2480	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2481	+ frm1_addr_y,
	2482	+ frm1_addr_uv,
	2483	+ buff_addr_y,
	2484	+ buff_addr_cbcr,
	2485	+ false);
2240	2486	} else {
2241		- if (stream->curr_buf) {
2242		- stream->next_buf = stream->curr_buf;
2243		- rkcif_write_register(dev, frm1_addr_y,
2244		- stream->next_buf->buff_addr[RKCIF_PLANE_Y]);
2245		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2246		- rkcif_write_register(dev, frm1_addr_uv,
2247		- stream->next_buf->buff_addr[RKCIF_PLANE_CBCR]);
2248		- }
2249		- if (stream->lack_buf_cnt < 2)
2250		- stream->lack_buf_cnt++;
	2487	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	2488	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2489	+ rkcif_write_register(dev, frm1_addr_uv, buff_addr_cbcr);
2251	2490	}
2252	2491	}
2253	2492	}
..	..	@@ -2295,6 +2534,7 @@
2295	2534	struct rkisp_rx_buf *dbufs = NULL;
2296	2535	struct dma_buf *dbuf = NULL;
2297	2536	int ret = 0;
	2537	+ u32 buff_addr_y, buff_addr_cbcr;
2298	2538	unsigned long flags;
2299	2539
2300	2540	if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
..	..	@@ -2315,19 +2555,9 @@
2315	2555	get_dvp_reg_index_of_frm1_uv_addr(channel_id);
2316	2556	}
2317	2557
2318		- if (dev->hdr.hdr_mode != NO_HDR && stream->id != 0 && (!dev->rdbk_buf[RDBK_L])) {
	2558	+ if (stream->to_stop_dma && (stream->dma_en & RKCIF_DMAEN_BY_ISP)) {
2319	2559	v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
2320		- return -EINVAL;
2321		- }
2322		-
2323		- if (stream->to_stop_dma) {
2324		- if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
2325		- v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
2326		- goto stop_dma;
2327		- } else {
2328		- v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
2329		- return -EINVAL;
2330		- }
	2560	+ goto stop_dma;
2331	2561	}
2332	2562
2333	2563	spin_lock_irqsave(&stream->vbq_lock, flags);
..	..	@@ -2347,8 +2577,8 @@
2347	2577	list_del(&stream->curr_buf->queue);
2348	2578	buffer = stream->curr_buf;
2349	2579	v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
2350		- "stream[%d] update curr_buf 0x%x\n",
2351		- stream->id, buffer->buff_addr[0]);
	2580	+ "stream[%d] update curr_buf 0x%x, buf idx %d\n",
	2581	+ stream->id, buffer->buff_addr[0], stream->curr_buf->vb.vb2_buf.index);
2352	2582	}
2353	2583	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
2354	2584	if (!stream->next_buf)
..	..	@@ -2368,14 +2598,14 @@
2368	2598	list_del(&stream->next_buf->queue);
2369	2599	buffer = stream->next_buf;
2370	2600	v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
2371		- "stream[%d] update next_buf 0x%x\n",
2372		- stream->id, buffer->buff_addr[0]);
	2601	+ "stream[%d] update next_buf 0x%x, buf idx %d\n",
	2602	+ stream->id, buffer->buff_addr[0], stream->next_buf->vb.vb2_buf.index);
2373	2603	}
2374	2604	}
2375	2605	}
2376		- } else if (!(stream->dma_en & RKCIF_DMAEN_BY_ISP)) {
	2606	+ } else {
2377	2607	buffer = NULL;
2378		- if (dummy_buf->vaddr) {
	2608	+ if (!(stream->cur_stream_mode & RKCIF_STREAM_MODE_TOISP) && dummy_buf->vaddr) {
2379	2609	if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
2380	2610	stream->curr_buf = NULL;
2381	2611	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
..	..	@@ -2386,12 +2616,11 @@
2386	2616	stream->next_buf = NULL;
2387	2617	}
2388	2618	}
2389		- } else if (stream->curr_buf && stream->next_buf &&
2390		- stream->curr_buf != stream->next_buf) {
2391		- if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2619	+ } else if (stream->curr_buf != stream->next_buf) {
	2620	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY && stream->next_buf) {
2392	2621	stream->curr_buf = stream->next_buf;
2393	2622	buffer = stream->next_buf;
2394		- } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2623	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY && stream->curr_buf) {
2395	2624	stream->next_buf = stream->curr_buf;
2396	2625	buffer = stream->curr_buf;
2397	2626	}
..	..	@@ -2407,19 +2636,37 @@
2407	2636	stream->frame_phase_cache = stream->frame_phase;
2408	2637
2409	2638	if (buffer) {
	2639	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	2640	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
2410	2641	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED &&
2411	2642	stream->frame_phase == CIF_CSI_FRAME1_READY) {
2412		- rkcif_write_register(dev, frm_addr_y,
2413		- buffer->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
2414		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2415		- rkcif_write_register(dev, frm_addr_uv,
2416		- buffer->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	2643	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2644	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2645	+ frm_addr_y,
	2646	+ frm_addr_uv,
	2647	+ buff_addr_y,
	2648	+ buff_addr_cbcr,
	2649	+ false);
	2650	+ } else {
	2651	+ rkcif_write_register(dev, frm_addr_y,
	2652	+ buff_addr_y + (channel->virtual_width / 2));
	2653	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2654	+ rkcif_write_register(dev, frm_addr_uv,
	2655	+ buff_addr_cbcr + (channel->virtual_width / 2));
	2656	+ }
2417	2657	} else {
2418		- rkcif_write_register(dev, frm_addr_y,
2419		- buffer->buff_addr[RKCIF_PLANE_Y]);
2420		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2421		- rkcif_write_register(dev, frm_addr_uv,
2422		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	2658	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2659	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2660	+ frm_addr_y,
	2661	+ frm_addr_uv,
	2662	+ buff_addr_y,
	2663	+ buff_addr_cbcr,
	2664	+ false);
	2665	+ } else {
	2666	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2667	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2668	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2669	+ }
2423	2670	}
2424	2671	if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
2425	2672	if (stream->buf_replace_cnt < 2)
..	..	@@ -2438,50 +2685,7 @@
2438	2685	}
2439	2686	}
2440	2687	if (dbufs)
2441		- rkcif_s_rx_buffer(dev, dbufs);
2442		- stream->buf_num_toisp--;
2443		- }
2444		- } else {
2445		- if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
2446		- rkcif_write_register(dev, frm_addr_y,
2447		- stream->curr_buf_toisp->dummy.dma_addr);
2448		- if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
2449		- stream->next_buf)
2450		- dbuf = stream->next_buf->dbuf;
2451		- else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
2452		- stream->curr_buf)
2453		- dbuf = stream->curr_buf->dbuf;
2454		-
2455		- if (dbuf) {
2456		- list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list)
2457		- if (dbufs->dbuf == dbuf)
2458		- break;
2459		- } else {
2460		- dbufs = &stream->curr_buf_toisp->dbufs;
2461		- }
2462		- rkcif_s_rx_buffer(dev, dbufs);
2463		- stream->buf_num_toisp--;
2464		- if (stream->curr_buf && stream->frame_phase == CIF_CSI_FRAME0_READY) {
2465		- stream->curr_buf = NULL;
2466		- if (stream->buf_replace_cnt)
2467		- stream->buf_replace_cnt--;
2468		- } else if (stream->next_buf && stream->frame_phase == CIF_CSI_FRAME1_READY) {
2469		- stream->next_buf = NULL;
2470		- if (stream->buf_replace_cnt)
2471		- stream->buf_replace_cnt--;
2472		- }
2473		- } else if (dummy_buf->vaddr) {
2474		- rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
2475		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2476		- rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
2477		- dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
2478		- dev->irq_stats.not_active_buf_cnt[stream->id]++;
2479		- } else {
2480		- ret = -EINVAL;
2481		- stream->curr_buf = NULL;
2482		- stream->next_buf = NULL;
2483		- dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
2484		- dev->irq_stats.not_active_buf_cnt[stream->id]++;
	2688	+ rkcif_s_rx_buffer(stream, dbufs);
2485	2689	}
2486	2690	}
2487	2691	spin_unlock_irqrestore(&stream->vbq_lock, flags);
..	..	@@ -2489,8 +2693,13 @@
2489	2693	stop_dma:
2490	2694	if (stream->buf_replace_cnt) {
2491	2695	spin_lock_irqsave(&stream->vbq_lock, flags);
2492		- rkcif_write_register(dev, frm_addr_y,
2493		- stream->curr_buf_toisp->dummy.dma_addr);
	2696	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2697	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	2698	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2699	+ frm_addr_y, 0,
	2700	+ buff_addr_y, 0, false);
	2701	+ else
	2702	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2494	2703	if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
2495	2704	stream->next_buf)
2496	2705	dbuf = stream->next_buf->dbuf;
..	..	@@ -2506,16 +2715,13 @@
2506	2715	dbufs = &stream->curr_buf_toisp->dbufs;
2507	2716	}
2508	2717	if (dbufs)
2509		- rkcif_s_rx_buffer(dev, dbufs);
2510		- stream->buf_num_toisp--;
	2718	+ rkcif_s_rx_buffer(stream, dbufs);
2511	2719
2512	2720	if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
2513	2721	stream->curr_buf) {
2514		- list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
2515	2722	stream->curr_buf = NULL;
2516	2723	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
2517	2724	stream->next_buf) {
2518		- list_add_tail(&stream->next_buf->queue, &stream->buf_head);
2519	2725	stream->next_buf = NULL;
2520	2726	}
2521	2727	stream->buf_replace_cnt--;
..	..	@@ -2587,8 +2793,10 @@
2587	2793	struct rkcif_device *dev = stream->cifdev;
2588	2794	struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2589	2795	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2796	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
2590	2797	struct rkcif_buffer *buffer = NULL;
2591	2798	u32 frm_addr_y, frm_addr_uv;
	2799	+ u32 buff_addr_y, buff_addr_cbcr;
2592	2800	int channel_id = stream->id;
2593	2801	int ret = 0;
2594	2802	unsigned long flags;
..	..	@@ -2619,16 +2827,35 @@
2619	2827	}
2620	2828	spin_unlock_irqrestore(&stream->vbq_lock, flags);
2621	2829	if (buffer) {
2622		- rkcif_write_register(dev, frm_addr_y,
2623		- buffer->buff_addr[RKCIF_PLANE_Y]);
2624		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2625		- rkcif_write_register(dev, frm_addr_uv,
2626		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	2830	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	2831	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	2832	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2833	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y,
	2834	+ frm_addr_uv,
	2835	+ buff_addr_y,
	2836	+ buff_addr_cbcr,
	2837	+ false);
	2838	+ } else {
	2839	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2840	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2841	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2842	+ }
2627	2843	} else {
2628	2844	if (dummy_buf->vaddr) {
2629		- rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
2630		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2631		- rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	2845	+ buff_addr_y = dummy_buf->dma_addr;
	2846	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2847	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2848	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2849	+ frm_addr_y,
	2850	+ frm_addr_uv,
	2851	+ buff_addr_y,
	2852	+ buff_addr_cbcr,
	2853	+ true);
	2854	+ } else {
	2855	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2856	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2857	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2858	+ }
2632	2859	} else {
2633	2860	if (dev->chip_id < CHIP_RK3588_CIF)
2634	2861	ret = -EINVAL;
..	..	@@ -2653,7 +2880,13 @@
2653	2880	int frame_phase = 0;
2654	2881
2655	2882	spin_lock_irqsave(&stream->vbq_lock, flags);
	2883	+ memset(&stream->toisp_buf_state, 0, sizeof(stream->toisp_buf_state));
2656	2884	if (!list_empty(&stream->rx_buf_head)) {
	2885	+ if (stream->curr_buf_toisp && stream->next_buf_toisp &&
	2886	+ stream->curr_buf_toisp != stream->next_buf_toisp)
	2887	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_ROTATE;
	2888	+ else
	2889	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_LOSS;
2657	2890	if (stream->line_int_cnt % 2) {
2658	2891	buffer = list_first_entry(&stream->rx_buf_head,
2659	2892	struct rkcif_rx_buffer, list);
..	..	@@ -2689,8 +2922,10 @@
2689	2922	"stream[%d] hold buf %x\n",
2690	2923	stream->id,
2691	2924	(u32)stream->next_buf_toisp->dummy.dma_addr);
	2925	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_THESAME;
2692	2926	} else {
2693	2927	ret = -EINVAL;
	2928	+ stream->toisp_buf_state.state = RKCIF_TOISP_BUF_LOSS;
2694	2929	}
2695	2930	}
2696	2931	if (buffer) {
..	..	@@ -3163,6 +3398,7 @@
3163	3398	struct csi_channel_info *channel)
3164	3399	{
3165	3400	struct rkcif_device *dev = stream->cifdev;
	3401	+ struct sditf_priv *priv = dev->sditf[0];
3166	3402	const struct cif_output_fmt *fmt;
3167	3403	u32 fourcc;
3168	3404	int vc = dev->channels[stream->id].vc;
..	..	@@ -3187,7 +3423,7 @@
3187	3423	channel->crop_st_x = stream->crop[CROP_SRC_ACT].left;
3188	3424
3189	3425	channel->crop_st_y = stream->crop[CROP_SRC_ACT].top;
3190		- if (dev->sditf_cnt > 1 && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	3426	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
3191	3427	channel->crop_st_y *= dev->sditf_cnt;
3192	3428	channel->width = stream->crop[CROP_SRC_ACT].width;
3193	3429	channel->height = stream->crop[CROP_SRC_ACT].height;
..	..	@@ -3197,7 +3433,7 @@
3197	3433	channel->crop_en = 0;
3198	3434	}
3199	3435
3200		- if (dev->sditf_cnt > 1 && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	3436	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
3201	3437	channel->height *= dev->sditf_cnt;
3202	3438
3203	3439	fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
..	..	@@ -3207,6 +3443,8 @@
3207	3443	return -EINVAL;
3208	3444	}
3209	3445
	3446	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	3447	+ channel->width /= channel->capture_info.multi_dev.dev_num;
3210	3448	/*
3211	3449	* for mipi or lvds, when enable compact, the virtual width of raw10/raw12
3212	3450	* needs aligned with :ALIGN(bits_per_pixel * width / 8, 8), if enable 16bit mode
..	..	@@ -3216,9 +3454,19 @@
3216	3454	if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
3217	3455	fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
3218	3456	fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
3219		- channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
	3457	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	3458	+ channel->virtual_width = ALIGN(channel->width * 2 * fmt->raw_bpp / 8, 256);
	3459	+ channel->left_virtual_width = channel->width * fmt->raw_bpp / 8;
	3460	+ } else {
	3461	+ channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
	3462	+ }
3220	3463	} else {
3221		- channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3464	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	3465	+ channel->virtual_width = ALIGN(channel->width * 2 * fmt->bpp[0] / 8, 8);
	3466	+ channel->left_virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3467	+ } else {
	3468	+ channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3469	+ }
3222	3470	}
3223	3471
3224	3472	if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 \|\| channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
..	..	@@ -3237,6 +3485,8 @@
3237	3485	channel->width *= 2;
3238	3486	}
3239	3487	channel->virtual_width *= 2;
	3488	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	3489	+ channel->left_virtual_width *= 2;
3240	3490	}
3241	3491	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
3242	3492	channel->virtual_width *= 2;
..	..	@@ -3387,6 +3637,7 @@
3387	3637	val &= ~CSI_HIGH_ALIGN;
3388	3638	rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
3389	3639
	3640	+ dev->intr_mask = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_INTEN);
3390	3641	return 0;
3391	3642	}
3392	3643
..	..	@@ -3585,15 +3836,18 @@
3585	3836
3586	3837	/config reg for rk3588/
3587	3838	static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
3588		- struct csi_channel_info *channel,
3589		- enum v4l2_mbus_type mbus_type, unsigned int mode)
	3839	+ struct csi_channel_info *channel,
	3840	+ enum v4l2_mbus_type mbus_type, unsigned int mode,
	3841	+ int index)
3590	3842	{
3591	3843	unsigned int val = 0x0;
3592	3844	struct rkcif_device *dev = stream->cifdev;
3593	3845	struct rkcif_stream *detect_stream = &dev->stream[0];
3594	3846	struct sditf_priv *priv = dev->sditf[0];
	3847	+ struct rkmodule_capture_info *capture_info = &channel->capture_info;
3595	3848	unsigned int wait_line = 0x3fff;
3596	3849	unsigned int dma_en = 0;
	3850	+ int offset = 0;
3597	3851
3598	3852	if (channel->id >= 4)
3599	3853	return -EINVAL;
..	..	@@ -3609,21 +3863,28 @@
3609	3863	CSI_DMA_END_INTSTAT(channel->id) \|
3610	3864	CSI_LINE_INTSTAT_V1(channel->id)));
3611	3865
3612		- rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3613		- CSI_START_INTEN(channel->id));
	3866	+ if (!(capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3867	+ index < capture_info->multi_dev.dev_num - 1)) {
3614	3868
3615		- if (priv && priv->mode.rdbk_mode && detect_stream->is_line_wake_up) {
3616	3869	rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3617		- CSI_LINE_INTEN_RK3588(channel->id));
3618		- wait_line = dev->wait_line;
3619		- }
3620		- rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
3621		- wait_line << 16 \| wait_line);
3622		- rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
3623		- wait_line << 16 \| wait_line);
	3870	+ CSI_START_INTEN(channel->id));
3624	3871
3625		- rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3626		- CSI_DMA_END_INTEN(channel->id));
	3872	+ if (priv && priv->mode.rdbk_mode && detect_stream->is_line_wake_up) {
	3873	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3874	+ CSI_LINE_INTEN_RK3588(channel->id));
	3875	+ wait_line = dev->wait_line;
	3876	+ }
	3877	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
	3878	+ wait_line << 16 \| wait_line);
	3879	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
	3880	+ wait_line << 16 \| wait_line);
	3881	+
	3882	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3883	+ CSI_DMA_END_INTEN(channel->id));
	3884	+
	3885	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3886	+ CSI_ALL_ERROR_INTEN_V1);
	3887	+ }
3627	3888	if (stream->cifdev->id_use_cnt == 0) {
3628	3889	val = CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(0x3) \|
3629	3890	CIF_MIPI_LVDS_SW_PRESS_ENABLE \|
..	..	@@ -3637,24 +3898,25 @@
3637	3898	else
3638	3899	val \|= CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
3639	3900	rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
3640		-
3641		- rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3642		- CSI_ALL_ERROR_INTEN_V1);
3643	3901	}
3644	3902	#if IS_ENABLED(CONFIG_CPU_RV1106)
3645	3903	if (channel->id == 1)
3646	3904	rv1106_sdmmc_get_lock();
3647	3905	#endif
	3906	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3907	+ priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE &&
	3908	+ (dev->hdr.hdr_mode == NO_HDR \|\|
	3909	+ (dev->hdr.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	3910	+ (dev->hdr.hdr_mode == HDR_X3 && stream->id == 2)))
	3911	+ offset = channel->capture_info.multi_dev.pixel_offset;
	3912	+
3648	3913	rkcif_write_register(dev, get_reg_index_of_id_ctrl1(channel->id),
3649		- channel->width \| (channel->height << 16));
	3914	+ (channel->width + offset) \| (channel->height << 16));
3650	3915
3651	3916	#if IS_ENABLED(CONFIG_CPU_RV1106)
3652	3917	if (channel->id == 1)
3653	3918	rv1106_sdmmc_put_lock();
3654	3919	#endif
3655		-
3656		- rkcif_write_register(dev, get_reg_index_of_frm0_y_vlw(channel->id),
3657		- channel->virtual_width);
3658	3920
3659	3921	if (channel->crop_en)
3660	3922	rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
..	..	@@ -3673,6 +3935,17 @@
3673	3935	rkcif_assign_new_buffer_pingpong_rockit(stream,
3674	3936	RKCIF_YUV_ADDR_STATE_INIT,
3675	3937	channel->id);
	3938	+
	3939	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3940	+ index == (capture_info->multi_dev.dev_num - 1) &&
	3941	+ priv && priv->mode.rdbk_mode != RKISP_VICAP_ONLINE)
	3942	+ rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
	3943	+ channel->crop_st_y << 16 \|
	3944	+ (channel->crop_st_x + capture_info->multi_dev.pixel_offset));
	3945	+
	3946	+ rkcif_write_register(dev, get_reg_index_of_frm0_y_vlw(channel->id),
	3947	+ channel->virtual_width);
	3948	+
3676	3949	if (stream->lack_buf_cnt == 2)
3677	3950	stream->dma_en = 0;
3678	3951
..	..	@@ -3735,7 +4008,25 @@
3735	4008	}
3736	4009	if (dev->chip_id >= CHIP_RV1106_CIF)
3737	4010	rkcif_modify_frame_skip_config(stream);
3738		- stream->cifdev->id_use_cnt++;
	4011	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4012	+ if (index == (capture_info->multi_dev.dev_num - 1))
	4013	+ stream->cifdev->id_use_cnt++;
	4014	+ } else {
	4015	+ stream->cifdev->id_use_cnt++;
	4016	+ }
	4017	+ if (!(capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	4018	+ index < capture_info->multi_dev.dev_num - 1)) {
	4019	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	4020	+ rkcif_assign_new_buffer_pingpong(stream,
	4021	+ RKCIF_YUV_ADDR_STATE_INIT,
	4022	+ channel->id);
	4023	+ else if (mode == RKCIF_STREAM_MODE_TOISP \|\|
	4024	+ mode == RKCIF_STREAM_MODE_TOISP_RDBK)
	4025	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	4026	+ RKCIF_YUV_ADDR_STATE_INIT,
	4027	+ channel->id);
	4028	+ }
	4029	+ dev->intr_mask = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_INTEN);
3739	4030	return 0;
3740	4031	}
3741	4032
..	..	@@ -3747,6 +4038,7 @@
3747	4038	enum v4l2_mbus_type mbus_type = active_sensor->mbus.type;
3748	4039	struct csi_channel_info *channel;
3749	4040	u32 ret = 0;
	4041	+ int i;
3750	4042
3751	4043	if (stream->state < RKCIF_STATE_STREAMING) {
3752	4044	stream->frame_idx = 0;
..	..	@@ -3785,10 +4077,18 @@
3785	4077	} else if (mode == RKCIF_STREAM_MODE_ROCKIT) {
3786	4078	stream->dma_en \|= RKCIF_DMAEN_BY_ROCKIT;
3787	4079	}
3788		- if (stream->cifdev->chip_id < CHIP_RK3588_CIF)
	4080	+ if (stream->cifdev->chip_id < CHIP_RK3588_CIF) {
3789	4081	rkcif_csi_channel_set(stream, channel, mbus_type);
3790		- else
3791		- rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode);
	4082	+ } else {
	4083	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4084	+ for (i = 0; i < channel->capture_info.multi_dev.dev_num; i++) {
	4085	+ dev->csi_host_idx = channel->capture_info.multi_dev.dev_idx[i];
	4086	+ rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode, i);
	4087	+ }
	4088	+ } else {
	4089	+ rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode, 0);
	4090	+ }
	4091	+ }
3792	4092	} else {
3793	4093	if (stream->cifdev->chip_id >= CHIP_RK3588_CIF) {
3794	4094	if (mode == RKCIF_STREAM_MODE_CAPTURE) {
..	..	@@ -3828,7 +4128,9 @@
3828	4128	struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
3829	4129	u32 val;
3830	4130	int id;
	4131	+ int i = 0;
3831	4132
	4133	+ stream->cifdev->id_use_cnt--;
3832	4134	if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
3833	4135	mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
3834	4136	mbus_cfg->type == V4L2_MBUS_CCP2) {
..	..	@@ -3840,7 +4142,14 @@
3840	4142	else
3841	4143	val &= ~LVDS_ENABLE_CAPTURE;
3842	4144
3843		- rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4145	+ if (cif_dev->channels[id].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4146	+ for (i = 0; i < cif_dev->channels[id].capture_info.multi_dev.dev_num; i++) {
	4147	+ cif_dev->csi_host_idx = cif_dev->channels[id].capture_info.multi_dev.dev_idx[i];
	4148	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4149	+ }
	4150	+ } else {
	4151	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4152	+ }
3844	4153
3845	4154	rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT,
3846	4155	CSI_START_INTSTAT(id) \|
..	..	@@ -3859,8 +4168,16 @@
3859	4168	if (stream->cifdev->id_use_cnt == 0) {
3860	4169	rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
3861	4170	~CSI_ALL_ERROR_INTEN_V1);
3862		- rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
3863		- ~CSI_ENABLE_CAPTURE);
	4171	+ if (cif_dev->channels[id].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4172	+ for (i = 0; i < cif_dev->channels[id].capture_info.multi_dev.dev_num; i++) {
	4173	+ cif_dev->csi_host_idx = cif_dev->channels[id].capture_info.multi_dev.dev_idx[i];
	4174	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
	4175	+ ~CSI_ENABLE_CAPTURE);
	4176	+ }
	4177	+ } else {
	4178	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
	4179	+ ~CSI_ENABLE_CAPTURE);
	4180	+ }
3864	4181	}
3865	4182	}
3866	4183
..	..	@@ -3876,7 +4193,6 @@
3876	4193	rkcif_config_dvp_pin(cif_dev, false);
3877	4194	}
3878	4195	}
3879		- stream->cifdev->id_use_cnt--;
3880	4196	stream->state = RKCIF_STATE_READY;
3881	4197	stream->dma_en = 0;
3882	4198	}
..	..	@@ -3955,7 +4271,7 @@
3955	4271	plane_fmt = &pixm->plane_fmt[i];
3956	4272	sizes[i] = plane_fmt->sizeimage / height * h;
3957	4273	}
3958		-
	4274	+ stream->total_buf_num = *num_buffers;
3959	4275	v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s count %d, size %d, extended(%d, %d)\n",
3960	4276	v4l2_type_names[queue->type], *num_buffers, sizes[0],
3961	4277	is_extended, extend_line->is_extended);
..	..	@@ -3973,6 +4289,8 @@
3973	4289	u32 frm_addr_y = 0, frm_addr_uv = 0;
3974	4290	u32 frm0_addr_y = 0, frm0_addr_uv = 0;
3975	4291	u32 frm1_addr_y = 0, frm1_addr_uv = 0;
	4292	+ u32 buff_addr_y = 0, buff_addr_cbcr = 0;
	4293	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
3976	4294	unsigned long flags;
3977	4295	int frame_phase = 0;
3978	4296	bool is_dual_update_buf = false;
..	..	@@ -4039,22 +4357,51 @@
4039	4357	}
4040	4358	if (buffer) {
4041	4359	if (is_dual_update_buf) {
4042		- rkcif_write_register(dev, frm0_addr_y,
4043		- buffer->buff_addr[RKCIF_PLANE_Y]);
4044		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
4045		- rkcif_write_register(dev, frm0_addr_uv,
4046		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
4047		- rkcif_write_register(dev, frm1_addr_y,
4048		- buffer->buff_addr[RKCIF_PLANE_Y]);
4049		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
4050		- rkcif_write_register(dev, frm1_addr_uv,
4051		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	4360	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	4361	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	4362	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4363	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4364	+ frm0_addr_y,
	4365	+ frm0_addr_uv,
	4366	+ buff_addr_y,
	4367	+ buff_addr_cbcr,
	4368	+ false);
	4369	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4370	+ frm1_addr_y,
	4371	+ frm1_addr_uv,
	4372	+ buff_addr_y,
	4373	+ buff_addr_cbcr,
	4374	+ false);
	4375	+ } else {
	4376	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	4377	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4378	+ rkcif_write_register(dev,
	4379	+ frm0_addr_uv,
	4380	+ buff_addr_cbcr);
	4381	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	4382	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4383	+ rkcif_write_register(dev,
	4384	+ frm1_addr_uv,
	4385	+ buff_addr_cbcr);
	4386	+ }
4052	4387	} else {
4053		- rkcif_write_register(dev, frm_addr_y,
4054		- buffer->buff_addr[RKCIF_PLANE_Y]);
4055		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
4056		- rkcif_write_register(dev, frm_addr_uv,
4057		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	4388	+
	4389	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	4390	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	4391	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4392	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4393	+ frm_addr_y,
	4394	+ frm_addr_uv,
	4395	+ buff_addr_y,
	4396	+ buff_addr_cbcr,
	4397	+ false);
	4398	+ } else {
	4399	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	4400	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4401	+ rkcif_write_register(dev,
	4402	+ frm_addr_uv,
	4403	+ buff_addr_cbcr);
	4404	+ }
4058	4405	}
4059	4406	}
4060	4407	} else {
..	..	@@ -4065,11 +4412,17 @@
4065	4412	if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
4066	4413	stream->curr_buf = list_first_entry(&stream->buf_head,
4067	4414	struct rkcif_buffer, queue);
	4415	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	4416	+ "%s %d, stream[%d] buf idx %d\n",
	4417	+ __func__, __LINE__, stream->id, stream->curr_buf->vb.vb2_buf.index);
4068	4418	if (stream->curr_buf)
4069	4419	list_del(&stream->curr_buf->queue);
4070	4420	} else if (stream->frame_phase_cache == CIF_CSI_FRAME1_READY) {
4071	4421	stream->next_buf = list_first_entry(&stream->buf_head,
4072	4422	struct rkcif_buffer, queue);
	4423	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev,
	4424	+ "%s %d, stream[%d] buf idx %d\n",
	4425	+ __func__, __LINE__, stream->id, stream->next_buf->vb.vb2_buf.index);
4073	4426	if (stream->next_buf)
4074	4427	list_del(&stream->next_buf->queue);
4075	4428	}
..	..	@@ -4098,6 +4451,7 @@
4098	4451	}
4099	4452	if (stream->lack_buf_cnt)
4100	4453	stream->lack_buf_cnt--;
	4454	+
4101	4455	} else {
4102	4456	v4l2_info(&dev->v4l2_dev, "%s %d, state %d, curr_buf %p, next_buf %p\n",
4103	4457	__func__, __LINE__, stream->state, stream->curr_buf, stream->next_buf);
..	..	@@ -4195,11 +4549,13 @@
4195	4549	list_add_tail(&dbufs->list, &stream->rx_buf_head_vicap);
4196	4550	}
4197	4551	if (stream->cifdev->workmode == RKCIF_WORKMODE_PINGPONG &&
4198		- stream->lack_buf_cnt)
	4552	+ stream->lack_buf_cnt &&
	4553	+ stream->cur_stream_mode & RKCIF_STREAM_MODE_CAPTURE)
4199	4554	rkcif_check_buffer_update_pingpong(stream, stream->id);
4200	4555	v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
4201	4556	"stream[%d] buf queue, index: %d, dma_addr 0x%x\n",
4202	4557	stream->id, vb->index, cifbuf->buff_addr[0]);
	4558	+ atomic_inc(&stream->buf_cnt);
4203	4559	}
4204	4560
4205	4561	void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num)
..	..	@@ -4207,11 +4563,54 @@
4207	4563	struct rkcif_rx_buffer *buf;
4208	4564	struct rkcif_device *dev = stream->cifdev;
4209	4565	struct sditf_priv *priv = dev->sditf[0];
	4566	+ struct v4l2_subdev *sd;
4210	4567	int i = 0;
4211	4568	unsigned long flags;
	4569	+ phys_addr_t resmem_free_start;
	4570	+ phys_addr_t resmem_free_end;
	4571	+ u32 share_head_size = 0;
4212	4572
4213	4573	if (!priv)
4214	4574	return;
	4575	+
	4576	+ sd = get_rkisp_sd(dev->sditf[0]);
	4577	+ if (!sd)
	4578	+ return;
	4579	+
	4580	+ if (dev->is_rtt_suspend && dev->is_thunderboot) {
	4581	+ stream->curr_buf_toisp = NULL;
	4582	+ stream->next_buf_toisp = NULL;
	4583	+ INIT_LIST_HEAD(&stream->rx_buf_head);
	4584	+
	4585	+ for (i = 0; i < buf_num; i++) {
	4586	+ buf = &stream->rx_buf[i];
	4587	+ if (buf->dbufs.is_init)
	4588	+ v4l2_subdev_call(sd, core, ioctl,
	4589	+ RKISP_VICAP_CMD_RX_BUFFER_FREE, &buf->dbufs);
	4590	+ buf->dummy.is_free = true;
	4591	+ }
	4592	+
	4593	+ if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
	4594	+ share_head_size = dev->thunderboot_sensor_num * sizeof(struct rkisp32_thunderboot_resmem_head);
	4595	+ if (share_head_size != dev->share_mem_size)
	4596	+ v4l2_info(&stream->cifdev->v4l2_dev,
	4597	+ "share mem head error, rtt head size %d, arm head size %d\n",
	4598	+ dev->share_mem_size, share_head_size);
	4599	+ resmem_free_start = dev->resmem_pa + share_head_size + dev->nr_buf_size;
	4600	+ resmem_free_end = dev->resmem_pa + dev->resmem_size;
	4601	+ v4l2_info(&stream->cifdev->v4l2_dev,
	4602	+ "free reserved mem start 0x%x, end 0x%x, share_head_size 0x%x, nr_buf_size 0x%x\n",
	4603	+ (u32)resmem_free_start, (u32)resmem_free_end, share_head_size, dev->nr_buf_size);
	4604	+ free_reserved_area(phys_to_virt(resmem_free_start),
	4605	+ phys_to_virt(resmem_free_end),
	4606	+ -1, "rkisp_thunderboot");
	4607	+ }
	4608	+ atomic_set(&stream->buf_cnt, 0);
	4609	+ stream->total_buf_num = 0;
	4610	+ stream->rx_buf_num = 0;
	4611	+
	4612	+ return;
	4613	+ }
4215	4614
4216	4615	spin_lock_irqsave(&stream->vbq_lock, flags);
4217	4616	stream->curr_buf_toisp = NULL;
..	..	@@ -4225,11 +4624,17 @@
4225	4624	buf = &stream->rx_buf[i];
4226	4625	if (buf->dummy.is_free)
4227	4626	continue;
	4627	+ if (buf->dbufs.is_init)
	4628	+ v4l2_subdev_call(sd, core, ioctl,
	4629	+ RKISP_VICAP_CMD_RX_BUFFER_FREE, &buf->dbufs);
4228	4630	if (!dev->is_thunderboot)
4229	4631	rkcif_free_buffer(dev, &buf->dummy);
4230	4632	else
4231	4633	list_add_tail(&buf->list_free, &priv->buf_free_list);
	4634	+ atomic_dec(&stream->buf_cnt);
	4635	+ stream->total_buf_num--;
4232	4636	}
	4637	+ stream->rx_buf_num = 0;
4233	4638
4234	4639	if (dev->is_thunderboot) {
4235	4640	spin_unlock_irqrestore(&dev->buffree_lock, flags);
..	..	@@ -4240,6 +4645,7 @@
4240	4645	"free rx_buf, buf_num %d\n", buf_num);
4241	4646	}
4242	4647
	4648	+static void rkcif_get_resmem_head(struct rkcif_device *cif_dev);
4243	4649	int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num)
4244	4650	{
4245	4651	struct rkcif_device *dev = stream->cifdev;
..	..	@@ -4287,10 +4693,12 @@
4287	4693	dummy->is_need_vaddr = true;
4288	4694	dummy->is_need_dbuf = true;
4289	4695	if (dev->is_thunderboot) {
	4696	+ if (i == 0)
	4697	+ rkcif_get_resmem_head(dev);
4290	4698	buf->buf_idx = i;
4291	4699	ret = rkcif_alloc_reserved_mem_buf(dev, buf);
4292	4700	if (ret) {
4293		- priv->buf_num = i;
	4701	+ stream->rx_buf_num = i;
4294	4702	v4l2_info(&dev->v4l2_dev,
4295	4703	"reserved mem support alloc buf num %d, require buf num %d\n",
4296	4704	i, buf_num);
..	..	@@ -4303,7 +4711,7 @@
4303	4711	} else {
4304	4712	ret = rkcif_alloc_buffer(dev, dummy);
4305	4713	if (ret) {
4306		- priv->buf_num = i;
	4714	+ stream->rx_buf_num = i;
4307	4715	v4l2_info(&dev->v4l2_dev,
4308	4716	"alloc buf num %d, require buf num %d\n",
4309	4717	i, buf_num);
..	..	@@ -4319,16 +4727,17 @@
4319	4727	buf->dbufs.is_uncompact = false;
4320	4728	else
4321	4729	buf->dbufs.is_uncompact = true;
4322		- if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE && i == 0) {
	4730	+ if (priv && i == 0) {
4323	4731	buf->dbufs.is_first = true;
4324		- rkcif_s_rx_buffer(dev, &buf->dbufs);
4325		- stream->buf_num_toisp--;
	4732	+ if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	4733	+ rkcif_s_rx_buffer(stream, &buf->dbufs);
4326	4734	}
4327	4735	i++;
4328	4736	if (!dev->is_thunderboot && i >= buf_num) {
	4737	+ stream->rx_buf_num = buf_num;
4329	4738	break;
4330	4739	} else if (i >= RKISP_VICAP_BUF_CNT_MAX) {
4331		- priv->buf_num = i;
	4740	+ stream->rx_buf_num = i;
4332	4741	v4l2_info(&dev->v4l2_dev,
4333	4742	"reserved mem alloc buf num %d\n", i);
4334	4743	break;
..	..	@@ -4337,8 +4746,9 @@
4337	4746	"init rx_buf,dma_addr 0x%llx size: 0x%x\n",
4338	4747	(u64)dummy->dma_addr, pixm->plane_fmt[0].sizeimage);
4339	4748	}
4340		- if (priv->buf_num) {
4341		- stream->buf_num_toisp = priv->buf_num;
	4749	+ if (stream->rx_buf_num) {
	4750	+ stream->total_buf_num = stream->rx_buf_num;
	4751	+ atomic_set(&stream->buf_cnt, stream->rx_buf_num);
4342	4752	return 0;
4343	4753	} else {
4344	4754	return -EINVAL;
..	..	@@ -4352,6 +4762,7 @@
4352	4762	struct rkcif_dummy_buffer *dummy_buf = &hw->dummy_buf;
4353	4763	struct rkcif_device *tmp_dev = NULL;
4354	4764	struct v4l2_subdev_frame_interval_enum fie;
	4765	+ struct v4l2_subdev_format fmt;
4355	4766	u32 max_size = 0;
4356	4767	u32 size = 0;
4357	4768	int ret = 0;
..	..	@@ -4369,7 +4780,9 @@
4369	4780	pad, enum_frame_interval,
4370	4781	NULL, &fie);
4371	4782	if (!ret) {
4372		- if (fie.code == MEDIA_BUS_FMT_RGB888_1X24)
	4783	+ if (fie.code == MEDIA_BUS_FMT_RGB888_1X24 \|\|
	4784	+ fie.code == MEDIA_BUS_FMT_BGR888_1X24 \|\|
	4785	+ fie.code == MEDIA_BUS_FMT_GBR888_1X24)
4373	4786	size = fie.width * fie.height * 3;
4374	4787	else
4375	4788	size = fie.width * fie.height * 2;
..	..	@@ -4386,6 +4799,23 @@
4386	4799	continue;
4387	4800	}
4388	4801	}
	4802	+
	4803	+ if (max_size == 0 && dev->terminal_sensor.sd) {
	4804	+ fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	4805	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	4806	+ pad, get_fmt, NULL, &fmt);
	4807	+ if (!ret) {
	4808	+ if (fmt.format.code == MEDIA_BUS_FMT_RGB888_1X24 \|\|
	4809	+ fmt.format.code == MEDIA_BUS_FMT_BGR888_1X24 \|\|
	4810	+ fmt.format.code == MEDIA_BUS_FMT_GBR888_1X24)
	4811	+ size = fmt.format.width * fmt.format.height * 3;
	4812	+ else
	4813	+ size = fmt.format.width * fmt.format.height * 2;
	4814	+ if (size > max_size)
	4815	+ max_size = size;
	4816	+ }
	4817	+ }
	4818	+
4389	4819	dummy_buf->size = max_size;
4390	4820
4391	4821	dummy_buf->is_need_vaddr = true;
..	..	@@ -4583,7 +5013,7 @@
4583	5013	spin_lock_irqsave(&stream->fps_lock, flags);
4584	5014	fs_time = stream->readout.fs_timestamp;
4585	5015	spin_unlock_irqrestore(&stream->fps_lock, flags);
4586		- cur_time = ktime_get_ns();
	5016	+ cur_time = rkcif_time_get_ns(dev);
4587	5017	if (cur_time > fs_time &&
4588	5018	cur_time - fs_time < (frame_time_ns - 10000000)) {
4589	5019	spin_lock_irqsave(&stream->vbq_lock, flags);
..	..	@@ -4621,14 +5051,16 @@
4621	5051	} else if (mode == RKCIF_STREAM_MODE_CAPTURE && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
4622	5052	//only stop dma
4623	5053	stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	5054	+ stream->is_wait_dma_stop = true;
4624	5055	wait_event_timeout(stream->wq_stopped,
4625		- stream->to_stop_dma != RKCIF_DMAEN_BY_VICAP,
	5056	+ !stream->is_wait_dma_stop,
4626	5057	msecs_to_jiffies(1000));
4627	5058	} else if (mode == RKCIF_STREAM_MODE_TOISP && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
4628	5059	//only stop dma
4629	5060	stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	5061	+ stream->is_wait_dma_stop = true;
4630	5062	wait_event_timeout(stream->wq_stopped,
4631		- stream->to_stop_dma != RKCIF_DMAEN_BY_ISP,
	5063	+ !stream->is_wait_dma_stop,
4632	5064	msecs_to_jiffies(1000));
4633	5065	}
4634	5066	if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE) {
..	..	@@ -4641,12 +5073,12 @@
4641	5073	list_add_tail(&stream->next_buf->queue, &stream->buf_head);
4642	5074	spin_unlock_irqrestore(&stream->vbq_lock, flags);
4643	5075
4644		- stream->curr_buf = NULL;
4645		- stream->next_buf = NULL;
4646		-
4647	5076	if (dev->hdr.hdr_mode == HDR_X2 \|\|
4648	5077	dev->hdr.hdr_mode == HDR_X3)
4649	5078	rkcif_release_rdbk_buf(stream);
	5079	+
	5080	+ stream->curr_buf = NULL;
	5081	+ stream->next_buf = NULL;
4650	5082
4651	5083	rkcif_rx_buffer_free(stream);
4652	5084	list_for_each_entry(buf, &stream->buf_head, queue) {
..	..	@@ -4664,6 +5096,8 @@
4664	5096	vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
4665	5097	}
4666	5098	}
	5099	+ stream->total_buf_num = 0;
	5100	+ atomic_set(&stream->buf_cnt, 0);
4667	5101	stream->lack_buf_cnt = 0;
4668	5102	stream->dma_en &= ~RKCIF_DMAEN_BY_VICAP;
4669	5103	}
..	..	@@ -4694,8 +5128,10 @@
4694	5128	}
4695	5129	}
4696	5130	mutex_unlock(&hw_dev->dev_lock);
4697		- if (dev->can_be_reset && dev->chip_id >= CHIP_RK3588_CIF)
	5131	+ if (dev->can_be_reset && dev->chip_id >= CHIP_RK3588_CIF) {
4698	5132	rkcif_do_soft_reset(dev);
	5133	+ atomic_set(&dev->streamoff_cnt, 0);
	5134	+ }
4699	5135	if (dev->can_be_reset && can_reset) {
4700	5136	dev->can_be_reset = false;
4701	5137	dev->reset_work_cancel = true;
..	..	@@ -4704,10 +5140,12 @@
4704	5140	dev->wait_line = 0;
4705	5141	stream->is_line_wake_up = false;
4706	5142	}
4707		- tasklet_disable(&stream->vb_done_tasklet);
	5143	+ if (can_reset && hw_dev->dummy_buf.vaddr)
	5144	+ rkcif_destroy_dummy_buf(stream);
4708	5145	}
4709		- if (can_reset && hw_dev->dummy_buf.vaddr)
4710		- rkcif_destroy_dummy_buf(stream);
	5146	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	5147	+ tasklet_disable(&stream->vb_done_tasklet);
	5148	+
4711	5149	stream->cur_stream_mode &= ~mode;
4712	5150	INIT_LIST_HEAD(&stream->vb_done_list);
4713	5151	v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished, dma_en 0x%x\n", stream->id, stream->dma_en);
..	..	@@ -4981,6 +5419,7 @@
4981	5419	stream->crop_mask \|= CROP_SRC_SENSOR_MASK;
4982	5420	dev->terminal_sensor.selection = input_sel;
4983	5421	} else {
	5422	+ stream->crop_mask &= ~CROP_SRC_SENSOR_MASK;
4984	5423	dev->terminal_sensor.selection.r = dev->terminal_sensor.raw_rect;
4985	5424	}
4986	5425	}
..	..	@@ -5001,8 +5440,10 @@
5001	5440	stream->crop[CROP_SRC_ACT].top = stream->crop[CROP_SRC_USR].top +
5002	5441	stream->crop[CROP_SRC_SENSOR].top;
5003	5442	}
5004		- } else {
	5443	+ } else if (stream->crop_mask & CROP_SRC_SENSOR_MASK) {
5005	5444	stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_SENSOR];
	5445	+ } else {
	5446	+ stream->crop[CROP_SRC_ACT] = dev->terminal_sensor.raw_rect;
5006	5447	}
5007	5448	}
5008	5449
..	..	@@ -5018,9 +5459,9 @@
5018	5459	struct v4l2_rect input, *crop;
5019	5460
5020	5461	if (dev->terminal_sensor.sd) {
5021		- stream->cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
5022		- &input, stream->id,
5023		- &dev->channels[stream->id]);
	5462	+ stream->cif_fmt_in = rkcif_get_input_fmt(dev,
	5463	+ &input, stream->id,
	5464	+ &dev->channels[stream->id]);
5024	5465	if (!stream->cif_fmt_in) {
5025	5466	v4l2_err(v4l2_dev, "Input fmt is invalid\n");
5026	5467	return -EINVAL;
..	..	@@ -5548,6 +5989,7 @@
5548	5989	rkcif_write_register(dev, CIF_REG_DVP_CTRL,
5549	5990	AXI_BURST_16 \| workmode \| ENABLE_CAPTURE);
5550	5991	}
	5992	+ dev->intr_mask = rkcif_read_register(dev, CIF_REG_DVP_INTSTAT);
5551	5993	#if IS_ENABLED(CONFIG_CPU_RV1106)
5552	5994	rv1106_sdmmc_put_lock();
5553	5995	#endif
..	..	@@ -5562,6 +6004,7 @@
5562	6004	{
5563	6005	struct rkcif_hw *hw = cifdev->hw_dev;
5564	6006	struct rkcif_device *dev;
	6007	+ struct sditf_priv *priv;
5565	6008	int i = 0, j = 0;
5566	6009	int ret = 0;
5567	6010	int count = 0;
..	..	@@ -5610,12 +6053,12 @@
5610	6053	else
5611	6054	sync_cfg.group = 0;
5612	6055	}
	6056	+ cifdev->sync_cfg = sync_cfg;
5613	6057	if (sync_cfg.type == NO_SYNC_MODE \|\|
5614	6058	hw->sync_config[sync_cfg.group].is_attach) {
5615	6059	mutex_unlock(&hw->dev_lock);
5616	6060	return;
5617	6061	}
5618		- cifdev->sync_cfg = sync_cfg;
5619	6062
5620	6063	sync_config = &hw->sync_config[sync_cfg.group];
5621	6064	memset(sync_config, 0, sizeof(struct rkcif_multi_sync_config));
..	..	@@ -5639,26 +6082,31 @@
5639	6082	else
5640	6083	sync_cfg.group = 0;
5641	6084	} else {
5642		- for (j = 0; j < dev->sditf_cnt; j++) {
5643		- ret \|= v4l2_subdev_call(dev->sditf[j]->sensor_sd,
5644		- core, ioctl,
5645		- RKMODULE_GET_SYNC_MODE,
5646		- &sync_type);
5647		- if (!ret && sync_type)
5648		- break;
	6085	+ priv = dev->sditf[0];
	6086	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	6087	+ for (j = 0; j < dev->sditf_cnt; j++) {
	6088	+ ret \|= v4l2_subdev_call(dev->sditf[j]->sensor_sd,
	6089	+ core, ioctl,
	6090	+ RKMODULE_GET_SYNC_MODE,
	6091	+ &sync_type);
	6092	+ if (!ret && sync_type) {
	6093	+ priv = dev->sditf[j];
	6094	+ break;
	6095	+ }
	6096	+ }
	6097	+ if (!ret)
	6098	+ sync_cfg.type = sync_type;
	6099	+ else
	6100	+ sync_cfg.type = NO_SYNC_MODE;
	6101	+ ret = v4l2_subdev_call(priv->sensor_sd,
	6102	+ core, ioctl,
	6103	+ RKMODULE_GET_GROUP_ID,
	6104	+ &sync_group);
	6105	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	6106	+ sync_cfg.group = sync_group;
	6107	+ else
	6108	+ sync_cfg.group = 0;
5649	6109	}
5650		- if (!ret)
5651		- sync_cfg.type = sync_type;
5652		- else
5653		- sync_cfg.type = NO_SYNC_MODE;
5654		- ret = v4l2_subdev_call(dev->sditf[j]->sensor_sd,
5655		- core, ioctl,
5656		- RKMODULE_GET_GROUP_ID,
5657		- &sync_group);
5658		- if (!ret && sync_group < RKCIF_MAX_GROUP)
5659		- sync_cfg.group = sync_group;
5660		- else
5661		- sync_cfg.group = 0;
5662	6110	}
5663	6111	if (sync_cfg.group == cifdev->sync_cfg.group) {
5664	6112	if (sync_cfg.type == EXTERNAL_MASTER_MODE) {
..	..	@@ -5681,6 +6129,11 @@
5681	6129	sync_config->sync_mask \|= BIT(dev->csi_host_idx);
5682	6130	}
5683	6131	dev->sync_cfg = sync_cfg;
	6132	+ } else {
	6133	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	6134	+ core, ioctl,
	6135	+ RKMODULE_GET_SYNC_MODE,
	6136	+ &sync_type);
5684	6137	}
5685	6138	}
5686	6139	if (sync_config->int_master.count == 1) {
..	..	@@ -5714,15 +6167,19 @@
5714	6167	struct rkcif_hw *hw_dev = dev->hw_dev;
5715	6168	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
5716	6169	struct rkcif_sensor_info *sensor_info = dev->active_sensor;
5717		- struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
	6170	+ struct rkcif_sensor_info *terminal_sensor = NULL;
5718	6171	struct rkmodule_hdr_cfg hdr_cfg;
	6172	+ struct rkcif_csi_info csi_info = {0};
5719	6173	int rkmodule_stream_seq = RKMODULE_START_STREAM_DEFAULT;
5720	6174	int ret;
	6175	+ int i = 0;
	6176	+ u32 skip_frame = 0;
5721	6177
5722	6178	v4l2_info(&dev->v4l2_dev, "stream[%d] start streaming\n", stream->id);
5723	6179
5724	6180	rkcif_attach_sync_mode(dev);
5725	6181	mutex_lock(&dev->stream_lock);
	6182	+
5726	6183	if ((stream->cur_stream_mode & RKCIF_STREAM_MODE_CAPTURE) == mode) {
5727	6184	ret = -EBUSY;
5728	6185	v4l2_err(v4l2_dev, "stream in busy state\n");
..	..	@@ -5735,7 +6192,7 @@
5735	6192	else
5736	6193	stream->is_line_inten = false;
5737	6194
5738		- if (dev->active_sensor) {
	6195	+ if (!dev->active_sensor) {
5739	6196	ret = rkcif_update_sensor_info(stream);
5740	6197	if (ret < 0) {
5741	6198	v4l2_err(v4l2_dev,
..	..	@@ -5744,7 +6201,7 @@
5744	6201	goto out;
5745	6202	}
5746	6203	}
5747		-
	6204	+ terminal_sensor = &dev->terminal_sensor;
5748	6205	if (terminal_sensor->sd) {
5749	6206	ret = v4l2_subdev_call(terminal_sensor->sd,
5750	6207	core, ioctl,
..	..	@@ -5775,6 +6232,39 @@
5775	6232	goto destroy_buf;
5776	6233
5777	6234	mutex_lock(&hw_dev->dev_lock);
	6235	+ if (atomic_read(&dev->pipe.stream_cnt) == 0 &&
	6236	+ dev->active_sensor &&
	6237	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	6238	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	6239	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)) {
	6240	+ if (dev->channels[0].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	6241	+ csi_info.csi_num = dev->channels[0].capture_info.multi_dev.dev_num;
	6242	+ if (csi_info.csi_num > RKCIF_MAX_CSI_NUM) {
	6243	+ v4l2_err(v4l2_dev,
	6244	+ "csi num %d, max %d\n",
	6245	+ csi_info.csi_num, RKCIF_MAX_CSI_NUM);
	6246	+ goto out;
	6247	+ }
	6248	+ for (i = 0; i < csi_info.csi_num; i++) {
	6249	+ csi_info.csi_idx[i] = dev->channels[0].capture_info.multi_dev.dev_idx[i];
	6250	+ if (dev->hw_dev->is_rk3588s2)
	6251	+ v4l2_info(v4l2_dev, "rk3588s2 combine mode attach to mipi%d\n",
	6252	+ csi_info.csi_idx[i]);
	6253	+ }
	6254	+ } else {
	6255	+ csi_info.csi_num = 1;
	6256	+ dev->csi_host_idx = dev->csi_host_idx_def;
	6257	+ csi_info.csi_idx[0] = dev->csi_host_idx;
	6258	+ }
	6259	+ ret = v4l2_subdev_call(dev->active_sensor->sd,
	6260	+ core, ioctl,
	6261	+ RKCIF_CMD_SET_CSI_IDX,
	6262	+ &csi_info);
	6263	+ if (ret)
	6264	+ v4l2_err(&dev->v4l2_dev, "set csi idx %d fail\n", dev->csi_host_idx);
	6265	+
	6266	+ }
	6267	+
5778	6268	if (((dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_BT656) \|\|
5779	6269	dev->is_use_dummybuf) &&
5780	6270	(!dev->hw_dev->dummy_buf.vaddr) &&
..	..	@@ -5788,8 +6278,10 @@
5788	6278	}
5789	6279	mutex_unlock(&hw_dev->dev_lock);
5790	6280
5791		- if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
	6281	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
5792	6282	tasklet_enable(&stream->vb_done_tasklet);
	6283	+
	6284	+ if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
5793	6285	ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
5794	6286	if (ret < 0) {
5795	6287	v4l2_err(v4l2_dev, "open cif pipeline failed %d\n",
..	..	@@ -5807,8 +6299,17 @@
5807	6299	rkmodule_stream_seq == RKMODULE_START_STREAM_FRONT) {
5808	6300	ret = dev->pipe.set_stream(&dev->pipe, true);
5809	6301	if (ret < 0)
5810		- goto runtime_put;
	6302	+ goto destroy_buf;
5811	6303	}
	6304	+ ret = v4l2_subdev_call(terminal_sensor->sd,
	6305	+ core, ioctl,
	6306	+ RKMODULE_GET_SKIP_FRAME,
	6307	+ &skip_frame);
	6308	+ if (!ret && skip_frame < RKCIF_SKIP_FRAME_MAX)
	6309	+ stream->skip_frame = skip_frame;
	6310	+ else
	6311	+ stream->skip_frame = 0;
	6312	+ stream->cur_skip_frame = stream->skip_frame;
5812	6313	}
5813	6314	if (dev->chip_id >= CHIP_RK1808_CIF) {
5814	6315	if (dev->active_sensor &&
..	..	@@ -5823,7 +6324,7 @@
5823	6324	}
5824	6325
5825	6326	if (ret < 0)
5826		- goto runtime_put;
	6327	+ goto destroy_buf;
5827	6328
5828	6329	if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
5829	6330	ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
..	..	@@ -5869,15 +6370,19 @@
5869	6370	rkcif_stream_stop(stream);
5870	6371	pipe_stream_off:
5871	6372	dev->pipe.set_stream(&dev->pipe, false);
5872		-runtime_put:
5873		- pm_runtime_put_sync(dev->dev);
	6373	+
5874	6374	destroy_buf:
5875		- if (stream->next_buf)
5876		- vb2_buffer_done(&stream->next_buf->vb.vb2_buf,
5877		- VB2_BUF_STATE_QUEUED);
	6375	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	6376	+ tasklet_disable(&stream->vb_done_tasklet);
5878	6377	if (stream->curr_buf)
5879		- vb2_buffer_done(&stream->curr_buf->vb.vb2_buf,
5880		- VB2_BUF_STATE_QUEUED);
	6378	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	6379	+ if (stream->next_buf &&
	6380	+ stream->next_buf != stream->curr_buf)
	6381	+ list_add_tail(&stream->next_buf->queue, &stream->buf_head);
	6382	+
	6383	+ stream->curr_buf = NULL;
	6384	+ stream->next_buf = NULL;
	6385	+ atomic_set(&stream->buf_cnt, 0);
5881	6386	while (!list_empty(&stream->buf_head)) {
5882	6387	struct rkcif_buffer *buf;
5883	6388
..	..	@@ -5942,6 +6447,7 @@
5942	6447	bool try)
5943	6448	{
5944	6449	struct rkcif_device *dev = stream->cifdev;
	6450	+ struct sditf_priv *priv = dev->sditf[0];
5945	6451	const struct cif_output_fmt *fmt;
5946	6452	const struct cif_input_fmt *cif_fmt_in = NULL;
5947	6453	struct v4l2_rect input_rect;
..	..	@@ -5949,6 +6455,7 @@
5949	6455	u32 xsubs = 1, ysubs = 1, i;
5950	6456	struct rkmodule_hdr_cfg hdr_cfg;
5951	6457	struct rkcif_extend_info *extend_line = &stream->extend_line;
	6458	+ struct csi_channel_info *channel_info = &dev->channels[stream->id];
5952	6459	int ret;
5953	6460
5954	6461	for (i = 0; i < RKCIF_MAX_PLANE; i++)
..	..	@@ -5962,9 +6469,9 @@
5962	6469	input_rect.height = RKCIF_DEFAULT_HEIGHT;
5963	6470
5964	6471	if (dev->terminal_sensor.sd) {
5965		- cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
5966		- &input_rect, stream->id,
5967		- &dev->channels[stream->id]);
	6472	+ cif_fmt_in = rkcif_get_input_fmt(dev,
	6473	+ &input_rect, stream->id,
	6474	+ channel_info);
5968	6475	stream->cif_fmt_in = cif_fmt_in;
5969	6476	} else {
5970	6477	v4l2_err(&stream->cifdev->v4l2_dev,
..	..	@@ -6006,8 +6513,9 @@
6006	6513
6007	6514	planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
6008	6515
6009		- if (cif_fmt_in && (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 \|\|
6010		- cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8))
	6516	+ if (cif_fmt_in &&
	6517	+ (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 \|\|
	6518	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8))
6011	6519	stream->crop_enable = false;
6012	6520
6013	6521	for (i = 0; i < planes; i++) {
..	..	@@ -6032,7 +6540,7 @@
6032	6540	}
6033	6541	}
6034	6542
6035		- if (dev->sditf_cnt > 1 && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	6543	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
6036	6544	height *= dev->sditf_cnt;
6037	6545
6038	6546	extend_line->pixm.height = height + RKMODULE_EXTEND_LINE;
..	..	@@ -6042,8 +6550,9 @@
6042	6550	* to optimize reading and writing of ddr, aliged with 256.
6043	6551	*/
6044	6552	if (fmt->fmt_type == CIF_FMT_TYPE_RAW &&
6045		- (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
6046		- stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8)) {
	6553	+ cif_fmt_in &&
	6554	+ (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
	6555	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8)) {
6047	6556	stream->is_compact = false;
6048	6557	}
6049	6558
..	..	@@ -6157,6 +6666,7 @@
6157	6666
6158	6667	stream->is_high_align = false;
6159	6668	stream->is_finish_stop_dma = false;
	6669	+ stream->is_wait_dma_stop = false;
6160	6670
6161	6671	if (dev->chip_id == CHIP_RV1126_CIF \|\|
6162	6672	dev->chip_id == CHIP_RV1126_CIF_LITE)
..	..	@@ -6184,6 +6694,11 @@
6184	6694	stream->buf_owner = 0;
6185	6695	stream->buf_replace_cnt = 0;
6186	6696	stream->is_stop_capture = false;
	6697	+ stream->is_single_cap = false;
	6698	+ atomic_set(&stream->buf_cnt, 0);
	6699	+ stream->rx_buf_num = 0;
	6700	+ init_completion(&stream->stop_complete);
	6701	+ stream->is_wait_stop_complete = false;
6187	6702	}
6188	6703
6189	6704	static int rkcif_fh_open(struct file *filp)
..	..	@@ -6329,9 +6844,9 @@
6329	6844	input_rect.height = RKCIF_DEFAULT_HEIGHT;
6330	6845
6331	6846	if (dev->terminal_sensor.sd)
6332		- get_input_fmt(dev->terminal_sensor.sd,
6333		- &input_rect, stream->id,
6334		- &csi_info);
	6847	+ rkcif_get_input_fmt(dev,
	6848	+ &input_rect, stream->id,
	6849	+ &csi_info);
6335	6850
6336	6851	if (dev->hw_dev->adapt_to_usbcamerahal) {
6337	6852	fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
..	..	@@ -6410,7 +6925,7 @@
6410	6925	return -EINVAL;
6411	6926
6412	6927	if (dev->terminal_sensor.sd) {
6413		- cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
	6928	+ cif_fmt_in = rkcif_get_input_fmt(dev,
6414	6929	&input_rect, stream->id,
6415	6930	&dev->channels[stream->id]);
6416	6931	stream->cif_fmt_in = cif_fmt_in;
..	..	@@ -6769,8 +7284,18 @@
6769	7284	skip_n);
6770	7285	}
6771	7286
	7287	+static bool rkcif_check_can_be_online(struct rkcif_device *cif_dev)
	7288	+{
	7289	+ if (cif_dev->sditf[0] == NULL \|\| cif_dev->sditf[0]->mode.name == NULL \|\|
	7290	+ (cif_dev->chip_id == CHIP_RV1106_CIF &&
	7291	+ strstr(cif_dev->sditf[0]->mode.name, "unite")))
	7292	+ return false;
	7293	+ return true;
	7294	+}
	7295	+
6772	7296	static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
6773	7297	enum rkmodule_reset_src reset_src);
	7298	+static bool rkcif_check_single_dev_stream_on(struct rkcif_hw *hw);
6774	7299
6775	7300	static long rkcif_ioctl_default(struct file file, void fh,
6776	7301	bool valid_prio, unsigned int cmd, void *arg)
..	..	@@ -6782,6 +7307,13 @@
6782	7307	struct csi_channel_info csi_info;
6783	7308	struct rkcif_fps fps;
6784	7309	int reset_src;
	7310	+ struct rkcif_quick_stream_param *stream_param;
	7311	+ bool is_single_dev = false;
	7312	+ struct v4l2_subdev *sd;
	7313	+ int ret = -EINVAL;
	7314	+ int i = 0;
	7315	+ int stream_num = 0;
	7316	+ bool is_can_be_online = false;
6785	7317
6786	7318	switch (cmd) {
6787	7319	case RKCIF_CMD_GET_CSI_MEMORY_MODE:
..	..	@@ -6796,8 +7328,8 @@
6796	7328	break;
6797	7329	case RKCIF_CMD_SET_CSI_MEMORY_MODE:
6798	7330	if (dev->terminal_sensor.sd) {
6799		- in_fmt = get_input_fmt(dev->terminal_sensor.sd,
6800		- &rect, 0, &csi_info);
	7331	+ in_fmt = rkcif_get_input_fmt(dev,
	7332	+ &rect, 0, &csi_info);
6801	7333	if (in_fmt == NULL) {
6802	7334	v4l2_err(&dev->v4l2_dev, "can't get sensor input format\n");
6803	7335	return -EINVAL;
..	..	@@ -6830,6 +7362,91 @@
6830	7362	case RKCIF_CMD_SET_RESET:
6831	7363	reset_src = (int )arg;
6832	7364	return rkcif_do_reset_work(dev, reset_src);
	7365	+ case RKCIF_CMD_SET_QUICK_STREAM:
	7366	+ stream_param = (struct rkcif_quick_stream_param *)arg;
	7367	+ if (!dev->sditf[0])
	7368	+ return -EINVAL;
	7369	+ if (dev->hdr.hdr_mode == HDR_X2)
	7370	+ stream_num = 2;
	7371	+ else if (dev->hdr.hdr_mode == HDR_X3)
	7372	+ stream_num = 3;
	7373	+ else
	7374	+ stream_num = 1;
	7375	+ if (stream_param->on) {
	7376	+ for (i = 0; i < stream_num; i++)
	7377	+ dev->stream[i].cur_skip_frame = dev->stream[i].skip_frame;
	7378	+ is_single_dev = rkcif_check_single_dev_stream_on(dev->hw_dev);
	7379	+ is_can_be_online = rkcif_check_can_be_online(dev);
	7380	+ if (is_single_dev && is_can_be_online) {
	7381	+ for (i = 0; i < stream_num - 1; i++) {
	7382	+ dev->stream[i].to_en_dma = RKCIF_DMAEN_BY_ISP;
	7383	+ rkcif_enable_dma_capture(&dev->stream[i], true);
	7384	+ }
	7385	+ dev->sditf[0]->mode.rdbk_mode = RKISP_VICAP_ONLINE;
	7386	+ sditf_change_to_online(dev->sditf[0]);
	7387	+ sd = get_rkisp_sd(dev->sditf[0]);
	7388	+ if (sd)
	7389	+ ret = v4l2_subdev_call(sd, core, ioctl,
	7390	+ RKISP_VICAP_CMD_MODE, &dev->sditf[0]->mode);
	7391	+ if (ret) {
	7392	+ v4l2_err(&dev->v4l2_dev, "set isp work mode online fail\n");
	7393	+ return -EINVAL;
	7394	+ }
	7395	+ } else {
	7396	+ sditf_disable_immediately(dev->sditf[0]);
	7397	+ dev->sditf[0]->mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO;
	7398	+ sd = get_rkisp_sd(dev->sditf[0]);
	7399	+ if (sd)
	7400	+ ret = v4l2_subdev_call(sd, core, ioctl,
	7401	+ RKISP_VICAP_CMD_MODE, &dev->sditf[0]->mode);
	7402	+ for (i = 0; i < stream_num; i++) {
	7403	+ if (dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO)
	7404	+ dev->stream[i].to_en_dma = RKCIF_DMAEN_BY_ISP;
	7405	+ else
	7406	+ dev->stream[i].to_en_dma = RKCIF_DMAEN_BY_VICAP;
	7407	+ rkcif_enable_dma_capture(&dev->stream[i], true);
	7408	+ }
	7409	+ }
	7410	+ rkcif_dphy_quick_stream(dev, stream_param->on);
	7411	+ v4l2_subdev_call(dev->terminal_sensor.sd, core, ioctl,
	7412	+ RKMODULE_SET_QUICK_STREAM, &stream_param->on);
	7413	+ } else {
	7414	+ if (dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_ONLINE) {
	7415	+ for (i = 0; i < stream_num - 1; i++) {
	7416	+ reinit_completion(&dev->stream[i].stop_complete);
	7417	+ dev->stream[i].is_wait_stop_complete = true;
	7418	+ dev->stream[i].to_stop_dma = RKCIF_DMAEN_BY_ISP;
	7419	+ wait_for_completion_timeout(&dev->stream[i].stop_complete,
	7420	+ msecs_to_jiffies(RKCIF_STOP_MAX_WAIT_TIME_MS));
	7421	+ }
	7422	+ stream->cifdev->sensor_state = stream_param->on;
	7423	+ stream->cifdev->sensor_state_change = true;
	7424	+ dev->stream[i].is_wait_stop_complete = true;
	7425	+ wait_for_completion_timeout(&dev->stream[i].stop_complete,
	7426	+ msecs_to_jiffies(RKCIF_STOP_MAX_WAIT_TIME_MS));
	7427	+ } else {
	7428	+ for (i = 0; i < stream_num; i++) {
	7429	+ dev->stream[i].is_wait_stop_complete = true;
	7430	+ reinit_completion(&dev->stream[i].stop_complete);
	7431	+ if (dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO)
	7432	+ dev->stream[i].to_stop_dma = RKCIF_DMAEN_BY_ISP;
	7433	+ else
	7434	+ dev->stream[i].to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	7435	+ wait_for_completion_timeout(&dev->stream[i].stop_complete,
	7436	+ msecs_to_jiffies(RKCIF_STOP_MAX_WAIT_TIME_MS));
	7437	+ }
	7438	+ rkcif_dphy_quick_stream(dev, stream_param->on);
	7439	+ v4l2_subdev_call(dev->terminal_sensor.sd, core, ioctl,
	7440	+ RKMODULE_SET_QUICK_STREAM, &stream_param->on);
	7441	+ }
	7442	+ stream_param->frame_num = dev->stream[0].frame_idx - 1;
	7443	+ if (!dev->is_rtt_suspend) {
	7444	+ dev->resume_mode = stream_param->resume_mode;
	7445	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	7446	+ "set resume mode %d\n", dev->resume_mode);
	7447	+ }
	7448	+ }
	7449	+ break;
6833	7450	default:
6834	7451	return -EINVAL;
6835	7452	}
..	..	@@ -6876,6 +7493,7 @@
6876	7493	v4l2_dbg(2, rkcif_debug, &stream->cifdev->v4l2_dev,
6877	7494	"stream[%d] vb done, index: %d, sequence %d\n", stream->id,
6878	7495	vb_done->vb2_buf.index, vb_done->sequence);
	7496	+ atomic_dec(&stream->buf_cnt);
6879	7497	}
6880	7498
6881	7499	static void rkcif_tasklet_handle(unsigned long data)
..	..	@@ -7632,7 +8250,7 @@
7632	8250	timer->csi2_err_triggered_cnt++;
7633	8251	if (timer->csi2_err_triggered_cnt == 1) {
7634	8252	is_first_err = true;
7635		- timer->csi2_first_err_timestamp = ktime_get_ns();
	8253	+ timer->csi2_first_err_timestamp = rkcif_time_get_ns(dev);
7636	8254	}
7637	8255
7638	8256	is_assign_triggered = true;
..	..	@@ -7644,7 +8262,7 @@
7644	8262
7645	8263	if (!is_first_err) {
7646	8264	if (timer->csi2_err_triggered_cnt >= 1) {
7647		- cur_time = ktime_get_ns();
	8265	+ cur_time = rkcif_time_get_ns(dev);
7648	8266	diff_time = cur_time - timer->csi2_first_err_timestamp;
7649	8267	diff_time = div_u64(diff_time, 1000000);
7650	8268	if (diff_time >= timer->err_time_interval) {
..	..	@@ -7987,7 +8605,7 @@
7987	8605	v4l2_err(&dev->v4l2_dev,
7988	8606	"s/m/l frame err, timestamp s:%lld m:%lld l:%lld\n",
7989	8607	s_ts, m_ts, l_ts);
7990		- goto RDBK_FRM_UNMATCH;
	8608	+ return;
7991	8609	}
7992	8610
7993	8611	if ((m_ts - l_ts) > time \|\| (s_ts - m_ts) > time) {
..	..	@@ -8008,7 +8626,7 @@
8008	8626	v4l2_err(&dev->v4l2_dev,
8009	8627	"timestamp no match, s:%lld m:%lld l:%lld, fps:%d\n",
8010	8628	s_ts, m_ts, l_ts, fps);
8011		- goto RDBK_FRM_UNMATCH;
	8629	+ return;
8012	8630	}
8013	8631	}
8014	8632	dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
..	..	@@ -8037,7 +8655,7 @@
8037	8655	v4l2_err(&dev->v4l2_dev, "lost medium frames\n");
8038	8656	if (!dev->rdbk_buf[RDBK_S])
8039	8657	v4l2_err(&dev->v4l2_dev, "lost short frames\n");
8040		- goto RDBK_FRM_UNMATCH;
	8658	+ return;
8041	8659	}
8042	8660	} else if (dev->hdr.hdr_mode == HDR_X2) {
8043	8661	if (dev->rdbk_buf[RDBK_L] && dev->rdbk_buf[RDBK_M]) {
..	..	@@ -8048,7 +8666,7 @@
8048	8666	v4l2_err(&dev->v4l2_dev,
8049	8667	"s/l frame err, timestamp s:%lld l:%lld\n",
8050	8668	s_ts, l_ts);
8051		- goto RDBK_FRM_UNMATCH;
	8669	+ return;
8052	8670	}
8053	8671
8054	8672	if ((s_ts - l_ts) > time) {
..	..	@@ -8068,7 +8686,7 @@
8068	8686	v4l2_err(&dev->v4l2_dev,
8069	8687	"timestamp no match, s:%lld l:%lld, fps:%d\n",
8070	8688	s_ts, l_ts, fps);
8071		- goto RDBK_FRM_UNMATCH;
	8689	+ return;
8072	8690	}
8073	8691	}
8074	8692	dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
..	..	@@ -8092,27 +8710,8 @@
8092	8710	v4l2_err(&dev->v4l2_dev, "lost long frames\n");
8093	8711	if (!dev->rdbk_buf[RDBK_M])
8094	8712	v4l2_err(&dev->v4l2_dev, "lost short frames\n");
8095		- goto RDBK_FRM_UNMATCH;
	8713	+ return;
8096	8714	}
8097		- }
8098		-
8099		- dev->rdbk_buf[RDBK_L] = NULL;
8100		- dev->rdbk_buf[RDBK_M] = NULL;
8101		- dev->rdbk_buf[RDBK_S] = NULL;
8102		- return;
8103		-
8104		-RDBK_FRM_UNMATCH:
8105		- if (dev->rdbk_buf[RDBK_L]) {
8106		- dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
8107		- rkcif_buf_queue(&dev->rdbk_buf[RDBK_L]->vb.vb2_buf);
8108		- }
8109		- if (dev->rdbk_buf[RDBK_M]) {
8110		- dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
8111		- rkcif_buf_queue(&dev->rdbk_buf[RDBK_M]->vb.vb2_buf);
8112		- }
8113		- if (dev->rdbk_buf[RDBK_S]) {
8114		- dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
8115		- rkcif_buf_queue(&dev->rdbk_buf[RDBK_S]->vb.vb2_buf);
8116	8715	}
8117	8716
8118	8717	dev->rdbk_buf[RDBK_L] = NULL;
..	..	@@ -8147,9 +8746,13 @@
8147	8746
8148	8747	if (active_buf) {
8149	8748	vb_done = &active_buf->vb;
8150		- vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
	8749	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	8750	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656)
	8751	+ vb_done->vb2_buf.timestamp = stream->readout.fe_timestamp;
	8752	+ else
	8753	+ vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
8151	8754	vb_done->sequence = stream->frame_idx - 1;
8152		- active_buf->fe_timestamp = ktime_get_ns();
	8755	+ active_buf->fe_timestamp = rkcif_time_get_ns(cif_dev);
8153	8756	if (stream->is_line_wake_up) {
8154	8757	spin_lock_irqsave(&stream->fps_lock, flags);
8155	8758	if (mode)
..	..	@@ -8161,6 +8764,19 @@
8161	8764	}
8162	8765	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED)
8163	8766	vb_done->sequence /= 2;
	8767	+ if (stream->cur_skip_frame) {
	8768	+ rkcif_buf_queue(&active_buf->vb.vb2_buf);
	8769	+ return;
	8770	+ }
	8771	+ } else if (cif_dev->rdbk_buf[stream->id]) {
	8772	+ vb_done = &cif_dev->rdbk_buf[stream->id]->vb;
	8773	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	8774	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656)
	8775	+ vb_done->vb2_buf.timestamp = stream->readout.fe_timestamp;
	8776	+ else
	8777	+ vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
	8778	+ vb_done->sequence = stream->frame_idx - 1;
	8779	+ cif_dev->rdbk_buf[stream->id]->fe_timestamp = rkcif_time_get_ns(cif_dev);
8164	8780	}
8165	8781
8166	8782	if (cif_dev->hdr.hdr_mode == NO_HDR \|\| cif_dev->hdr.hdr_mode == HDR_COMPR) {
..	..	@@ -8184,7 +8800,7 @@
8184	8800	if (cif_dev->is_start_hdr) {
8185	8801	spin_lock_irqsave(&cif_dev->hdr_lock, flags);
8186	8802	if (mipi_id == RKCIF_STREAM_MIPI_ID0) {
8187		- if (cif_dev->rdbk_buf[RDBK_L]) {
	8803	+ if (cif_dev->rdbk_buf[RDBK_L] && active_buf) {
8188	8804	v4l2_err(&cif_dev->v4l2_dev,
8189	8805	"multiple long data in %s frame,frm_idx:%d,state:0x%x\n",
8190	8806	cif_dev->hdr.hdr_mode == HDR_X2 ? "hdr_x2" : "hdr_x3",
..	..	@@ -8197,7 +8813,7 @@
8197	8813	if (active_buf)
8198	8814	cif_dev->rdbk_buf[RDBK_L] = active_buf;
8199	8815	} else if (mipi_id == RKCIF_STREAM_MIPI_ID1) {
8200		- if (cif_dev->rdbk_buf[RDBK_M]) {
	8816	+ if (cif_dev->rdbk_buf[RDBK_M] && active_buf) {
8201	8817	v4l2_err(&cif_dev->v4l2_dev,
8202	8818	"multiple %s frame,frm_idx:%d,state:0x%x\n",
8203	8819	cif_dev->hdr.hdr_mode == HDR_X2 ? "short data in hdr_x2" : "medium data in hdr_x3",
..	..	@@ -8212,7 +8828,7 @@
8212	8828	if (cif_dev->hdr.hdr_mode == HDR_X2)
8213	8829	rkcif_rdbk_frame_end(stream);
8214	8830	} else if (mipi_id == RKCIF_STREAM_MIPI_ID2) {
8215		- if (cif_dev->rdbk_buf[RDBK_S]) {
	8831	+ if (cif_dev->rdbk_buf[RDBK_S] && active_buf) {
8216	8832	v4l2_err(&cif_dev->v4l2_dev,
8217	8833	"multiple %s frame, frm_idx:%d,state:0x%x\n",
8218	8834	cif_dev->hdr.hdr_mode == HDR_X2 ? "err short data in hdr_x3" : "short data in hdr_x3",
..	..	@@ -8308,8 +8924,10 @@
8308	8924	spin_lock_irqsave(&priv->cif_dev->buffree_lock, flags);
8309	8925	for (i = 0; i < priv->buf_num; i++) {
8310	8926	rx_buf = &stream->rx_buf[i];
8311		- if (rx_buf && (!rx_buf->dummy.is_free) && rx_buf != buf)
	8927	+ if (rx_buf && (!rx_buf->dummy.is_free) && rx_buf != buf) {
8312	8928	list_add_tail(&rx_buf->list_free, &priv->buf_free_list);
	8929	+ stream->total_buf_num--;
	8930	+ }
8313	8931	}
8314	8932	spin_unlock_irqrestore(&priv->cif_dev->buffree_lock, flags);
8315	8933	schedule_work(&priv->buffree_work.work);
..	..	@@ -8377,13 +8995,15 @@
8377	8995	spin_unlock_irqrestore(&stream->vbq_lock, flags);
8378	8996	active_buf->dbufs.sequence = stream->frame_idx - 1;
8379	8997	active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
8380		- active_buf->fe_timestamp = ktime_get_ns();
	8998	+ active_buf->fe_timestamp = rkcif_time_get_ns(stream->cifdev);
8381	8999	stream->last_frame_idx = stream->frame_idx;
8382		- if (stream->cifdev->hdr.hdr_mode == NO_HDR)
8383		- rkcif_s_rx_buffer(stream->cifdev, &active_buf->dbufs);
8384		- else
	9000	+ if (stream->cifdev->hdr.hdr_mode == NO_HDR) {
	9001	+ rkcif_s_rx_buffer(stream, &active_buf->dbufs);
	9002	+ if (stream->cifdev->is_support_tools && stream->tools_vdev)
	9003	+ rkcif_rdbk_with_tools(stream, active_buf);
	9004	+ } else {
8385	9005	rkcif_rdbk_frame_end_toisp(stream, active_buf);
8386		- stream->buf_num_toisp--;
	9006	+ }
8387	9007	}
8388	9008	}
8389	9009	}
..	..	@@ -8395,7 +9015,7 @@
8395	9015	unsigned long flags;
8396	9016
8397	9017	spin_lock_irqsave(&stream->fps_lock, flags);
8398		- stream->readout.fe_timestamp = ktime_get_ns();
	9018	+ stream->readout.fe_timestamp = rkcif_time_get_ns(cif_dev);
8399	9019
8400	9020	if (cif_dev->inf_id == RKCIF_DVP) {
8401	9021	spin_unlock_irqrestore(&stream->fps_lock, flags);
..	..	@@ -8442,11 +9062,11 @@
8442	9062	if (stream->frame_phase & CIF_CSI_FRAME0_READY) {
8443	9063	if (stream->curr_buf)
8444	9064	active_buf = stream->curr_buf;
8445		- stream->fps_stats.frm0_timestamp = ktime_get_ns();
	9065	+ stream->fps_stats.frm0_timestamp = rkcif_time_get_ns(cif_dev);
8446	9066	} else if (stream->frame_phase & CIF_CSI_FRAME1_READY) {
8447	9067	if (stream->next_buf)
8448	9068	active_buf = stream->next_buf;
8449		- stream->fps_stats.frm1_timestamp = ktime_get_ns();
	9069	+ stream->fps_stats.frm1_timestamp = rkcif_time_get_ns(cif_dev);
8450	9070	}
8451	9071	spin_unlock_irqrestore(&stream->fps_lock, flags);
8452	9072	}
..	..	@@ -8455,8 +9075,8 @@
8455	9075
8456	9076	if (!stream->is_line_wake_up) {
8457	9077	ret = rkcif_assign_new_buffer_pingpong(stream,
8458		- RKCIF_YUV_ADDR_STATE_UPDATE,
8459		- mipi_id);
	9078	+ RKCIF_YUV_ADDR_STATE_UPDATE,
	9079	+ mipi_id);
8460	9080	if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
8461	9081	return;
8462	9082	} else {
..	..	@@ -8464,7 +9084,11 @@
8464	9084	if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
8465	9085	return;
8466	9086	}
8467		- if (!stream->is_line_wake_up && stream->dma_en & RKCIF_DMAEN_BY_VICAP)
	9087	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	9088	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656 &&
	9089	+ stream->id != 0)
	9090	+ stream->frame_idx++;
	9091	+ if (!stream->is_line_wake_up)
8468	9092	rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0);
8469	9093
8470	9094	if (cif_dev->chip_id == CHIP_RV1126_CIF \|\|
..	..	@@ -8486,9 +9110,9 @@
8486	9110
8487	9111	spin_lock(&stream->fps_lock);
8488	9112	if (stream->frame_phase & CIF_CSI_FRAME0_READY)
8489		- stream->fps_stats.frm0_timestamp = ktime_get_ns();
	9113	+ stream->fps_stats.frm0_timestamp = rkcif_time_get_ns(cif_dev);
8490	9114	else if (stream->frame_phase & CIF_CSI_FRAME1_READY)
8491		- stream->fps_stats.frm1_timestamp = ktime_get_ns();
	9115	+ stream->fps_stats.frm1_timestamp = rkcif_time_get_ns(cif_dev);
8492	9116	spin_unlock(&stream->fps_lock);
8493	9117
8494	9118	if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
..	..	@@ -8520,11 +9144,11 @@
8520	9144	if (stream->frame_phase & CIF_CSI_FRAME0_READY) {
8521	9145	if (stream->curr_buf_rockit)
8522	9146	active_buf = stream->curr_buf_rockit;
8523		- stream->fps_stats.frm0_timestamp = ktime_get_ns();
	9147	+ stream->fps_stats.frm0_timestamp = rkcif_time_get_ns(cif_dev);
8524	9148	} else if (stream->frame_phase & CIF_CSI_FRAME1_READY) {
8525	9149	if (stream->next_buf_rockit)
8526	9150	active_buf = stream->next_buf_rockit;
8527		- stream->fps_stats.frm1_timestamp = ktime_get_ns();
	9151	+ stream->fps_stats.frm1_timestamp = rkcif_time_get_ns(cif_dev);
8528	9152	}
8529	9153	spin_unlock_irqrestore(&stream->fps_lock, flags);
8530	9154	}
..	..	@@ -8581,6 +9205,15 @@
8581	9205	}
8582	9206	}
8583	9207
	9208	+static void rkcif_toisp_set_stream(struct rkcif_device *dev, int on)
	9209	+{
	9210	+ struct v4l2_subdev *sd = get_rkisp_sd(dev->sditf[0]);
	9211	+
	9212	+ if (sd)
	9213	+ v4l2_subdev_call(sd, core, ioctl,
	9214	+ RKISP_VICAP_CMD_SET_STREAM, &on);
	9215	+}
	9216	+
8584	9217	static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
8585	9218	enum rkmodule_reset_src reset_src)
8586	9219	{
..	..	@@ -8590,6 +9223,7 @@
8590	9223	struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
8591	9224	struct rkcif_resume_info *resume_info = &cif_dev->reset_work.resume_info;
8592	9225	struct rkcif_timer *timer = &cif_dev->reset_watchdog_timer;
	9226	+ struct sditf_priv *priv = cif_dev->sditf[0];
8593	9227	int i, j, ret = 0;
8594	9228	u32 on, sof_cnt;
8595	9229	int capture_mode = 0;
..	..	@@ -8658,10 +9292,12 @@
8658	9292	__func__, on ? "on" : "off", p->subdevs[i]->name);
8659	9293	}
8660	9294
8661		- for (i = 0; i < cif_dev->sditf_cnt; i++) {
8662		- if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
8663		- ret = v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
8664		- RKMODULE_SET_QUICK_STREAM, &on);
	9295	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	9296	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	9297	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	9298	+ ret = v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
	9299	+ RKMODULE_SET_QUICK_STREAM, &on);
	9300	+ }
8665	9301	}
8666	9302
8667	9303	rockchip_clear_system_status(SYS_STATUS_CIF0);
..	..	@@ -8683,6 +9319,9 @@
8683	9319	goto unlock_stream;
8684	9320	}
8685	9321	}
	9322	+
	9323	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	9324	+ rkcif_toisp_set_stream(cif_dev, 1);
8686	9325
8687	9326	for (i = 0; i < j; i++) {
8688	9327	stream = resume_stream[i];
..	..	@@ -8756,10 +9395,12 @@
8756	9395	p->subdevs[i]->name);
8757	9396	}
8758	9397
8759		- for (i = 0; i < cif_dev->sditf_cnt; i++) {
8760		- if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
8761		- v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
8762		- RKMODULE_SET_QUICK_STREAM, &on);
	9398	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	9399	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	9400	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	9401	+ v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
	9402	+ RKMODULE_SET_QUICK_STREAM, &on);
	9403	+ }
8763	9404	}
8764	9405
8765	9406	if (cif_dev->chip_id < CHIP_RK3588_CIF)
..	..	@@ -8820,7 +9461,7 @@
8820	9461	v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "diff_time:%lld,devi_t:%ld,devi_h:%d\n",
8821	9462	diff_time, timer->line_end_cycle * deviation, deviation);
8822	9463
8823		- cur_time = ktime_get_ns();
	9464	+ cur_time = rkcif_time_get_ns(dev);
8824	9465	time_distance = timestamp0 > timestamp1 ?
8825	9466	cur_time - timestamp0 : cur_time - timestamp1;
8826	9467	time_distance = div_u64(time_distance, 1000);
..	..	@@ -8929,6 +9570,7 @@
8929	9570	timer->csi2_err_cnt_even = 0;
8930	9571	timer->csi2_err_fs_fe_cnt = 0;
8931	9572	timer->notifer_called_cnt = 0;
	9573	+ dev->is_toisp_reset = false;
8932	9574	for (i = 0; i < dev->num_channels; i++) {
8933	9575	stream = &dev->stream[i];
8934	9576	if (stream->state == RKCIF_STATE_STREAMING)
..	..	@@ -8938,10 +9580,10 @@
8938	9580	if (timer->is_ctrl_by_user) {
8939	9581	rkcif_send_reset_event(dev, timer->reset_src);
8940	9582	} else {
	9583	+ dev->reset_work.reset_src = timer->reset_src;
8941	9584	if (!schedule_work(&dev->reset_work.work))
8942	9585	v4l2_info(&dev->v4l2_dev,
8943	9586	"schedule reset work failed\n");
8944		- dev->reset_work.reset_src = timer->reset_src;
8945	9587	}
8946	9588	}
8947	9589
..	..	@@ -8955,6 +9597,15 @@
8955	9597	unsigned long flags;
8956	9598	int ret, is_reset = 0;
8957	9599	struct rkmodule_vicap_reset_info rst_info;
	9600	+
	9601	+ if (dev->is_toisp_reset) {
	9602	+ is_reset = 1;
	9603	+ timer->reset_src = RKCIF_RESET_SRC_ERR_ISP;
	9604	+ }
	9605	+ if (is_reset) {
	9606	+ rkcif_init_reset_work(timer);
	9607	+ return is_reset;
	9608	+ }
8958	9609
8959	9610	if (timer->last_buf_wakeup_cnt[stream->id] < stream->buf_wake_up_cnt &&
8960	9611	check_cnt == 0) {
..	..	@@ -9329,6 +9980,7 @@
9329	9980	if (stream->buf_owner == RKCIF_DMAEN_BY_ISP)
9330	9981	stream->buf_owner = RKCIF_DMAEN_BY_ISP_TO_VICAP;
9331	9982
	9983	+ atomic_dec(&cif_dev->streamoff_cnt);
9332	9984	if (stream->dma_en) {
9333	9985	stream->dma_en \|= stream->to_en_dma;
9334	9986	stream->to_en_dma = 0;
..	..	@@ -9399,7 +10051,7 @@
9399	10051	return -EINVAL;
9400	10052
9401	10053	stream->dma_en &= ~stream->to_stop_dma;
9402		-
	10054	+ atomic_inc(&cif_dev->streamoff_cnt);
9403	10055	if (stream->dma_en != 0) {
9404	10056	if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
9405	10057	stream->buf_owner = RKCIF_DMAEN_BY_ISP;
..	..	@@ -9437,6 +10089,11 @@
9437	10089	rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
9438	10090	}
9439	10091	stream->to_stop_dma = 0;
	10092	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	10093	+ "stream[%d] replace_cnt %d, y_addr 0x%x, 0x%x\n",
	10094	+ stream->id, stream->buf_replace_cnt,
	10095	+ rkcif_read_register(cif_dev, get_reg_index_of_frm0_y_addr(stream->id)),
	10096	+ rkcif_read_register(cif_dev, get_reg_index_of_frm1_y_addr(stream->id)));
9440	10097	return 0;
9441	10098	}
9442	10099
..	..	@@ -9490,6 +10147,7 @@
9490	10147	int i = 0;
9491	10148	u32 val = 0;
9492	10149	u64 cur_time = 0;
	10150	+ int on = 0;
9493	10151
9494	10152	for (i = 0; i < TOISP_CH_MAX; i++) {
9495	10153	ch = rkcif_g_toisp_ch(intstat_glb, index);
..	..	@@ -9507,7 +10165,30 @@
9507	10165	stream->stopping = false;
9508	10166	wake_up(&stream->wq_stopped);
9509	10167	}
9510		-
	10168	+ if (stream->cifdev->sensor_state_change) {
	10169	+ rkcif_dphy_quick_stream(stream->cifdev, on);
	10170	+ stream->cifdev->sensor_work.on = stream->cifdev->sensor_state;
	10171	+ schedule_work(&stream->cifdev->sensor_work.work);
	10172	+ stream->cifdev->sensor_state_change = false;
	10173	+ if (stream->is_wait_stop_complete) {
	10174	+ stream->is_wait_stop_complete = false;
	10175	+ complete(&stream->stop_complete);
	10176	+ }
	10177	+ }
	10178	+ if (stream->is_single_cap && (!stream->cur_skip_frame) &&
	10179	+ (stream->cifdev->hdr.hdr_mode == NO_HDR \|\|
	10180	+ (stream->cifdev->hdr.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	10181	+ (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 2))) {
	10182	+ rkcif_dphy_quick_stream(stream->cifdev, on);
	10183	+ stream->cifdev->sensor_work.on = 0;
	10184	+ schedule_work(&stream->cifdev->sensor_work.work);
	10185	+ stream->is_single_cap = false;
	10186	+ }
	10187	+ if (stream->cur_skip_frame &&
	10188	+ (stream->cifdev->hdr.hdr_mode == NO_HDR \|\|
	10189	+ (stream->cifdev->hdr.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	10190	+ (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 2)))
	10191	+ stream->cur_skip_frame--;
9511	10192	if (stream->cifdev->chip_id >= CHIP_RV1106_CIF)
9512	10193	rkcif_modify_frame_skip_config(stream);
9513	10194	if (stream->cifdev->rdbk_debug &&
..	..	@@ -9544,9 +10225,14 @@
9544	10225	if (stream->id == 0)
9545	10226	rkcif_send_sof(stream->cifdev);
9546	10227	stream->frame_idx++;
9547		- cur_time = ktime_get_ns();
	10228	+ cur_time = rkcif_time_get_ns(stream->cifdev);
9548	10229	stream->readout.readout_time = cur_time - stream->readout.fs_timestamp;
9549	10230	stream->readout.fs_timestamp = cur_time;
	10231	+ stream->buf_wake_up_cnt++;
	10232	+ if (stream->frame_idx % 2)
	10233	+ stream->fps_stats.frm0_timestamp = rkcif_time_get_ns(stream->cifdev);
	10234	+ else
	10235	+ stream->fps_stats.frm1_timestamp = rkcif_time_get_ns(stream->cifdev);
9550	10236	if (stream->cifdev->rdbk_debug &&
9551	10237	stream->frame_idx < 15)
9552	10238	v4l2_info(&priv->cif_dev->v4l2_dev,
..	..	@@ -9616,15 +10302,16 @@
9616	10302
9617	10303	sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
9618	10304	sync_config->sync_code \|= BIT(cif_dev->csi_host_idx);
9619		- if (sync_config->sync_code != sync_config->sync_mask)
9620		- return -EINVAL;
9621		-
9622	10305	v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
9623		- "sync code 0x%x, mask 0x%x, update 0x%x, cache 0x%x\n",
	10306	+ "sync code 0x%x, mask 0x%x, update 0x%x, cache 0x%x, timestamp %llu\n",
9624	10307	sync_config->sync_code,
9625	10308	sync_config->sync_mask,
9626	10309	sync_config->update_code,
9627		- sync_config->update_cache);
	10310	+ sync_config->update_cache,
	10311	+ detect_stream->readout.fs_timestamp);
	10312	+
	10313	+ if (sync_config->sync_code != sync_config->sync_mask)
	10314	+ return -EINVAL;
9628	10315
9629	10316	for (i = 0; i < sync_config->dev_cnt; i++) {
9630	10317	if (sync_config->mode == RKCIF_MASTER_MASTER) {
..	..	@@ -9670,7 +10357,7 @@
9670	10357	if (cif_dev->chip_id < CHIP_RK3588_CIF)
9671	10358	detect_stream->fs_cnt_in_single_frame++;
9672	10359	spin_lock_irqsave(&detect_stream->fps_lock, flags);
9673		- detect_stream->readout.fs_timestamp = ktime_get_ns();
	10360	+ detect_stream->readout.fs_timestamp = rkcif_time_get_ns(cif_dev);
9674	10361	spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
9675	10362
9676	10363	if (cif_dev->sync_cfg.type != RKCIF_NOSYNC_MODE) {
..	..	@@ -9721,7 +10408,7 @@
9721	10408	"stream[%d] sof %d %lld\n",
9722	10409	detect_stream->id,
9723	10410	detect_stream->frame_idx - 1,
9724		- ktime_get_ns());
	10411	+ rkcif_time_get_ns(cif_dev));
9725	10412	}
9726	10413	}
9727	10414
..	..	@@ -9780,6 +10467,425 @@
9780	10467	return is_update;
9781	10468	}
9782	10469
	10470	+static bool rkcif_check_single_dev_stream_on(struct rkcif_hw *hw)
	10471	+{
	10472	+ struct rkcif_device *cif_dev = NULL;
	10473	+ struct rkcif_stream *stream = NULL;
	10474	+ int i = 0, j = 0;
	10475	+ int stream_cnt = 0;
	10476	+
	10477	+ if (hw->dev_num == 1)
	10478	+ return true;
	10479	+ for (i = 0; i < hw->dev_num; i++) {
	10480	+ cif_dev = hw->cif_dev[i];
	10481	+ for (j = 0; j < RKCIF_MAX_STREAM_MIPI; j++) {
	10482	+ stream = &cif_dev->stream[j];
	10483	+ if (stream->state == RKCIF_STATE_STREAMING \|\|
	10484	+ stream->state == RKCIF_STATE_RESET_IN_STREAMING) {
	10485	+ stream_cnt++;
	10486	+ break;
	10487	+ }
	10488	+ }
	10489	+ }
	10490	+ if (stream_cnt > 1)
	10491	+ return false;
	10492	+ return true;
	10493	+}
	10494	+
	10495	+static void rkcif_get_resmem_head(struct rkcif_device *cif_dev)
	10496	+{
	10497	+ void *resmem_va = phys_to_virt(cif_dev->resmem_pa);
	10498	+ struct rkisp_thunderboot_resmem_head *head = NULL;
	10499	+ int size = 0;
	10500	+ int offset = 0;
	10501	+ int ret = 0;
	10502	+ int cam_idx = 0;
	10503	+ char cam_idx_str[3] = {0};
	10504	+
	10505	+ if (!cif_dev->is_rtt_suspend)
	10506	+ return;
	10507	+ strscpy(cam_idx_str, cif_dev->terminal_sensor.sd->name + 1, 2);
	10508	+ cam_idx_str[2] = '\0';
	10509	+ ret = kstrtoint(cam_idx_str, 0, &cam_idx);
	10510	+ if (ret) {
	10511	+ v4l2_err(&cif_dev->v4l2_dev,
	10512	+ "get camera index fail\n");
	10513	+ return;
	10514	+ }
	10515	+
	10516	+ if (cif_dev->chip_id == CHIP_RV1106_CIF) {
	10517	+ size = sizeof(struct rkisp32_thunderboot_resmem_head);
	10518	+ offset = size * cam_idx;
	10519	+ }
	10520	+ /* currently, thunderboot with mcu only run one camera */
	10521	+ offset = 0;
	10522	+
	10523	+ if (size && size < cif_dev->resmem_size) {
	10524	+ dma_sync_single_for_cpu(cif_dev->dev, cif_dev->resmem_addr + offset,
	10525	+ size, DMA_FROM_DEVICE);
	10526	+ if (cif_dev->chip_id == CHIP_RV1106_CIF) {
	10527	+ struct rkisp32_thunderboot_resmem_head *tmp = resmem_va + offset;
	10528	+
	10529	+ head = &tmp->head;
	10530	+ cif_dev->resume_mode = head->rtt_mode;
	10531	+ cif_dev->nr_buf_size = head->nr_buf_size;
	10532	+ cif_dev->share_mem_size = head->share_mem_size;
	10533	+ cif_dev->thunderboot_sensor_num = head->camera_num;
	10534	+ }
	10535	+ }
	10536	+ v4l2_err(&cif_dev->v4l2_dev,
	10537	+ "get camera index %02x, resume_mode 0x%x, nr_buf_size %d\n",
	10538	+ cam_idx, cif_dev->resume_mode, cif_dev->nr_buf_size);
	10539	+}
	10540	+
	10541	+static int rkcif_subdevs_set_power(struct rkcif_device *cif_dev, int on)
	10542	+{
	10543	+ struct sditf_priv *priv = cif_dev->sditf[0];
	10544	+ int ret = 0;
	10545	+ int i = 0;
	10546	+
	10547	+ if (cif_dev->terminal_sensor.sd)
	10548	+ ret = v4l2_subdev_call(cif_dev->terminal_sensor.sd,
	10549	+ core, s_power, on);
	10550	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	10551	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	10552	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	10553	+ v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core,
	10554	+ s_power, on);
	10555	+ }
	10556	+ }
	10557	+ return ret;
	10558	+}
	10559	+
	10560	+static void rkcif_sensor_quick_streaming_cb(void *data)
	10561	+{
	10562	+ struct v4l2_subdev subdevs = (struct v4l2_subdev )data;
	10563	+ int on = 1;
	10564	+
	10565	+ v4l2_subdev_call(subdevs, core, ioctl,
	10566	+ RKMODULE_SET_QUICK_STREAM, &on);
	10567	+}
	10568	+
	10569	+static int rkcif_subdevs_set_stream(struct rkcif_device *cif_dev, int on)
	10570	+{
	10571	+ struct rkcif_pipeline *p = &cif_dev->pipe;
	10572	+ struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
	10573	+ struct sditf_priv *priv = cif_dev->sditf[0];
	10574	+ int i = 0;
	10575	+ int ret = 0;
	10576	+
	10577	+ for (i = 0; i < p->num_subdevs; i++) {
	10578	+ if (p->subdevs[i] == terminal_sensor->sd && on)
	10579	+ rkcif_set_sof(cif_dev, cif_dev->stream[0].frame_idx);
	10580	+ if (p->subdevs[i] == terminal_sensor->sd &&
	10581	+ cif_dev->chip_id == CHIP_RV1106_CIF) {
	10582	+ if (!rk_tb_mcu_is_done() && on) {
	10583	+ cif_dev->tb_client.data = p->subdevs[i];
	10584	+ cif_dev->tb_client.cb = rkcif_sensor_quick_streaming_cb;
	10585	+ rk_tb_client_register_cb(&cif_dev->tb_client);
	10586	+ } else {
	10587	+ ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
	10588	+ RKMODULE_SET_QUICK_STREAM, &on);
	10589	+ if (ret)
	10590	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10591	+ "%s:quick stream %s subdev:%s failed\n",
	10592	+ __func__, on ? "on" : "off",
	10593	+ p->subdevs[i]->name);
	10594	+ }
	10595	+ } else {
	10596	+ ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
	10597	+ if (ret)
	10598	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10599	+ "%s:stream %s subdev:%s failed\n",
	10600	+ __func__, on ? "on" : "off", p->subdevs[i]->name);
	10601	+ }
	10602	+ }
	10603	+
	10604	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	10605	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	10606	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd) {
	10607	+ ret = v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, video, s_stream, on);
	10608	+ if (ret)
	10609	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10610	+ "%s:stream %s subdev:%s failed\n",
	10611	+ __func__, on ? "on" : "off",
	10612	+ cif_dev->sditf[i]->sensor_sd->name);
	10613	+ }
	10614	+ }
	10615	+ }
	10616	+ return ret;
	10617	+}
	10618	+
	10619	+int rkcif_stream_suspend(struct rkcif_device *cif_dev, int mode)
	10620	+{
	10621	+ struct rkcif_stream *stream = NULL;
	10622	+ struct rkcif_resume_info *resume_info = &cif_dev->reset_work.resume_info;
	10623	+ struct sditf_priv *priv = cif_dev->sditf[0];
	10624	+ int ret = 0;
	10625	+ int i = 0;
	10626	+ int sof_cnt = 0;
	10627	+ int on = 0;
	10628	+ int suspend_cnt = 0;
	10629	+
	10630	+ mutex_lock(&cif_dev->stream_lock);
	10631	+
	10632	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE && mode == RKCIF_RESUME_CIF)
	10633	+ goto out_suspend;
	10634	+
	10635	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	10636	+ stream = &cif_dev->stream[i];
	10637	+
	10638	+ if (stream->state == RKCIF_STATE_STREAMING) {
	10639	+ suspend_cnt++;
	10640	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10641	+ "stream[%d] stopping\n", stream->id);
	10642	+ if (stream->dma_en) {
	10643	+ stream->stopping = true;
	10644	+ ret = wait_event_timeout(stream->wq_stopped,
	10645	+ stream->state != RKCIF_STATE_STREAMING,
	10646	+ msecs_to_jiffies(500));
	10647	+ if (!ret) {
	10648	+ rkcif_stream_stop(stream);
	10649	+ stream->stopping = false;
	10650	+ }
	10651	+ } else {
	10652	+ rkcif_stream_stop(stream);
	10653	+ }
	10654	+
	10655	+ if (stream->id == RKCIF_STREAM_MIPI_ID0) {
	10656	+ sof_cnt = rkcif_get_sof(cif_dev);
	10657	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10658	+ "%s: stream[%d] sync frmid & csi_sof, frm_id:%d, csi_sof:%d\n",
	10659	+ __func__,
	10660	+ stream->id,
	10661	+ stream->frame_idx,
	10662	+ sof_cnt);
	10663	+
	10664	+ resume_info->frm_sync_seq = stream->frame_idx;
	10665	+ }
	10666	+
	10667	+ stream->state = RKCIF_STATE_RESET_IN_STREAMING;
	10668	+ stream->is_fs_fe_not_paired = false;
	10669	+ stream->fs_cnt_in_single_frame = 0;
	10670	+
	10671	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10672	+ "%s stop stream[%d] in streaming, frm_id:%d, csi_sof:%d\n",
	10673	+ __func__, stream->id, stream->frame_idx, rkcif_get_sof(cif_dev));
	10674	+
	10675	+ }
	10676	+ }
	10677	+
	10678	+ if (suspend_cnt == 0)
	10679	+ goto out_suspend;
	10680	+
	10681	+ if (!cif_dev->resume_mode)
	10682	+ rkcif_subdevs_set_power(cif_dev, on);
	10683	+
	10684	+ rkcif_subdevs_set_stream(cif_dev, on);
	10685	+
	10686	+out_suspend:
	10687	+ mutex_unlock(&cif_dev->stream_lock);
	10688	+ return 0;
	10689	+}
	10690	+
	10691	+int rkcif_stream_resume(struct rkcif_device *cif_dev, int mode)
	10692	+{
	10693	+ struct rkcif_stream *stream = NULL;
	10694	+ struct sditf_priv *priv = cif_dev->sditf[0];
	10695	+ struct v4l2_subdev *sd = NULL;
	10696	+ int ret = 0;
	10697	+ int i = 0;
	10698	+ u32 capture_mode = 0;
	10699	+ int on = 1;
	10700	+ int resume_cnt = 0;
	10701	+ unsigned long flags;
	10702	+ bool is_single_dev = false;
	10703	+ bool is_can_be_online = false;
	10704	+ struct rkisp_vicap_mode vicap_mode;
	10705	+
	10706	+ mutex_lock(&cif_dev->stream_lock);
	10707	+
	10708	+ rkcif_get_resmem_head(cif_dev);
	10709	+ is_single_dev = rkcif_check_single_dev_stream_on(cif_dev->hw_dev);
	10710	+ is_can_be_online = rkcif_check_can_be_online(cif_dev);
	10711	+ if (cif_dev->resume_mode == RKISP_RTT_MODE_ONE_FRAME) {
	10712	+ if (cif_dev->is_rtt_suspend) {
	10713	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	10714	+ if (priv)
	10715	+ priv->mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO;
	10716	+ } else {
	10717	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE) {
	10718	+ if (cif_dev->chip_id == CHIP_RV1106_CIF) {
	10719	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	10720	+ priv->mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO;
	10721	+ } else {
	10722	+ capture_mode = RKCIF_STREAM_MODE_TOISP;
	10723	+ }
	10724	+ } else if (priv &&
	10725	+ (priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO \|\|
	10726	+ priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME)) {
	10727	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	10728	+ } else {
	10729	+ capture_mode = RKCIF_STREAM_MODE_CAPTURE;
	10730	+ }
	10731	+ }
	10732	+ } else if (cif_dev->resume_mode == RKISP_RTT_MODE_MULTI_FRAME) {
	10733	+ if (is_single_dev && is_can_be_online) {
	10734	+ capture_mode = RKCIF_STREAM_MODE_TOISP;
	10735	+ if (priv)
	10736	+ priv->mode.rdbk_mode = RKISP_VICAP_ONLINE;
	10737	+ } else {
	10738	+ if (cif_dev->is_thunderboot) {
	10739	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	10740	+ if (priv)
	10741	+ priv->mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO;
	10742	+ } else {
	10743	+ capture_mode = RKCIF_STREAM_MODE_CAPTURE;
	10744	+ if (priv)
	10745	+ priv->mode.rdbk_mode = RKISP_VICAP_RDBK_AIQ;
	10746	+ }
	10747	+ }
	10748	+ } else {
	10749	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	10750	+ capture_mode = RKCIF_STREAM_MODE_TOISP;
	10751	+ else if (priv &&
	10752	+ (priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO \|\|
	10753	+ priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME))
	10754	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	10755	+ else
	10756	+ capture_mode = RKCIF_STREAM_MODE_CAPTURE;
	10757	+ }
	10758	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE && mode == RKCIF_RESUME_CIF)
	10759	+ goto out_resume;
	10760	+
	10761	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	10762	+ stream = &cif_dev->stream[i];
	10763	+ if (stream->state != RKCIF_STATE_RESET_IN_STREAMING)
	10764	+ continue;
	10765	+
	10766	+ stream->fs_cnt_in_single_frame = 0;
	10767	+ if (cif_dev->resume_mode == RKISP_RTT_MODE_ONE_FRAME)
	10768	+ stream->is_single_cap = true;
	10769	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	10770	+ if (!priv \|\| priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AIQ) {
	10771	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	10772	+ if (stream->curr_buf == stream->next_buf) {
	10773	+ if (stream->curr_buf)
	10774	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	10775	+ } else {
	10776	+ if (stream->curr_buf)
	10777	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	10778	+ if (stream->next_buf)
	10779	+ list_add_tail(&stream->next_buf->queue, &stream->buf_head);
	10780	+ }
	10781	+ stream->curr_buf = NULL;
	10782	+ stream->next_buf = NULL;
	10783	+ }
	10784	+ } else {
	10785	+ if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE) {
	10786	+ if (stream->curr_buf_toisp == stream->next_buf_toisp) {
	10787	+ if (stream->curr_buf_toisp)
	10788	+ list_add_tail(&stream->curr_buf_toisp->list, &stream->rx_buf_head);
	10789	+ } else {
	10790	+ if (stream->curr_buf_toisp)
	10791	+ list_add_tail(&stream->curr_buf_toisp->list, &stream->rx_buf_head);
	10792	+ if (stream->next_buf_toisp)
	10793	+ list_add_tail(&stream->next_buf_toisp->list, &stream->rx_buf_head);
	10794	+ }
	10795	+ stream->curr_buf_toisp = NULL;
	10796	+ stream->next_buf_toisp = NULL;
	10797	+ } else {
	10798	+ if (stream->curr_buf_toisp == stream->next_buf_toisp) {
	10799	+ if (stream->curr_buf_toisp)
	10800	+ list_add_tail(&stream->curr_buf_toisp->list, &stream->rx_buf_head);
	10801	+ } else {
	10802	+ if (stream->curr_buf_toisp)
	10803	+ list_add_tail(&stream->curr_buf_toisp->list, &stream->rx_buf_head);
	10804	+ if (stream->next_buf_toisp)
	10805	+ list_add_tail(&stream->next_buf_toisp->list, &stream->rx_buf_head);
	10806	+ }
	10807	+ stream->curr_buf_toisp = NULL;
	10808	+ stream->next_buf_toisp = NULL;
	10809	+ }
	10810	+ }
	10811	+
	10812	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	10813	+
	10814	+ if (priv) {
	10815	+ if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE) {
	10816	+ sditf_change_to_online(priv);
	10817	+ if (cif_dev->resume_mode == RKISP_RTT_MODE_MULTI_FRAME &&
	10818	+ stream->rx_buf_num &&
	10819	+ (priv->hdr_cfg.hdr_mode == NO_HDR \|\|
	10820	+ (priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	10821	+ (priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id == 2)))
	10822	+ rkcif_free_rx_buf(stream, priv->buf_num);
	10823	+ else if (!stream->rx_buf_num &&
	10824	+ ((priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 0) \|\|
	10825	+ (priv->hdr_cfg.hdr_mode == HDR_X3 && (stream->id == 0 \|\| stream->id == 1))))
	10826	+ rkcif_init_rx_buf(stream, 1);
	10827	+ } else {
	10828	+ if (stream->is_single_cap && stream->id == 0) {
	10829	+ vicap_mode = priv->mode;
	10830	+ vicap_mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO_ONE_FRAME;
	10831	+ sd = get_rkisp_sd(priv);
	10832	+ if (sd) {
	10833	+ ret = v4l2_subdev_call(sd, core, ioctl,
	10834	+ RKISP_VICAP_CMD_MODE, &vicap_mode);
	10835	+ if (ret)
	10836	+ v4l2_err(&cif_dev->v4l2_dev,
	10837	+ "set isp work mode rdbk aotu oneframe fail\n");
	10838	+
	10839	+ }
	10840	+ }
	10841	+ sditf_disable_immediately(priv);
	10842	+ if (!stream->rx_buf_num &&
	10843	+ capture_mode == RKCIF_STREAM_MODE_TOISP_RDBK) {
	10844	+ if (cif_dev->resume_mode == RKISP_RTT_MODE_ONE_FRAME)
	10845	+ rkcif_init_rx_buf(stream, 1);
	10846	+ else
	10847	+ rkcif_init_rx_buf(stream, priv->buf_num);
	10848	+ }
	10849	+ }
	10850	+ }
	10851	+
	10852	+ stream->lack_buf_cnt = 0;
	10853	+ if (cif_dev->active_sensor &&
	10854	+ (cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	10855	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	10856	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_CCP2))
	10857	+ ret = rkcif_csi_stream_start(stream, capture_mode);
	10858	+ else
	10859	+ ret = rkcif_stream_start(stream, capture_mode);
	10860	+ if (ret)
	10861	+ v4l2_err(&cif_dev->v4l2_dev, "%s:resume stream[%d] failed\n",
	10862	+ __func__, stream->id);
	10863	+
	10864	+ resume_cnt++;
	10865	+ stream->cur_skip_frame = stream->skip_frame;
	10866	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	10867	+ "resume stream[%d], frm_idx:%d, csi_sof:%d\n",
	10868	+ stream->id, stream->frame_idx,
	10869	+ rkcif_get_sof(cif_dev));
	10870	+ }
	10871	+
	10872	+ if (resume_cnt == 0)
	10873	+ goto out_resume;
	10874	+
	10875	+ if (!cif_dev->resume_mode)
	10876	+ rkcif_subdevs_set_power(cif_dev, on);
	10877	+
	10878	+ atomic_set(&cif_dev->streamoff_cnt, 0);
	10879	+ rkcif_subdevs_set_stream(cif_dev, on);
	10880	+
	10881	+ if (cif_dev->chip_id < CHIP_RK3588_CIF)
	10882	+ rkcif_start_luma(&cif_dev->luma_vdev,
	10883	+ cif_dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
	10884	+out_resume:
	10885	+ mutex_unlock(&cif_dev->stream_lock);
	10886	+ return 0;
	10887	+}
	10888	+
9783	10889	void rkcif_err_print_work(struct work_struct *work)
9784	10890	{
9785	10891	struct rkcif_err_state_work *err_state_work = container_of(work,
..	..	@@ -9795,7 +10901,7 @@
9795	10901	u64 cur_time = 0;
9796	10902	bool is_print = false;
9797	10903
9798		- cur_time = ktime_get_ns();
	10904	+ cur_time = rkcif_time_get_ns(dev);
9799	10905	if (err_state_work->last_timestamp == 0) {
9800	10906	is_print = true;
9801	10907	} else {
..	..	@@ -9839,10 +10945,18 @@
9839	10945	v4l2_err(&dev->v4l2_dev,
9840	10946	"stream[3], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
9841	10947	dev->stream[3].frame_idx, dev->irq_stats.trig_simult_cnt[3]);
9842		- if (err_state & RKCIF_ERR_SIZE)
9843		- v4l2_err(&dev->v4l2_dev,
9844		- "ERROR: csi size err, intstat:0x%x, lastline:0x%x, cnt %llu\n",
9845		- intstat, lastline, dev->irq_stats.csi_size_err_cnt);
	10948	+ if (err_state & RKCIF_ERR_SIZE) {
	10949	+ if (dev->chip_id >= CHIP_RK3588_CIF)
	10950	+ v4l2_err(&dev->v4l2_dev,
	10951	+ "ERROR: csi size err, intstat:0x%x, size:0x%x,0x%x,0x%x,0x%x, cnt %llu\n",
	10952	+ intstat, err_state_work->size_id0, err_state_work->size_id1,
	10953	+ err_state_work->size_id2, err_state_work->size_id3,
	10954	+ dev->irq_stats.csi_size_err_cnt);
	10955	+ else
	10956	+ v4l2_err(&dev->v4l2_dev,
	10957	+ "ERROR: csi size err, intstat:0x%x, lastline:0x%x, cnt %llu\n",
	10958	+ intstat, lastline, dev->irq_stats.csi_size_err_cnt);
	10959	+ }
9846	10960	if (err_state & RKCIF_ERR_OVERFLOW)
9847	10961	v4l2_err(&dev->v4l2_dev,
9848	10962	"ERROR: csi fifo overflow, intstat:0x%x, lastline:0x%x, cnt %llu\n",
..	..	@@ -9876,6 +10990,7 @@
9876	10990	unsigned long flags;
9877	10991	bool is_update = false;
9878	10992	int ret = 0;
	10993	+ int on = 0;
9879	10994
9880	10995	if (!cif_dev->active_sensor)
9881	10996	return;
..	..	@@ -9896,13 +11011,22 @@
9896	11011	if (intstat) {
9897	11012	rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
9898	11013	v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
9899		- "intstat 0x%x\n",
9900		- intstat);
	11014	+ "intstat 0x%x\n", intstat);
9901	11015	} else {
9902	11016	return;
9903	11017	}
9904	11018
9905	11019	if (intstat & CSI_SIZE_ERR) {
	11020	+ if (cif_dev->chip_id >= CHIP_RK3588_CIF) {
	11021	+ cif_dev->err_state_work.size_id0 = rkcif_read_register(cif_dev,
	11022	+ CIF_REG_MIPI_FRAME_SIZE_ID0);
	11023	+ cif_dev->err_state_work.size_id1 = rkcif_read_register(cif_dev,
	11024	+ CIF_REG_MIPI_FRAME_SIZE_ID1);
	11025	+ cif_dev->err_state_work.size_id2 = rkcif_read_register(cif_dev,
	11026	+ CIF_REG_MIPI_FRAME_SIZE_ID2);
	11027	+ cif_dev->err_state_work.size_id3 = rkcif_read_register(cif_dev,
	11028	+ CIF_REG_MIPI_FRAME_SIZE_ID3);
	11029	+ }
9906	11030	cif_dev->irq_stats.csi_size_err_cnt++;
9907	11031	cif_dev->err_state \|= RKCIF_ERR_SIZE;
9908	11032	rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
..	..	@@ -9915,9 +11039,15 @@
9915	11039	return;
9916	11040	}
9917	11041
9918		- if (intstat & CSI_BANDWIDTH_LACK_V1) {
	11042	+ if (intstat & CSI_BANDWIDTH_LACK_V1 &&
	11043	+ cif_dev->intr_mask & CSI_BANDWIDTH_LACK_V1) {
9919	11044	cif_dev->irq_stats.csi_bwidth_lack_cnt++;
9920	11045	cif_dev->err_state \|= RKCIF_ERR_BANDWIDTH_LACK;
	11046	+ if (cif_dev->irq_stats.csi_bwidth_lack_cnt > 10) {
	11047	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN, ~(CSI_BANDWIDTH_LACK_V1));
	11048	+ cif_dev->intr_mask &= ~(CSI_BANDWIDTH_LACK_V1);
	11049	+ schedule_delayed_work(&cif_dev->work_deal_err, msecs_to_jiffies(1000));
	11050	+ }
9921	11051	}
9922	11052
9923	11053	if (intstat & CSI_ALL_ERROR_INTEN_V1) {
..	..	@@ -9972,7 +11102,19 @@
9972	11102	stream->id,
9973	11103	stream->frame_idx - 1,
9974	11104	stream->frame_phase,
9975		- ktime_get_ns());
	11105	+ rkcif_time_get_ns(cif_dev));
	11106	+ if (stream->is_finish_stop_dma && stream->is_wait_dma_stop) {
	11107	+ stream->is_wait_dma_stop = false;
	11108	+ wake_up(&stream->wq_stopped);
	11109	+ stream->is_finish_stop_dma = false;
	11110	+ continue;
	11111	+ }
	11112	+
	11113	+ if (stream->is_finish_stop_dma && stream->is_wait_stop_complete) {
	11114	+ stream->is_finish_stop_dma = false;
	11115	+ stream->is_wait_stop_complete = false;
	11116	+ complete(&stream->stop_complete);
	11117	+ }
9976	11118
9977	11119	if (stream->crop_dyn_en)
9978	11120	rkcif_dynamic_crop(stream);
..	..	@@ -9982,13 +11124,42 @@
9982	11124	is_update = true;
9983	11125	else
9984	11126	is_update = rkcif_check_buffer_prepare(stream);
	11127	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	11128	+ "dma capture by vicap, is_updata %d, group mode %d, dma_en %d\n",
	11129	+ is_update, cif_dev->sync_cfg.type, stream->dma_en);
9985	11130	if (is_update)
9986	11131	rkcif_update_stream(cif_dev, stream, mipi_id);
9987	11132	} else if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	11133	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	11134	+ "dma capture by isp, dma_en 0x%x\n",
	11135	+ stream->dma_en);
9988	11136	rkcif_update_stream_toisp(cif_dev, stream, mipi_id);
9989	11137	} else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT) {
	11138	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	11139	+ "dma capture by rockit, dma_en 0x%x\n",
	11140	+ stream->dma_en);
9990	11141	rkcif_update_stream_rockit(cif_dev, stream, mipi_id);
9991	11142	}
	11143	+ if (stream->is_single_cap && !stream->cur_skip_frame) {
	11144	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
	11145	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	11146	+ else if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
	11147	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	11148	+ else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT)
	11149	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ROCKIT;
	11150	+ rkcif_stop_dma_capture(stream);
	11151	+ stream->is_single_cap = false;
	11152	+ if ((cif_dev->hdr.hdr_mode == NO_HDR && atomic_read(&cif_dev->streamoff_cnt) == 1) \|\|
	11153	+ (cif_dev->hdr.hdr_mode == HDR_X2 && atomic_read(&cif_dev->streamoff_cnt) == 2) \|\|
	11154	+ (cif_dev->hdr.hdr_mode == HDR_X3 && atomic_read(&cif_dev->streamoff_cnt) == 3)) {
	11155	+ rkcif_dphy_quick_stream(stream->cifdev, on);
	11156	+ cif_dev->sensor_work.on = 0;
	11157	+ schedule_work(&cif_dev->sensor_work.work);
	11158	+ }
	11159	+ }
	11160	+
	11161	+ if (stream->cur_skip_frame)
	11162	+ stream->cur_skip_frame--;
9992	11163
9993	11164	if (cif_dev->chip_id >= CHIP_RV1106_CIF)
9994	11165	rkcif_modify_frame_skip_config(stream);
..	..	@@ -10003,13 +11174,13 @@
10003	11174	}
10004	11175
10005	11176	spin_lock_irqsave(&stream->vbq_lock, flags);
10006		- if (stream->is_finish_stop_dma) {
10007		- wake_up(&stream->wq_stopped);
10008		- stream->is_finish_stop_dma = false;
10009		- }
10010		- if (!(stream->dma_en & RKCIF_DMAEN_BY_ISP) && stream->lack_buf_cnt == 2) {
	11177	+ if (!(stream->cur_stream_mode & RKCIF_STREAM_MODE_TOISP) &&
	11178	+ stream->lack_buf_cnt == 2) {
10011	11179	stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
10012	11180	rkcif_stop_dma_capture(stream);
	11181	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	11182	+ "stream[%d] to stop dma, lack_buf_cnt %d\n",
	11183	+ stream->id, stream->lack_buf_cnt);
10013	11184	}
10014	11185	spin_unlock_irqrestore(&stream->vbq_lock, flags);
10015	11186	if (stream->to_en_scale) {
..	..	@@ -10036,10 +11207,11 @@
10036	11207	if (intstat & CSI_START_INTSTAT(i)) {
10037	11208	stream = &cif_dev->stream[i];
10038	11209	if (i == 0) {
10039		- rkcif_deal_sof(cif_dev);
	11210	+ if (!stream->cur_skip_frame)
	11211	+ rkcif_deal_sof(cif_dev);
10040	11212	} else {
10041	11213	spin_lock_irqsave(&stream->fps_lock, flags);
10042		- stream->readout.fs_timestamp = ktime_get_ns();
	11214	+ stream->readout.fs_timestamp = rkcif_time_get_ns(cif_dev);
10043	11215	stream->frame_idx++;
10044	11216	spin_unlock_irqrestore(&stream->fps_lock, flags);
10045	11217	}
..	..	@@ -10070,7 +11242,8 @@
10070	11242	v4l2_info(&cif_dev->v4l2_dev,
10071	11243	"line int %lld\n",
10072	11244	stream->line_int_cnt);
10073		- if (cif_dev->sditf[0] && cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO)
	11245	+ if (cif_dev->sditf[0] && (cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO \|\|
	11246	+ cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME))
10074	11247	rkcif_line_wake_up_rdbk(stream, stream->id);
10075	11248	else
10076	11249	rkcif_line_wake_up(stream, stream->id);
..	..	@@ -10179,7 +11352,8 @@
10179	11352
10180	11353	if (intstat & DVP_FRAME0_START_ID0 \|\| intstat & DVP_FRAME1_START_ID0) {
10181	11354	stream->is_in_vblank = false;
10182		- rkcif_deal_sof(cif_dev);
	11355	+ if (!stream->cur_skip_frame)
	11356	+ rkcif_deal_sof(cif_dev);
10183	11357	}
10184	11358
10185	11359	if (stream->crop_dyn_en)
..	..	@@ -10291,10 +11465,11 @@
10291	11465	if (intstat & CSI_START_INTSTAT(i)) {
10292	11466	stream = &cif_dev->stream[i];
10293	11467	if (i == 0) {
10294		- rkcif_deal_sof(cif_dev);
	11468	+ if (!stream->cur_skip_frame)
	11469	+ rkcif_deal_sof(cif_dev);
10295	11470	} else {
10296	11471	spin_lock_irqsave(&stream->fps_lock, flags);
10297		- stream->readout.fs_timestamp = ktime_get_ns();
	11472	+ stream->readout.fs_timestamp = rkcif_time_get_ns(cif_dev);
10298	11473	stream->frame_idx++;
10299	11474	spin_unlock_irqrestore(&stream->fps_lock, flags);
10300	11475	}
..	..	@@ -10421,9 +11596,9 @@
10421	11596
10422	11597	spin_lock_irqsave(&stream->fps_lock, flags);
10423	11598	if (stream->frame_phase & CIF_CSI_FRAME0_READY)
10424		- stream->fps_stats.frm0_timestamp = ktime_get_ns();
	11599	+ stream->fps_stats.frm0_timestamp = rkcif_time_get_ns(cif_dev);
10425	11600	else if (stream->frame_phase & CIF_CSI_FRAME1_READY)
10426		- stream->fps_stats.frm1_timestamp = ktime_get_ns();
	11601	+ stream->fps_stats.frm1_timestamp = rkcif_time_get_ns(cif_dev);
10427	11602	spin_unlock_irqrestore(&stream->fps_lock, flags);
10428	11603
10429	11604	ret = rkcif_assign_new_buffer_oneframe(stream,
..	..	@@ -10494,7 +11669,8 @@
10494	11669	(cif_dev->dvp_sof_in_oneframe == 0)) {
10495	11670	if ((intstat & (PRE_INF_FRAME_END \| PST_INF_FRAME_END)) == 0x0) {
10496	11671	if ((intstat & INTSTAT_ERR) == 0x0) {
10497		- rkcif_deal_sof(cif_dev);
	11672	+ if (!stream->cur_skip_frame)
	11673	+ rkcif_deal_sof(cif_dev);
10498	11674	int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
10499	11675	int_en &= ~LINE_INT_EN;
10500	11676	rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);