| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. |
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| 3 | 4 | * Copyright (C) 2017 Linaro Ltd. |
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| 4 | | - * |
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| 5 | | - * This program is free software; you can redistribute it and/or modify |
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| 6 | | - * it under the terms of the GNU General Public License version 2 and |
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| 7 | | - * only version 2 as published by the Free Software Foundation. |
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| 8 | | - * |
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| 9 | | - * This program is distributed in the hope that it will be useful, |
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| 10 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 11 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 12 | | - * GNU General Public License for more details. |
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| 13 | | - * |
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| 14 | 5 | */ |
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| 15 | 6 | |
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| 16 | 7 | #include <linux/delay.h> |
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| .. | .. |
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| 19 | 10 | #include <linux/interrupt.h> |
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| 20 | 11 | #include <linux/iopoll.h> |
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| 21 | 12 | #include <linux/kernel.h> |
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| 22 | | -#include <linux/qcom_scm.h> |
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| 23 | 13 | #include <linux/slab.h> |
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| 24 | 14 | |
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| 25 | 15 | #include "core.h" |
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| .. | .. |
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| 27 | 17 | #include "hfi_msgs.h" |
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| 28 | 18 | #include "hfi_venus.h" |
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| 29 | 19 | #include "hfi_venus_io.h" |
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| 20 | +#include "firmware.h" |
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| 30 | 21 | |
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| 31 | 22 | #define HFI_MASK_QHDR_TX_TYPE 0xff000000 |
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| 32 | 23 | #define HFI_MASK_QHDR_RX_TYPE 0x00ff0000 |
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| .. | .. |
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| 54 | 45 | #define IFACEQ_VAR_SMALL_PKT_SIZE 100 |
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| 55 | 46 | #define IFACEQ_VAR_LARGE_PKT_SIZE 512 |
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| 56 | 47 | #define IFACEQ_VAR_HUGE_PKT_SIZE (1024 * 12) |
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| 57 | | - |
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| 58 | | -enum tzbsp_video_state { |
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| 59 | | - TZBSP_VIDEO_STATE_SUSPEND = 0, |
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| 60 | | - TZBSP_VIDEO_STATE_RESUME |
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| 61 | | -}; |
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| 62 | 48 | |
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| 63 | 49 | struct hfi_queue_table_header { |
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| 64 | 50 | u32 version; |
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| .. | .. |
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| 144 | 130 | }; |
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| 145 | 131 | |
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| 146 | 132 | static bool venus_pkt_debug; |
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| 147 | | -static int venus_fw_debug = HFI_DEBUG_MSG_ERROR | HFI_DEBUG_MSG_FATAL; |
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| 133 | +int venus_fw_debug = HFI_DEBUG_MSG_ERROR | HFI_DEBUG_MSG_FATAL; |
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| 148 | 134 | static bool venus_sys_idle_indicator; |
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| 149 | 135 | static bool venus_fw_low_power_mode = true; |
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| 150 | 136 | static int venus_hw_rsp_timeout = 1000; |
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| .. | .. |
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| 359 | 345 | dma_free_attrs(dev, mem->size, mem->kva, mem->da, mem->attrs); |
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| 360 | 346 | } |
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| 361 | 347 | |
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| 362 | | -static void venus_writel(struct venus_hfi_device *hdev, u32 reg, u32 value) |
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| 363 | | -{ |
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| 364 | | - writel(value, hdev->core->base + reg); |
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| 365 | | -} |
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| 366 | | - |
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| 367 | | -static u32 venus_readl(struct venus_hfi_device *hdev, u32 reg) |
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| 368 | | -{ |
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| 369 | | - return readl(hdev->core->base + reg); |
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| 370 | | -} |
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| 371 | | - |
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| 372 | 348 | static void venus_set_registers(struct venus_hfi_device *hdev) |
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| 373 | 349 | { |
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| 374 | 350 | const struct venus_resources *res = hdev->core->res; |
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| .. | .. |
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| 377 | 353 | unsigned int i; |
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| 378 | 354 | |
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| 379 | 355 | for (i = 0; i < count; i++) |
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| 380 | | - venus_writel(hdev, tbl[i].reg, tbl[i].value); |
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| 356 | + writel(tbl[i].value, hdev->core->base + tbl[i].reg); |
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| 381 | 357 | } |
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| 382 | 358 | |
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| 383 | 359 | static void venus_soft_int(struct venus_hfi_device *hdev) |
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| 384 | 360 | { |
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| 385 | | - venus_writel(hdev, CPU_IC_SOFTINT, BIT(CPU_IC_SOFTINT_H2A_SHIFT)); |
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| 361 | + void __iomem *cpu_ic_base = hdev->core->cpu_ic_base; |
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| 362 | + |
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| 363 | + writel(BIT(CPU_IC_SOFTINT_H2A_SHIFT), cpu_ic_base + CPU_IC_SOFTINT); |
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| 386 | 364 | } |
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| 387 | 365 | |
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| 388 | 366 | static int venus_iface_cmdq_write_nolock(struct venus_hfi_device *hdev, |
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| .. | .. |
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| 453 | 431 | { |
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| 454 | 432 | struct device *dev = hdev->core->dev; |
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| 455 | 433 | static const unsigned int max_tries = 100; |
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| 456 | | - u32 ctrl_status = 0; |
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| 434 | + u32 ctrl_status = 0, mask_val; |
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| 457 | 435 | unsigned int count = 0; |
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| 436 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
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| 437 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
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| 458 | 438 | int ret = 0; |
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| 459 | 439 | |
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| 460 | | - venus_writel(hdev, VIDC_CTRL_INIT, BIT(VIDC_CTRL_INIT_CTRL_SHIFT)); |
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| 461 | | - venus_writel(hdev, WRAPPER_INTR_MASK, WRAPPER_INTR_MASK_A2HVCODEC_MASK); |
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| 462 | | - venus_writel(hdev, CPU_CS_SCIACMDARG3, 1); |
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| 440 | + if (IS_V6(hdev->core)) { |
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| 441 | + mask_val = readl(wrapper_base + WRAPPER_INTR_MASK); |
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| 442 | + mask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BASK_V6 | |
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| 443 | + WRAPPER_INTR_MASK_A2HCPU_MASK); |
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| 444 | + } else { |
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| 445 | + mask_val = WRAPPER_INTR_MASK_A2HVCODEC_MASK; |
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| 446 | + } |
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| 447 | + writel(mask_val, wrapper_base + WRAPPER_INTR_MASK); |
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| 448 | + writel(1, cpu_cs_base + CPU_CS_SCIACMDARG3); |
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| 463 | 449 | |
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| 450 | + writel(BIT(VIDC_CTRL_INIT_CTRL_SHIFT), cpu_cs_base + VIDC_CTRL_INIT); |
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| 464 | 451 | while (!ctrl_status && count < max_tries) { |
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| 465 | | - ctrl_status = venus_readl(hdev, CPU_CS_SCIACMDARG0); |
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| 452 | + ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0); |
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| 466 | 453 | if ((ctrl_status & CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK) == 4) { |
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| 467 | 454 | dev_err(dev, "invalid setting for UC_REGION\n"); |
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| 468 | 455 | ret = -EINVAL; |
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| .. | .. |
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| 476 | 463 | if (count >= max_tries) |
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| 477 | 464 | ret = -ETIMEDOUT; |
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| 478 | 465 | |
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| 466 | + if (IS_V6(hdev->core)) |
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| 467 | + writel(0x0, cpu_cs_base + CPU_CS_X2RPMH_V6); |
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| 468 | + |
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| 479 | 469 | return ret; |
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| 480 | 470 | } |
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| 481 | 471 | |
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| 482 | 472 | static u32 venus_hwversion(struct venus_hfi_device *hdev) |
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| 483 | 473 | { |
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| 484 | 474 | struct device *dev = hdev->core->dev; |
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| 485 | | - u32 ver = venus_readl(hdev, WRAPPER_HW_VERSION); |
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| 475 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
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| 476 | + u32 ver; |
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| 486 | 477 | u32 major, minor, step; |
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| 487 | 478 | |
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| 479 | + ver = readl(wrapper_base + WRAPPER_HW_VERSION); |
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| 488 | 480 | major = ver & WRAPPER_HW_VERSION_MAJOR_VERSION_MASK; |
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| 489 | 481 | major = major >> WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT; |
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| 490 | 482 | minor = ver & WRAPPER_HW_VERSION_MINOR_VERSION_MASK; |
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| 491 | 483 | minor = minor >> WRAPPER_HW_VERSION_MINOR_VERSION_SHIFT; |
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| 492 | 484 | step = ver & WRAPPER_HW_VERSION_STEP_VERSION_MASK; |
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| 493 | 485 | |
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| 494 | | - dev_dbg(dev, "venus hw version %x.%x.%x\n", major, minor, step); |
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| 486 | + dev_dbg(dev, VDBGL "venus hw version %x.%x.%x\n", major, minor, step); |
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| 495 | 487 | |
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| 496 | 488 | return major; |
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| 497 | 489 | } |
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| .. | .. |
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| 499 | 491 | static int venus_run(struct venus_hfi_device *hdev) |
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| 500 | 492 | { |
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| 501 | 493 | struct device *dev = hdev->core->dev; |
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| 494 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
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| 502 | 495 | int ret; |
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| 503 | 496 | |
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| 504 | 497 | /* |
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| .. | .. |
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| 507 | 500 | */ |
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| 508 | 501 | venus_set_registers(hdev); |
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| 509 | 502 | |
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| 510 | | - venus_writel(hdev, UC_REGION_ADDR, hdev->ifaceq_table.da); |
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| 511 | | - venus_writel(hdev, UC_REGION_SIZE, SHARED_QSIZE); |
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| 512 | | - venus_writel(hdev, CPU_CS_SCIACMDARG2, hdev->ifaceq_table.da); |
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| 513 | | - venus_writel(hdev, CPU_CS_SCIACMDARG1, 0x01); |
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| 503 | + writel(hdev->ifaceq_table.da, cpu_cs_base + UC_REGION_ADDR); |
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| 504 | + writel(SHARED_QSIZE, cpu_cs_base + UC_REGION_SIZE); |
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| 505 | + writel(hdev->ifaceq_table.da, cpu_cs_base + CPU_CS_SCIACMDARG2); |
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| 506 | + writel(0x01, cpu_cs_base + CPU_CS_SCIACMDARG1); |
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| 514 | 507 | if (hdev->sfr.da) |
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| 515 | | - venus_writel(hdev, SFR_ADDR, hdev->sfr.da); |
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| 508 | + writel(hdev->sfr.da, cpu_cs_base + SFR_ADDR); |
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| 516 | 509 | |
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| 517 | 510 | ret = venus_boot_core(hdev); |
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| 518 | 511 | if (ret) { |
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| .. | .. |
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| 527 | 520 | |
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| 528 | 521 | static int venus_halt_axi(struct venus_hfi_device *hdev) |
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| 529 | 522 | { |
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| 530 | | - void __iomem *base = hdev->core->base; |
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| 523 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
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| 524 | + void __iomem *vbif_base = hdev->core->vbif_base; |
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| 531 | 525 | struct device *dev = hdev->core->dev; |
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| 532 | 526 | u32 val; |
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| 533 | 527 | int ret; |
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| 534 | 528 | |
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| 535 | 529 | if (IS_V4(hdev->core)) { |
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| 536 | | - val = venus_readl(hdev, WRAPPER_CPU_AXI_HALT); |
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| 530 | + val = readl(wrapper_base + WRAPPER_CPU_AXI_HALT); |
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| 537 | 531 | val |= WRAPPER_CPU_AXI_HALT_HALT; |
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| 538 | | - venus_writel(hdev, WRAPPER_CPU_AXI_HALT, val); |
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| 532 | + writel(val, wrapper_base + WRAPPER_CPU_AXI_HALT); |
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| 539 | 533 | |
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| 540 | | - ret = readl_poll_timeout(base + WRAPPER_CPU_AXI_HALT_STATUS, |
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| 534 | + ret = readl_poll_timeout(wrapper_base + WRAPPER_CPU_AXI_HALT_STATUS, |
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| 541 | 535 | val, |
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| 542 | 536 | val & WRAPPER_CPU_AXI_HALT_STATUS_IDLE, |
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| 543 | 537 | POLL_INTERVAL_US, |
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| .. | .. |
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| 551 | 545 | } |
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| 552 | 546 | |
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| 553 | 547 | /* Halt AXI and AXI IMEM VBIF Access */ |
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| 554 | | - val = venus_readl(hdev, VBIF_AXI_HALT_CTRL0); |
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| 548 | + val = readl(vbif_base + VBIF_AXI_HALT_CTRL0); |
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| 555 | 549 | val |= VBIF_AXI_HALT_CTRL0_HALT_REQ; |
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| 556 | | - venus_writel(hdev, VBIF_AXI_HALT_CTRL0, val); |
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| 550 | + writel(val, vbif_base + VBIF_AXI_HALT_CTRL0); |
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| 557 | 551 | |
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| 558 | 552 | /* Request for AXI bus port halt */ |
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| 559 | | - ret = readl_poll_timeout(base + VBIF_AXI_HALT_CTRL1, val, |
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| 553 | + ret = readl_poll_timeout(vbif_base + VBIF_AXI_HALT_CTRL1, val, |
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| 560 | 554 | val & VBIF_AXI_HALT_CTRL1_HALT_ACK, |
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| 561 | 555 | POLL_INTERVAL_US, |
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| 562 | 556 | VBIF_AXI_HALT_ACK_TIMEOUT_US); |
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| .. | .. |
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| 575 | 569 | if (!hdev->power_enabled) |
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| 576 | 570 | return 0; |
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| 577 | 571 | |
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| 578 | | - ret = qcom_scm_set_remote_state(TZBSP_VIDEO_STATE_SUSPEND, 0); |
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| 572 | + ret = venus_set_hw_state_suspend(hdev->core); |
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| 579 | 573 | if (ret) |
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| 580 | 574 | return ret; |
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| 581 | 575 | |
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| .. | .. |
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| 595 | 589 | if (hdev->power_enabled) |
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| 596 | 590 | return 0; |
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| 597 | 591 | |
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| 598 | | - ret = qcom_scm_set_remote_state(TZBSP_VIDEO_STATE_RESUME, 0); |
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| 592 | + ret = venus_set_hw_state_resume(hdev->core); |
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| 599 | 593 | if (ret) |
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| 600 | 594 | goto err; |
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| 601 | 595 | |
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| .. | .. |
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| 608 | 602 | return 0; |
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| 609 | 603 | |
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| 610 | 604 | err_suspend: |
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| 611 | | - qcom_scm_set_remote_state(TZBSP_VIDEO_STATE_SUSPEND, 0); |
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| 605 | + venus_set_hw_state_suspend(hdev->core); |
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| 612 | 606 | err: |
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| 613 | 607 | hdev->power_enabled = false; |
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| 614 | 608 | return ret; |
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| .. | .. |
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| 920 | 914 | if (pkt->hdr.pkt_type != HFI_MSG_SYS_COV) { |
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| 921 | 915 | struct hfi_msg_sys_debug_pkt *pkt = packet; |
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| 922 | 916 | |
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| 923 | | - dev_dbg(dev, "%s", pkt->msg_data); |
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| 917 | + dev_dbg(dev, VDBGFW "%s", pkt->msg_data); |
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| 924 | 918 | } |
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| 925 | 919 | } |
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| 926 | 920 | } |
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| .. | .. |
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| 1000 | 994 | |
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| 1001 | 995 | venus_set_state(hdev, VENUS_STATE_DEINIT); |
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| 1002 | 996 | |
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| 1003 | | - /* |
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| 1004 | | - * Once SYS_ERROR received from HW, it is safe to halt the AXI. |
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| 1005 | | - * With SYS_ERROR, Venus FW may have crashed and HW might be |
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| 1006 | | - * active and causing unnecessary transactions. Hence it is |
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| 1007 | | - * safe to stop all AXI transactions from venus subsystem. |
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| 1008 | | - */ |
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| 1009 | | - venus_halt_axi(hdev); |
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| 1010 | 997 | venus_sfr_print(hdev); |
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| 1011 | 998 | } |
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| 1012 | 999 | |
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| .. | .. |
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| 1023 | 1010 | res = hdev->core->res; |
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| 1024 | 1011 | pkt = hdev->pkt_buf; |
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| 1025 | 1012 | |
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| 1026 | | - if (hdev->irq_status & WRAPPER_INTR_STATUS_A2HWD_MASK) { |
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| 1027 | | - venus_sfr_print(hdev); |
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| 1028 | | - hfi_process_watchdog_timeout(core); |
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| 1029 | | - } |
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| 1030 | 1013 | |
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| 1031 | 1014 | while (!venus_iface_msgq_read(hdev, pkt)) { |
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| 1032 | 1015 | msg_ret = hfi_process_msg_packet(core, pkt); |
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| .. | .. |
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| 1060 | 1043 | { |
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| 1061 | 1044 | struct venus_hfi_device *hdev = to_hfi_priv(core); |
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| 1062 | 1045 | u32 status; |
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| 1046 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
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| 1047 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
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| 1063 | 1048 | |
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| 1064 | 1049 | if (!hdev) |
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| 1065 | 1050 | return IRQ_NONE; |
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| 1066 | 1051 | |
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| 1067 | | - status = venus_readl(hdev, WRAPPER_INTR_STATUS); |
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| 1052 | + status = readl(wrapper_base + WRAPPER_INTR_STATUS); |
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| 1068 | 1053 | |
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| 1069 | 1054 | if (status & WRAPPER_INTR_STATUS_A2H_MASK || |
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| 1070 | 1055 | status & WRAPPER_INTR_STATUS_A2HWD_MASK || |
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| 1071 | 1056 | status & CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK) |
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| 1072 | 1057 | hdev->irq_status = status; |
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| 1073 | 1058 | |
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| 1074 | | - venus_writel(hdev, CPU_CS_A2HSOFTINTCLR, 1); |
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| 1075 | | - venus_writel(hdev, WRAPPER_INTR_CLEAR, status); |
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| 1059 | + writel(1, cpu_cs_base + CPU_CS_A2HSOFTINTCLR); |
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| 1060 | + writel(status, wrapper_base + WRAPPER_INTR_CLEAR); |
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| 1076 | 1061 | |
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| 1077 | 1062 | return IRQ_WAKE_THREAD; |
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| 1078 | 1063 | } |
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| .. | .. |
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| 1146 | 1131 | struct venus_hfi_device *hdev = to_hfi_priv(inst->core); |
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| 1147 | 1132 | struct hfi_session_init_pkt pkt; |
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| 1148 | 1133 | int ret; |
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| 1134 | + |
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| 1135 | + ret = venus_sys_set_debug(hdev, venus_fw_debug); |
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| 1136 | + if (ret) |
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| 1137 | + goto err; |
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| 1149 | 1138 | |
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| 1150 | 1139 | ret = pkt_session_init(&pkt, inst, session_type, codec); |
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| 1151 | 1140 | if (ret) |
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| .. | .. |
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| 1355 | 1344 | pkt = (struct hfi_session_set_property_pkt *)packet; |
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| 1356 | 1345 | |
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| 1357 | 1346 | ret = pkt_session_set_property(pkt, inst, ptype, pdata); |
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| 1347 | + if (ret == -ENOTSUPP) |
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| 1348 | + return 0; |
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| 1358 | 1349 | if (ret) |
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| 1359 | 1350 | return ret; |
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| 1360 | 1351 | |
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| .. | .. |
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| 1399 | 1390 | { |
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| 1400 | 1391 | struct venus_hfi_device *hdev = to_hfi_priv(core); |
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| 1401 | 1392 | struct device *dev = core->dev; |
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| 1393 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
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| 1402 | 1394 | u32 ctrl_status; |
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| 1403 | 1395 | int ret; |
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| 1404 | 1396 | |
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| .. | .. |
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| 1433 | 1425 | return -EINVAL; |
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| 1434 | 1426 | } |
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| 1435 | 1427 | |
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| 1436 | | - ctrl_status = venus_readl(hdev, CPU_CS_SCIACMDARG0); |
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| 1428 | + ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0); |
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| 1437 | 1429 | if (!(ctrl_status & CPU_CS_SCIACMDARG0_PC_READY)) { |
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| 1438 | 1430 | mutex_unlock(&hdev->lock); |
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| 1439 | 1431 | return -EINVAL; |
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| .. | .. |
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| 1454 | 1446 | |
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| 1455 | 1447 | static bool venus_cpu_and_video_core_idle(struct venus_hfi_device *hdev) |
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| 1456 | 1448 | { |
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| 1449 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
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| 1450 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
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| 1457 | 1451 | u32 ctrl_status, cpu_status; |
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| 1458 | 1452 | |
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| 1459 | | - cpu_status = venus_readl(hdev, WRAPPER_CPU_STATUS); |
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| 1460 | | - ctrl_status = venus_readl(hdev, CPU_CS_SCIACMDARG0); |
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| 1453 | + cpu_status = readl(wrapper_base + WRAPPER_CPU_STATUS); |
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| 1454 | + ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0); |
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| 1461 | 1455 | |
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| 1462 | 1456 | if (cpu_status & WRAPPER_CPU_STATUS_WFI && |
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| 1463 | 1457 | ctrl_status & CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK) |
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| .. | .. |
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| 1468 | 1462 | |
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| 1469 | 1463 | static bool venus_cpu_idle_and_pc_ready(struct venus_hfi_device *hdev) |
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| 1470 | 1464 | { |
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| 1465 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
|---|
| 1466 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
|---|
| 1471 | 1467 | u32 ctrl_status, cpu_status; |
|---|
| 1472 | 1468 | |
|---|
| 1473 | | - cpu_status = venus_readl(hdev, WRAPPER_CPU_STATUS); |
|---|
| 1474 | | - ctrl_status = venus_readl(hdev, CPU_CS_SCIACMDARG0); |
|---|
| 1469 | + cpu_status = readl(wrapper_base + WRAPPER_CPU_STATUS); |
|---|
| 1470 | + ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0); |
|---|
| 1475 | 1471 | |
|---|
| 1476 | 1472 | if (cpu_status & WRAPPER_CPU_STATUS_WFI && |
|---|
| 1477 | 1473 | ctrl_status & CPU_CS_SCIACMDARG0_PC_READY) |
|---|
| .. | .. |
|---|
| 1484 | 1480 | { |
|---|
| 1485 | 1481 | struct venus_hfi_device *hdev = to_hfi_priv(core); |
|---|
| 1486 | 1482 | struct device *dev = core->dev; |
|---|
| 1483 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
|---|
| 1487 | 1484 | u32 ctrl_status; |
|---|
| 1488 | 1485 | bool val; |
|---|
| 1489 | 1486 | int ret; |
|---|
| .. | .. |
|---|
| 1500 | 1497 | return -EINVAL; |
|---|
| 1501 | 1498 | } |
|---|
| 1502 | 1499 | |
|---|
| 1503 | | - ctrl_status = venus_readl(hdev, CPU_CS_SCIACMDARG0); |
|---|
| 1500 | + ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0); |
|---|
| 1504 | 1501 | if (ctrl_status & CPU_CS_SCIACMDARG0_PC_READY) |
|---|
| 1505 | 1502 | goto power_off; |
|---|
| 1506 | 1503 | |
|---|
| .. | .. |
|---|
| 1626 | 1623 | core->ops = NULL; |
|---|
| 1627 | 1624 | return ret; |
|---|
| 1628 | 1625 | } |
|---|
| 1626 | + |
|---|
| 1627 | +void venus_hfi_queues_reinit(struct venus_core *core) |
|---|
| 1628 | +{ |
|---|
| 1629 | + struct venus_hfi_device *hdev = to_hfi_priv(core); |
|---|
| 1630 | + struct hfi_queue_table_header *tbl_hdr; |
|---|
| 1631 | + struct iface_queue *queue; |
|---|
| 1632 | + struct hfi_sfr *sfr; |
|---|
| 1633 | + unsigned int i; |
|---|
| 1634 | + |
|---|
| 1635 | + mutex_lock(&hdev->lock); |
|---|
| 1636 | + |
|---|
| 1637 | + for (i = 0; i < IFACEQ_NUM; i++) { |
|---|
| 1638 | + queue = &hdev->queues[i]; |
|---|
| 1639 | + queue->qhdr = |
|---|
| 1640 | + IFACEQ_GET_QHDR_START_ADDR(hdev->ifaceq_table.kva, i); |
|---|
| 1641 | + |
|---|
| 1642 | + venus_set_qhdr_defaults(queue->qhdr); |
|---|
| 1643 | + |
|---|
| 1644 | + queue->qhdr->start_addr = queue->qmem.da; |
|---|
| 1645 | + |
|---|
| 1646 | + if (i == IFACEQ_CMD_IDX) |
|---|
| 1647 | + queue->qhdr->type |= HFI_HOST_TO_CTRL_CMD_Q; |
|---|
| 1648 | + else if (i == IFACEQ_MSG_IDX) |
|---|
| 1649 | + queue->qhdr->type |= HFI_CTRL_TO_HOST_MSG_Q; |
|---|
| 1650 | + else if (i == IFACEQ_DBG_IDX) |
|---|
| 1651 | + queue->qhdr->type |= HFI_CTRL_TO_HOST_DBG_Q; |
|---|
| 1652 | + } |
|---|
| 1653 | + |
|---|
| 1654 | + tbl_hdr = hdev->ifaceq_table.kva; |
|---|
| 1655 | + tbl_hdr->version = 0; |
|---|
| 1656 | + tbl_hdr->size = IFACEQ_TABLE_SIZE; |
|---|
| 1657 | + tbl_hdr->qhdr0_offset = sizeof(struct hfi_queue_table_header); |
|---|
| 1658 | + tbl_hdr->qhdr_size = sizeof(struct hfi_queue_header); |
|---|
| 1659 | + tbl_hdr->num_q = IFACEQ_NUM; |
|---|
| 1660 | + tbl_hdr->num_active_q = IFACEQ_NUM; |
|---|
| 1661 | + |
|---|
| 1662 | + /* |
|---|
| 1663 | + * Set receive request to zero on debug queue as there is no |
|---|
| 1664 | + * need of interrupt from video hardware for debug messages |
|---|
| 1665 | + */ |
|---|
| 1666 | + queue = &hdev->queues[IFACEQ_DBG_IDX]; |
|---|
| 1667 | + queue->qhdr->rx_req = 0; |
|---|
| 1668 | + |
|---|
| 1669 | + sfr = hdev->sfr.kva; |
|---|
| 1670 | + sfr->buf_size = ALIGNED_SFR_SIZE; |
|---|
| 1671 | + |
|---|
| 1672 | + /* ensure table and queue header structs are settled in memory */ |
|---|
| 1673 | + wmb(); |
|---|
| 1674 | + |
|---|
| 1675 | + mutex_unlock(&hdev->lock); |
|---|
| 1676 | +} |
|---|