| .. | .. |
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| 345 | 345 | dma_free_attrs(dev, mem->size, mem->kva, mem->da, mem->attrs); |
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| 346 | 346 | } |
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| 347 | 347 | |
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| 348 | | -static void venus_writel(struct venus_hfi_device *hdev, u32 reg, u32 value) |
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| 349 | | -{ |
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| 350 | | - writel(value, hdev->core->base + reg); |
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| 351 | | -} |
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| 352 | | - |
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| 353 | | -static u32 venus_readl(struct venus_hfi_device *hdev, u32 reg) |
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| 354 | | -{ |
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| 355 | | - return readl(hdev->core->base + reg); |
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| 356 | | -} |
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| 357 | | - |
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| 358 | 348 | static void venus_set_registers(struct venus_hfi_device *hdev) |
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| 359 | 349 | { |
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| 360 | 350 | const struct venus_resources *res = hdev->core->res; |
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| .. | .. |
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| 363 | 353 | unsigned int i; |
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| 364 | 354 | |
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| 365 | 355 | for (i = 0; i < count; i++) |
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| 366 | | - venus_writel(hdev, tbl[i].reg, tbl[i].value); |
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| 356 | + writel(tbl[i].value, hdev->core->base + tbl[i].reg); |
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| 367 | 357 | } |
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| 368 | 358 | |
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| 369 | 359 | static void venus_soft_int(struct venus_hfi_device *hdev) |
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| 370 | 360 | { |
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| 371 | | - venus_writel(hdev, CPU_IC_SOFTINT, BIT(CPU_IC_SOFTINT_H2A_SHIFT)); |
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| 361 | + void __iomem *cpu_ic_base = hdev->core->cpu_ic_base; |
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| 362 | + |
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| 363 | + writel(BIT(CPU_IC_SOFTINT_H2A_SHIFT), cpu_ic_base + CPU_IC_SOFTINT); |
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| 372 | 364 | } |
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| 373 | 365 | |
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| 374 | 366 | static int venus_iface_cmdq_write_nolock(struct venus_hfi_device *hdev, |
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| .. | .. |
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| 439 | 431 | { |
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| 440 | 432 | struct device *dev = hdev->core->dev; |
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| 441 | 433 | static const unsigned int max_tries = 100; |
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| 442 | | - u32 ctrl_status = 0; |
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| 434 | + u32 ctrl_status = 0, mask_val; |
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| 443 | 435 | unsigned int count = 0; |
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| 436 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
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| 437 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
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| 444 | 438 | int ret = 0; |
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| 445 | 439 | |
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| 446 | | - venus_writel(hdev, VIDC_CTRL_INIT, BIT(VIDC_CTRL_INIT_CTRL_SHIFT)); |
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| 447 | | - venus_writel(hdev, WRAPPER_INTR_MASK, WRAPPER_INTR_MASK_A2HVCODEC_MASK); |
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| 448 | | - venus_writel(hdev, CPU_CS_SCIACMDARG3, 1); |
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| 440 | + if (IS_V6(hdev->core)) { |
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| 441 | + mask_val = readl(wrapper_base + WRAPPER_INTR_MASK); |
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| 442 | + mask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BASK_V6 | |
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| 443 | + WRAPPER_INTR_MASK_A2HCPU_MASK); |
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| 444 | + } else { |
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| 445 | + mask_val = WRAPPER_INTR_MASK_A2HVCODEC_MASK; |
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| 446 | + } |
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| 447 | + writel(mask_val, wrapper_base + WRAPPER_INTR_MASK); |
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| 448 | + writel(1, cpu_cs_base + CPU_CS_SCIACMDARG3); |
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| 449 | 449 | |
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| 450 | + writel(BIT(VIDC_CTRL_INIT_CTRL_SHIFT), cpu_cs_base + VIDC_CTRL_INIT); |
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| 450 | 451 | while (!ctrl_status && count < max_tries) { |
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| 451 | | - ctrl_status = venus_readl(hdev, CPU_CS_SCIACMDARG0); |
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| 452 | + ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0); |
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| 452 | 453 | if ((ctrl_status & CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK) == 4) { |
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| 453 | 454 | dev_err(dev, "invalid setting for UC_REGION\n"); |
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| 454 | 455 | ret = -EINVAL; |
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| .. | .. |
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| 462 | 463 | if (count >= max_tries) |
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| 463 | 464 | ret = -ETIMEDOUT; |
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| 464 | 465 | |
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| 466 | + if (IS_V6(hdev->core)) |
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| 467 | + writel(0x0, cpu_cs_base + CPU_CS_X2RPMH_V6); |
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| 468 | + |
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| 465 | 469 | return ret; |
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| 466 | 470 | } |
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| 467 | 471 | |
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| 468 | 472 | static u32 venus_hwversion(struct venus_hfi_device *hdev) |
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| 469 | 473 | { |
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| 470 | 474 | struct device *dev = hdev->core->dev; |
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| 471 | | - u32 ver = venus_readl(hdev, WRAPPER_HW_VERSION); |
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| 475 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
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| 476 | + u32 ver; |
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| 472 | 477 | u32 major, minor, step; |
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| 473 | 478 | |
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| 479 | + ver = readl(wrapper_base + WRAPPER_HW_VERSION); |
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| 474 | 480 | major = ver & WRAPPER_HW_VERSION_MAJOR_VERSION_MASK; |
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| 475 | 481 | major = major >> WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT; |
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| 476 | 482 | minor = ver & WRAPPER_HW_VERSION_MINOR_VERSION_MASK; |
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| .. | .. |
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| 485 | 491 | static int venus_run(struct venus_hfi_device *hdev) |
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| 486 | 492 | { |
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| 487 | 493 | struct device *dev = hdev->core->dev; |
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| 494 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
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| 488 | 495 | int ret; |
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| 489 | 496 | |
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| 490 | 497 | /* |
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| .. | .. |
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| 493 | 500 | */ |
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| 494 | 501 | venus_set_registers(hdev); |
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| 495 | 502 | |
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| 496 | | - venus_writel(hdev, UC_REGION_ADDR, hdev->ifaceq_table.da); |
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| 497 | | - venus_writel(hdev, UC_REGION_SIZE, SHARED_QSIZE); |
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| 498 | | - venus_writel(hdev, CPU_CS_SCIACMDARG2, hdev->ifaceq_table.da); |
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| 499 | | - venus_writel(hdev, CPU_CS_SCIACMDARG1, 0x01); |
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| 503 | + writel(hdev->ifaceq_table.da, cpu_cs_base + UC_REGION_ADDR); |
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| 504 | + writel(SHARED_QSIZE, cpu_cs_base + UC_REGION_SIZE); |
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| 505 | + writel(hdev->ifaceq_table.da, cpu_cs_base + CPU_CS_SCIACMDARG2); |
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| 506 | + writel(0x01, cpu_cs_base + CPU_CS_SCIACMDARG1); |
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| 500 | 507 | if (hdev->sfr.da) |
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| 501 | | - venus_writel(hdev, SFR_ADDR, hdev->sfr.da); |
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| 508 | + writel(hdev->sfr.da, cpu_cs_base + SFR_ADDR); |
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| 502 | 509 | |
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| 503 | 510 | ret = venus_boot_core(hdev); |
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| 504 | 511 | if (ret) { |
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| .. | .. |
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| 513 | 520 | |
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| 514 | 521 | static int venus_halt_axi(struct venus_hfi_device *hdev) |
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| 515 | 522 | { |
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| 516 | | - void __iomem *base = hdev->core->base; |
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| 523 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
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| 524 | + void __iomem *vbif_base = hdev->core->vbif_base; |
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| 517 | 525 | struct device *dev = hdev->core->dev; |
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| 518 | 526 | u32 val; |
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| 519 | 527 | int ret; |
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| 520 | 528 | |
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| 521 | 529 | if (IS_V4(hdev->core)) { |
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| 522 | | - val = venus_readl(hdev, WRAPPER_CPU_AXI_HALT); |
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| 530 | + val = readl(wrapper_base + WRAPPER_CPU_AXI_HALT); |
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| 523 | 531 | val |= WRAPPER_CPU_AXI_HALT_HALT; |
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| 524 | | - venus_writel(hdev, WRAPPER_CPU_AXI_HALT, val); |
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| 532 | + writel(val, wrapper_base + WRAPPER_CPU_AXI_HALT); |
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| 525 | 533 | |
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| 526 | | - ret = readl_poll_timeout(base + WRAPPER_CPU_AXI_HALT_STATUS, |
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| 534 | + ret = readl_poll_timeout(wrapper_base + WRAPPER_CPU_AXI_HALT_STATUS, |
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| 527 | 535 | val, |
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| 528 | 536 | val & WRAPPER_CPU_AXI_HALT_STATUS_IDLE, |
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| 529 | 537 | POLL_INTERVAL_US, |
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| .. | .. |
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| 537 | 545 | } |
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| 538 | 546 | |
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| 539 | 547 | /* Halt AXI and AXI IMEM VBIF Access */ |
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| 540 | | - val = venus_readl(hdev, VBIF_AXI_HALT_CTRL0); |
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| 548 | + val = readl(vbif_base + VBIF_AXI_HALT_CTRL0); |
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| 541 | 549 | val |= VBIF_AXI_HALT_CTRL0_HALT_REQ; |
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| 542 | | - venus_writel(hdev, VBIF_AXI_HALT_CTRL0, val); |
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| 550 | + writel(val, vbif_base + VBIF_AXI_HALT_CTRL0); |
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| 543 | 551 | |
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| 544 | 552 | /* Request for AXI bus port halt */ |
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| 545 | | - ret = readl_poll_timeout(base + VBIF_AXI_HALT_CTRL1, val, |
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| 553 | + ret = readl_poll_timeout(vbif_base + VBIF_AXI_HALT_CTRL1, val, |
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| 546 | 554 | val & VBIF_AXI_HALT_CTRL1_HALT_ACK, |
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| 547 | 555 | POLL_INTERVAL_US, |
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| 548 | 556 | VBIF_AXI_HALT_ACK_TIMEOUT_US); |
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| .. | .. |
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| 1035 | 1043 | { |
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| 1036 | 1044 | struct venus_hfi_device *hdev = to_hfi_priv(core); |
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| 1037 | 1045 | u32 status; |
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| 1046 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
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| 1047 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
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| 1038 | 1048 | |
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| 1039 | 1049 | if (!hdev) |
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| 1040 | 1050 | return IRQ_NONE; |
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| 1041 | 1051 | |
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| 1042 | | - status = venus_readl(hdev, WRAPPER_INTR_STATUS); |
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| 1052 | + status = readl(wrapper_base + WRAPPER_INTR_STATUS); |
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| 1043 | 1053 | |
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| 1044 | 1054 | if (status & WRAPPER_INTR_STATUS_A2H_MASK || |
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| 1045 | 1055 | status & WRAPPER_INTR_STATUS_A2HWD_MASK || |
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| 1046 | 1056 | status & CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK) |
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| 1047 | 1057 | hdev->irq_status = status; |
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| 1048 | 1058 | |
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| 1049 | | - venus_writel(hdev, CPU_CS_A2HSOFTINTCLR, 1); |
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| 1050 | | - venus_writel(hdev, WRAPPER_INTR_CLEAR, status); |
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| 1059 | + writel(1, cpu_cs_base + CPU_CS_A2HSOFTINTCLR); |
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| 1060 | + writel(status, wrapper_base + WRAPPER_INTR_CLEAR); |
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| 1051 | 1061 | |
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| 1052 | 1062 | return IRQ_WAKE_THREAD; |
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| 1053 | 1063 | } |
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| .. | .. |
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| 1380 | 1390 | { |
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| 1381 | 1391 | struct venus_hfi_device *hdev = to_hfi_priv(core); |
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| 1382 | 1392 | struct device *dev = core->dev; |
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| 1393 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
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| 1383 | 1394 | u32 ctrl_status; |
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| 1384 | 1395 | int ret; |
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| 1385 | 1396 | |
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| .. | .. |
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| 1414 | 1425 | return -EINVAL; |
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| 1415 | 1426 | } |
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| 1416 | 1427 | |
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| 1417 | | - ctrl_status = venus_readl(hdev, CPU_CS_SCIACMDARG0); |
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| 1428 | + ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0); |
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| 1418 | 1429 | if (!(ctrl_status & CPU_CS_SCIACMDARG0_PC_READY)) { |
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| 1419 | 1430 | mutex_unlock(&hdev->lock); |
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| 1420 | 1431 | return -EINVAL; |
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| .. | .. |
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| 1435 | 1446 | |
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| 1436 | 1447 | static bool venus_cpu_and_video_core_idle(struct venus_hfi_device *hdev) |
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| 1437 | 1448 | { |
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| 1449 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
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| 1450 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
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| 1438 | 1451 | u32 ctrl_status, cpu_status; |
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| 1439 | 1452 | |
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| 1440 | | - cpu_status = venus_readl(hdev, WRAPPER_CPU_STATUS); |
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| 1441 | | - ctrl_status = venus_readl(hdev, CPU_CS_SCIACMDARG0); |
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| 1453 | + cpu_status = readl(wrapper_base + WRAPPER_CPU_STATUS); |
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| 1454 | + ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0); |
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| 1442 | 1455 | |
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| 1443 | 1456 | if (cpu_status & WRAPPER_CPU_STATUS_WFI && |
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| 1444 | 1457 | ctrl_status & CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK) |
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| .. | .. |
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| 1449 | 1462 | |
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| 1450 | 1463 | static bool venus_cpu_idle_and_pc_ready(struct venus_hfi_device *hdev) |
|---|
| 1451 | 1464 | { |
|---|
| 1465 | + void __iomem *wrapper_base = hdev->core->wrapper_base; |
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| 1466 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
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| 1452 | 1467 | u32 ctrl_status, cpu_status; |
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| 1453 | 1468 | |
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| 1454 | | - cpu_status = venus_readl(hdev, WRAPPER_CPU_STATUS); |
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| 1455 | | - ctrl_status = venus_readl(hdev, CPU_CS_SCIACMDARG0); |
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| 1469 | + cpu_status = readl(wrapper_base + WRAPPER_CPU_STATUS); |
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| 1470 | + ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0); |
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| 1456 | 1471 | |
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| 1457 | 1472 | if (cpu_status & WRAPPER_CPU_STATUS_WFI && |
|---|
| 1458 | 1473 | ctrl_status & CPU_CS_SCIACMDARG0_PC_READY) |
|---|
| .. | .. |
|---|
| 1465 | 1480 | { |
|---|
| 1466 | 1481 | struct venus_hfi_device *hdev = to_hfi_priv(core); |
|---|
| 1467 | 1482 | struct device *dev = core->dev; |
|---|
| 1483 | + void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; |
|---|
| 1468 | 1484 | u32 ctrl_status; |
|---|
| 1469 | 1485 | bool val; |
|---|
| 1470 | 1486 | int ret; |
|---|
| .. | .. |
|---|
| 1481 | 1497 | return -EINVAL; |
|---|
| 1482 | 1498 | } |
|---|
| 1483 | 1499 | |
|---|
| 1484 | | - ctrl_status = venus_readl(hdev, CPU_CS_SCIACMDARG0); |
|---|
| 1500 | + ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0); |
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| 1485 | 1501 | if (ctrl_status & CPU_CS_SCIACMDARG0_PC_READY) |
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| 1486 | 1502 | goto power_off; |
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| 1487 | 1503 | |
|---|