| .. | .. |
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| 51 | 51 | #define SC5336_REG_EXPOSURE_H 0x3e00 |
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| 52 | 52 | #define SC5336_REG_EXPOSURE_M 0x3e01 |
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| 53 | 53 | #define SC5336_REG_EXPOSURE_L 0x3e02 |
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| 54 | | -#define SC5336_EXPOSURE_MIN 1 |
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| 54 | +#define SC5336_EXPOSURE_MIN 2 |
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| 55 | 55 | #define SC5336_EXPOSURE_STEP 1 |
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| 56 | 56 | #define SC5336_VTS_MAX 0x7fff |
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| 57 | 57 | |
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| .. | .. |
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| 244 | 244 | {0x3633, 0x33}, |
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| 245 | 245 | {0x3638, 0xcf}, |
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| 246 | 246 | {0x363f, 0xc0}, |
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| 247 | | - {0x3641, 0x20}, |
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| 247 | + {0x3641, 0x38}, |
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| 248 | 248 | {0x3670, 0x56}, |
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| 249 | 249 | {0x3674, 0xc0}, |
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| 250 | 250 | {0x3675, 0xa0}, |
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| .. | .. |
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| 287 | 287 | {0x37fb, 0x24}, |
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| 288 | 288 | {0x37fc, 0x01}, |
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| 289 | 289 | {0x37fd, 0x36}, |
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| 290 | + {0x3900, 0x0d}, |
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| 290 | 291 | {0x3901, 0x00}, |
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| 291 | 292 | {0x3904, 0x04}, |
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| 292 | 293 | {0x3905, 0x8c}, |
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| .. | .. |
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| 866 | 867 | static int __sc5336_start_stream(struct sc5336 *sc5336) |
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| 867 | 868 | { |
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| 868 | 869 | int ret; |
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| 870 | + u32 chip_version = 0; |
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| 869 | 871 | |
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| 870 | 872 | if (!sc5336->is_thunderboot) { |
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| 871 | 873 | ret = sc5336_write_array(sc5336->client, sc5336->cur_mode->reg_list); |
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| .. | .. |
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| 877 | 879 | if (ret) |
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| 878 | 880 | return ret; |
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| 879 | 881 | } |
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| 882 | + ret = sc5336_read_reg(sc5336->client, 0x3040, SC5336_REG_VALUE_08BIT, &chip_version); |
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| 883 | + if (chip_version == 0x00) { |
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| 884 | + ret |= sc5336_write_reg(sc5336->client, 0x3258, SC5336_REG_VALUE_08BIT, 0x0c); |
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| 885 | + ret |= sc5336_write_reg(sc5336->client, 0x3249, SC5336_REG_VALUE_08BIT, 0x0b); |
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| 886 | + ret |= sc5336_write_reg(sc5336->client, 0x3934, SC5336_REG_VALUE_08BIT, 0x0a); |
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| 887 | + ret |= sc5336_write_reg(sc5336->client, 0x3935, SC5336_REG_VALUE_08BIT, 0x00); |
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| 888 | + ret |= sc5336_write_reg(sc5336->client, 0x3937, SC5336_REG_VALUE_08BIT, 0x75); |
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| 889 | + } else if (chip_version == 0x03) { |
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| 890 | + ret |= sc5336_write_reg(sc5336->client, 0x3258, SC5336_REG_VALUE_08BIT, 0x08); |
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| 891 | + ret |= sc5336_write_reg(sc5336->client, 0x3249, SC5336_REG_VALUE_08BIT, 0x07); |
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| 892 | + ret |= sc5336_write_reg(sc5336->client, 0x3934, SC5336_REG_VALUE_08BIT, 0x05); |
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| 893 | + ret |= sc5336_write_reg(sc5336->client, 0x3935, SC5336_REG_VALUE_08BIT, 0x07); |
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| 894 | + ret |= sc5336_write_reg(sc5336->client, 0x3937, SC5336_REG_VALUE_08BIT, 0x74); |
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| 895 | + } |
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| 896 | + if (ret) |
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| 897 | + return ret; |
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| 880 | 898 | |
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| 881 | 899 | return sc5336_write_reg(sc5336->client, SC5336_REG_CTRL_MODE, |
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| 882 | 900 | SC5336_REG_VALUE_08BIT, SC5336_MODE_STREAMING); |
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