forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/media/dvb-frontends/drx39xyj/drxj.c
....@@ -380,10 +380,10 @@
380380 */
381381 
382382 /*****************************************************************************/
383
-/* Audio block 0x103 is write only. To avoid shadowing in driver accessing    */
384
-/* RAM adresses directly. This must be READ ONLY to avoid problems.           */
385
-/* Writing to the interface adresses is more than only writing the RAM        */
386
-/* locations                                                                  */
383
+/* Audio block 0x103 is write only. To avoid shadowing in driver accessing   */
384
+/* RAM addresses directly. This must be READ ONLY to avoid problems.         */
385
+/* Writing to the interface addresses are more than only writing the RAM     */
386
+/* locations                                                                 */
387387 /*****************************************************************************/
388388 /*
389389 * \brief RAM location of MODUS registers
....@@ -656,8 +656,8 @@
656656 	false,			/* flag: true=bypass             */
657657 	ATV_TOP_VID_PEAK__PRE,	/* shadow of ATV_TOP_VID_PEAK__A */
658658 	ATV_TOP_NOISE_TH__PRE,	/* shadow of ATV_TOP_NOISE_TH__A */
659
-	true,			/* flag CVBS ouput enable        */
660
-	false,			/* flag SIF ouput enable         */
659
+	true,			/* flag CVBS output enable       */
660
+	false,			/* flag SIF output enable        */
661661 	DRXJ_SIF_ATTENUATION_0DB,	/* current SIF att setting       */
662662 	{			/* qam_rf_agc_cfg */
663663 	 DRX_STANDARD_ITU_B,	/* standard            */
....@@ -832,7 +832,7 @@
832832 	false,			/* If true mirror frequency spectrum            */
833833 	{
834834 	 /* MPEG output configuration */
835
-	 true,			/* If true, enable MPEG ouput    */
835
+	 true,			/* If true, enable MPEG output   */
836836 	 false,			/* If true, insert RS byte       */
837837 	 false,			/* If true, parallel out otherwise serial */
838838 	 false,			/* If true, invert DATA signals  */
....@@ -848,7 +848,7 @@
848848 	 DRX_MPEG_STR_WIDTH_1	/* MPEG Start width in clock cycles */
849849 	 },
850850 	/* Initilisations below can be omitted, they require no user input and
851
-	   are initialy 0, NULL or false. The compiler will initialize them to these
851
+	   are initially 0, NULL or false. The compiler will initialize them to these
852852 	   values when omitted.  */
853853 	false,			/* is_opened */
854854 
....@@ -869,7 +869,7 @@
869869 	DRX_POWER_UP,
870870 
871871 	/* Tuner */
872
-	1,			/* nr of I2C port to wich tuner is     */
872
+	1,			/* nr of I2C port to which tuner is    */
873873 	0L,			/* minimum RF input frequency, in kHz  */
874874 	0L,			/* maximum RF input frequency, in kHz  */
875875 	false,			/* Rf Agc Polarity                     */
....@@ -1656,7 +1656,7 @@
16561656 		   sequense will be visible: (1) write address {i2c addr,
16571657 		   4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
16581658 		   (3) write address (4) write data etc...
1659
-		   Address must be rewriten because HI is reset after data transport and
1659
+		   Address must be rewritten because HI is reset after data transport and
16601660 		   expects an address.
16611661 		 */
16621662 		todo = (block_size < datasize ? block_size : datasize);
....@@ -1820,7 +1820,7 @@
18201820 * \param wdata    Data to write
18211821 * \param rdata    Buffer for data to read
18221822 * \return int
1823
-* \retval 0 Succes
1823
+* \retval 0 Success
18241824 * \retval -EIO Timeout, I2C error, illegal bank
18251825 *
18261826 * 16 bits register read modify write access using short addressing format only.
....@@ -1897,7 +1897,7 @@
18971897 * \param addr
18981898 * \param data
18991899 * \return int
1900
-* \retval 0 Succes
1900
+* \retval 0 Success
19011901 * \retval -EIO Timeout, I2C error, illegal bank
19021902 *
19031903 * 16 bits register read access via audio token ring interface.
....@@ -2004,7 +2004,7 @@
20042004 * \param addr
20052005 * \param data
20062006 * \return int
2007
-* \retval 0 Succes
2007
+* \retval 0 Success
20082008 * \retval -EIO Timeout, I2C error, illegal bank
20092009 *
20102010 * 16 bits register write access via audio token ring interface.
....@@ -2094,7 +2094,7 @@
20942094 * \param datasize size of data buffer in bytes
20952095 * \param data     pointer to data buffer
20962096 * \return int
2097
-* \retval 0 Succes
2097
+* \retval 0 Success
20982098 * \retval -EIO Timeout, I2C error, illegal bank
20992099 *
21002100 */
....@@ -2182,7 +2182,7 @@
21822182 				     u32 *data, u32 flags)
21832183 {
21842184 	u8 buf[sizeof(*data)] = { 0 };
2185
-	int rc = -EIO;
2185
+	int rc;
21862186 	u32 word = 0;
21872187 
21882188 	if (!data)
....@@ -2306,7 +2306,7 @@
23062306 			pr_err("error %d\n", rc);
23072307 			goto rw_error;
23082308 		}
2309
-		/* fallthrough */
2309
+		fallthrough;
23102310 	case SIO_HI_RA_RAM_CMD_BRDCTRL:
23112311 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
23122312 		if (rc != 0) {
....@@ -2318,7 +2318,7 @@
23182318 			pr_err("error %d\n", rc);
23192319 			goto rw_error;
23202320 		}
2321
-		/* fallthrough */
2321
+		fallthrough;
23222322 	case SIO_HI_RA_RAM_CMD_NULL:
23232323 		/* No parameters */
23242324 		break;
....@@ -2338,7 +2338,7 @@
23382338 	if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET)
23392339 		msleep(1);
23402340 
2341
-	/* Detect power down to ommit reading result */
2341
+	/* Detect power down to omit reading result */
23422342 	powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
23432343 				  (((cmd->
23442344 				     param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
....@@ -2754,7 +2754,7 @@
27542754 	common_attr = (struct drx_common_attr *) demod->my_common_attr;
27552755 
27562756 	if (cfg_data->enable_mpeg_output == true) {
2757
-		/* quick and dirty patch to set MPEG incase current std is not
2757
+		/* quick and dirty patch to set MPEG in case current std is not
27582758 		   producing MPEG */
27592759 		switch (ext_attr->standard) {
27602760 		case DRX_STANDARD_8VSB:
....@@ -2841,7 +2841,7 @@
28412841 			/* coef = 188/204                          */
28422842 			max_bit_rate =
28432843 			    (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
2844
-			/* fall-through - as b/c Annex A/C need following settings */
2844
+			fallthrough;	/* as b/c Annex A/C need following settings */
28452845 		case DRX_STANDARD_ITU_B:
28462846 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
28472847 			if (rc != 0) {
....@@ -2894,7 +2894,7 @@
28942894 			break;
28952895 		default:
28962896 			break;
2897
-		}		/* swtich (standard) */
2897
+		}		/* switch (standard) */
28982898 
28992899 		/* Check insertion of the Reed-Solomon parity bytes */
29002900 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
....@@ -3555,8 +3555,8 @@
35553555 		if (!ext_attr->has_smatx)
35563556 			return -EIO;
35573557 		switch (uio_cfg->mode) {
3558
-		case DRX_UIO_MODE_FIRMWARE_SMA:	/* falltrough */
3559
-		case DRX_UIO_MODE_FIRMWARE_SAW:	/* falltrough */
3558
+		case DRX_UIO_MODE_FIRMWARE_SMA:
3559
+		case DRX_UIO_MODE_FIRMWARE_SAW:
35603560 		case DRX_UIO_MODE_READWRITE:
35613561 			ext_attr->uio_sma_tx_mode = uio_cfg->mode;
35623562 			break;
....@@ -3579,7 +3579,7 @@
35793579 		if (!ext_attr->has_smarx)
35803580 			return -EIO;
35813581 		switch (uio_cfg->mode) {
3582
-		case DRX_UIO_MODE_FIRMWARE0:	/* falltrough */
3582
+		case DRX_UIO_MODE_FIRMWARE0:
35833583 		case DRX_UIO_MODE_READWRITE:
35843584 			ext_attr->uio_sma_rx_mode = uio_cfg->mode;
35853585 			break;
....@@ -3603,7 +3603,7 @@
36033603 		if (!ext_attr->has_gpio)
36043604 			return -EIO;
36053605 		switch (uio_cfg->mode) {
3606
-		case DRX_UIO_MODE_FIRMWARE0:	/* falltrough */
3606
+		case DRX_UIO_MODE_FIRMWARE0:
36073607 		case DRX_UIO_MODE_READWRITE:
36083608 			ext_attr->uio_gpio_mode = uio_cfg->mode;
36093609 			break;
....@@ -3639,7 +3639,7 @@
36393639 			}
36403640 			ext_attr->uio_irqn_mode = uio_cfg->mode;
36413641 			break;
3642
-		case DRX_UIO_MODE_FIRMWARE0:	/* falltrough */
3642
+		case DRX_UIO_MODE_FIRMWARE0:
36433643 		default:
36443644 			return -EINVAL;
36453645 			break;
....@@ -4004,31 +4004,36 @@
40044004 		if (rc != 0) {
40054005 			pr_err("error %d\n", rc);
40064006 			goto rw_error;
4007
-		}	/* fallthrough */
4007
+		}
4008
+		fallthrough;
40084009 	case 4:
40094010 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
40104011 		if (rc != 0) {
40114012 			pr_err("error %d\n", rc);
40124013 			goto rw_error;
4013
-		}	/* fallthrough */
4014
+		}
4015
+		fallthrough;
40144016 	case 3:
40154017 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
40164018 		if (rc != 0) {
40174019 			pr_err("error %d\n", rc);
40184020 			goto rw_error;
4019
-		}	/* fallthrough */
4021
+		}
4022
+		fallthrough;
40204023 	case 2:
40214024 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
40224025 		if (rc != 0) {
40234026 			pr_err("error %d\n", rc);
40244027 			goto rw_error;
4025
-		}	/* fallthrough */
4028
+		}
4029
+		fallthrough;
40264030 	case 1:
40274031 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
40284032 		if (rc != 0) {
40294033 			pr_err("error %d\n", rc);
40304034 			goto rw_error;
4031
-		}	/* fallthrough */
4035
+		}
4036
+		fallthrough;
40324037 	case 0:
40334038 		/* do nothing */
40344039 		break;
....@@ -4068,25 +4073,29 @@
40684073 			if (rc != 0) {
40694074 				pr_err("error %d\n", rc);
40704075 				goto rw_error;
4071
-			}	/* fallthrough */
4076
+			}
4077
+			fallthrough;
40724078 		case 3:
40734079 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
40744080 			if (rc != 0) {
40754081 				pr_err("error %d\n", rc);
40764082 				goto rw_error;
4077
-			}	/* fallthrough */
4083
+			}
4084
+			fallthrough;
40784085 		case 2:
40794086 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
40804087 			if (rc != 0) {
40814088 				pr_err("error %d\n", rc);
40824089 				goto rw_error;
4083
-			}	/* fallthrough */
4090
+			}
4091
+			fallthrough;
40844092 		case 1:
40854093 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
40864094 			if (rc != 0) {
40874095 				pr_err("error %d\n", rc);
40884096 				goto rw_error;
4089
-			}	/* fallthrough */
4097
+			}
4098
+			fallthrough;
40904099 		case 0:
40914100 			/* do nothing */
40924101 			break;
....@@ -4127,7 +4136,7 @@
41274136 * \param datasize size of data buffer in bytes
41284137 * \param data     pointer to data buffer
41294138 * \return int
4130
-* \retval 0 Succes
4139
+* \retval 0 Success
41314140 * \retval -EIO Timeout, I2C error, illegal bank
41324141 *
41334142 */
....@@ -4201,7 +4210,7 @@
42014210 					 u16 *data, u32 flags)
42024211 {
42034212 	u8 buf[2] = { 0 };
4204
-	int rc = -EIO;
4213
+	int rc;
42054214 	u16 word = 0;
42064215 
42074216 	if (!data)
....@@ -4229,7 +4238,7 @@
42294238 					  u16 data, u32 flags)
42304239 {
42314240 	u8 buf[2];
4232
-	int rc = -EIO;
4241
+	int rc;
42334242 
42344243 	buf[0] = (u8) (data & 0xff);
42354244 	buf[1] = (u8) ((data >> 8) & 0xff);
....@@ -4791,7 +4800,7 @@
47914800 		   Sound carrier is already 3Mhz above centre frequency due
47924801 		   to tuner setting so now add an extra shift of 1MHz... */
47934802 		fm_frequency_shift = 1000;
4794
-		/*fall through */
4803
+		fallthrough;
47954804 	case DRX_STANDARD_ITU_B:
47964805 	case DRX_STANDARD_NTSC:
47974806 	case DRX_STANDARD_PAL_SECAM_BG:
....@@ -8989,7 +8998,7 @@
89898998 	     ((jiffies_to_msecs(jiffies) - start_time) <
89908999 	      (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))
89919000 	    );
8992
-	/* Returning control to apllication ... */
9001
+	/* Returning control to application ... */
89939002 
89949003 	return 0;
89959004 rw_error:
....@@ -9309,7 +9318,7 @@
93099318 		return -EINVAL;
93109319 
93119320 	/* all reported errors are received in the  */
9312
-	/* most recently finished measurment period */
9321
+	/* most recently finished measurement period */
93139322 	/*   no of pre RS bit errors */
93149323 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
93159324 	if (rc != 0) {
....@@ -9689,7 +9698,7 @@
96899698       (3) SIF AGC (used to amplify the output signal in case input to low)
96909699 
96919700       The SIF AGC is now coupled to the RF/IF AGCs.
9692
-      The SIF AGC is needed for both SIF ouput and the internal SIF signal to
9701
+      The SIF AGC is needed for both SIF output and the internal SIF signal to
96939702       the AUD block.
96949703 
96959704       RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of
....@@ -9702,11 +9711,11 @@
97029711        later on because of the schedule)
97039712 
97049713       Several HW/SCU "settings" can be used for ATV. The standard selection
9705
-      will reset most of these settings. To avoid that the end user apllication
9714
+      will reset most of these settings. To avoid that the end user application
97069715       has to perform these settings each time the ATV or FM standards is
97079716       selected the driver will shadow these settings. This enables the end user
97089717       to perform the settings only once after a drx_open(). The driver must
9709
-      write the shadow settings to HW/SCU incase:
9718
+      write the shadow settings to HW/SCU in case:
97109719 	 ( setstandard FM/ATV) ||
97119720 	 ( settings have changed && FM/ATV standard is active)
97129721       The shadow settings will be stored in the device specific data container.
....@@ -9908,7 +9917,7 @@
99089917 #define IMPULSE_COSINE_ALPHA_0_5    { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145}	/*sqrt raised-cosine filter with alpha=0.5 */
99099918 #define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16,  0, 34, 77, 114, 128}	/*full raised-cosine filter with alpha=0.5 (receiver only) */
99109919 
9911
-/* Coefficients for the nyquist fitler (total: 27 taps) */
9920
+/* Coefficients for the nyquist filter (total: 27 taps) */
99129921 #define NYQFILTERLEN 27
99139922 
99149923 static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)
....@@ -10475,11 +10484,11 @@
1047510484 	    (standard == DRX_STANDARD_NTSC)) {
1047610485 		switch (channel->bandwidth) {
1047710486 		case DRX_BANDWIDTH_6MHZ:
10478
-		case DRX_BANDWIDTH_UNKNOWN:	/* fall through */
10487
+		case DRX_BANDWIDTH_UNKNOWN:
1047910488 			channel->bandwidth = DRX_BANDWIDTH_6MHZ;
1048010489 			break;
10481
-		case DRX_BANDWIDTH_8MHZ:	/* fall through */
10482
-		case DRX_BANDWIDTH_7MHZ:	/* fall through */
10490
+		case DRX_BANDWIDTH_8MHZ:
10491
+		case DRX_BANDWIDTH_7MHZ:
1048310492 		default:
1048410493 			return -EINVAL;
1048510494 		}
....@@ -10511,10 +10520,10 @@
1051110520 		}
1051210521 
1051310522 		switch (channel->constellation) {
10514
-		case DRX_CONSTELLATION_QAM16:	/* fall through */
10515
-		case DRX_CONSTELLATION_QAM32:	/* fall through */
10516
-		case DRX_CONSTELLATION_QAM64:	/* fall through */
10517
-		case DRX_CONSTELLATION_QAM128:	/* fall through */
10523
+		case DRX_CONSTELLATION_QAM16:
10524
+		case DRX_CONSTELLATION_QAM32:
10525
+		case DRX_CONSTELLATION_QAM64:
10526
+		case DRX_CONSTELLATION_QAM128:
1051810527 		case DRX_CONSTELLATION_QAM256:
1051910528 			bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
1052010529 			bandwidth = bandwidth_temp / 100;
....@@ -10628,8 +10637,8 @@
1062810637 		}
1062910638 		break;
1063010639 #ifndef DRXJ_VSB_ONLY
10631
-	case DRX_STANDARD_ITU_A:	/* fallthrough */
10632
-	case DRX_STANDARD_ITU_B:	/* fallthrough */
10640
+	case DRX_STANDARD_ITU_A:
10641
+	case DRX_STANDARD_ITU_B:
1063310642 	case DRX_STANDARD_ITU_C:
1063410643 		rc = set_qam_channel(demod, channel, tuner_freq_offset);
1063510644 		if (rc != 0) {
....@@ -10820,7 +10829,7 @@
1082010829 		    SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
1082110830 		break;
1082210831 #endif
10823
-	case DRX_STANDARD_UNKNOWN:	/* fallthrough */
10832
+	case DRX_STANDARD_UNKNOWN:
1082410833 	default:
1082510834 		return -EIO;
1082610835 	}
....@@ -10888,8 +10897,8 @@
1088810897 	 */
1088910898 	switch (prev_standard) {
1089010899 #ifndef DRXJ_VSB_ONLY
10891
-	case DRX_STANDARD_ITU_A:	/* fallthrough */
10892
-	case DRX_STANDARD_ITU_B:	/* fallthrough */
10900
+	case DRX_STANDARD_ITU_A:
10901
+	case DRX_STANDARD_ITU_B:
1089310902 	case DRX_STANDARD_ITU_C:
1089410903 		rc = power_down_qam(demod, false);
1089510904 		if (rc != 0) {
....@@ -10908,7 +10917,7 @@
1090810917 	case DRX_STANDARD_UNKNOWN:
1090910918 		/* Do nothing */
1091010919 		break;
10911
-	case DRX_STANDARD_AUTO:	/* fallthrough */
10920
+	case DRX_STANDARD_AUTO:
1091210921 	default:
1091310922 		return -EINVAL;
1091410923 	}
....@@ -10921,8 +10930,8 @@
1092110930 
1092210931 	switch (*standard) {
1092310932 #ifndef DRXJ_VSB_ONLY
10924
-	case DRX_STANDARD_ITU_A:	/* fallthrough */
10925
-	case DRX_STANDARD_ITU_B:	/* fallthrough */
10933
+	case DRX_STANDARD_ITU_A:
10934
+	case DRX_STANDARD_ITU_B:
1092610935 	case DRX_STANDARD_ITU_C:
1092710936 		do {
1092810937 			u16 dummy;
....@@ -11111,12 +11120,12 @@
1111111120 				goto rw_error;
1111211121 			}
1111311122 			break;
11114
-		case DRX_STANDARD_PAL_SECAM_BG:	/* fallthrough */
11115
-		case DRX_STANDARD_PAL_SECAM_DK:	/* fallthrough */
11116
-		case DRX_STANDARD_PAL_SECAM_I:	/* fallthrough */
11117
-		case DRX_STANDARD_PAL_SECAM_L:	/* fallthrough */
11118
-		case DRX_STANDARD_PAL_SECAM_LP:	/* fallthrough */
11119
-		case DRX_STANDARD_NTSC:	/* fallthrough */
11123
+		case DRX_STANDARD_PAL_SECAM_BG:
11124
+		case DRX_STANDARD_PAL_SECAM_DK:
11125
+		case DRX_STANDARD_PAL_SECAM_I:
11126
+		case DRX_STANDARD_PAL_SECAM_L:
11127
+		case DRX_STANDARD_PAL_SECAM_LP:
11128
+		case DRX_STANDARD_NTSC:
1112011129 		case DRX_STANDARD_FM:
1112111130 			rc = power_down_atv(demod, ext_attr->standard, true);
1112211131 			if (rc != 0) {
....@@ -11127,7 +11136,7 @@
1112711136 		case DRX_STANDARD_UNKNOWN:
1112811137 			/* Do nothing */
1112911138 			break;
11130
-		case DRX_STANDARD_AUTO:	/* fallthrough */
11139
+		case DRX_STANDARD_AUTO:
1113111140 		default:
1113211141 			return -EIO;
1113311142 		}
....@@ -11220,8 +11229,8 @@
1122011229 		ext_attr->vsb_pre_saw_cfg = *pre_saw;
1122111230 		break;
1122211231 #ifndef DRXJ_VSB_ONLY
11223
-	case DRX_STANDARD_ITU_A:	/* fallthrough */
11224
-	case DRX_STANDARD_ITU_B:	/* fallthrough */
11232
+	case DRX_STANDARD_ITU_A:
11233
+	case DRX_STANDARD_ITU_B:
1122511234 	case DRX_STANDARD_ITU_C:
1122611235 		ext_attr->qam_pre_saw_cfg = *pre_saw;
1122711236 		break;
....@@ -11264,10 +11273,10 @@
1126411273 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
1126511274 
1126611275 	switch (afe_gain->standard) {
11267
-	case DRX_STANDARD_8VSB:	/* fallthrough */
11276
+	case DRX_STANDARD_8VSB:	fallthrough;
1126811277 #ifndef DRXJ_VSB_ONLY
11269
-	case DRX_STANDARD_ITU_A:	/* fallthrough */
11270
-	case DRX_STANDARD_ITU_B:	/* fallthrough */
11278
+	case DRX_STANDARD_ITU_A:
11279
+	case DRX_STANDARD_ITU_B:
1127111280 	case DRX_STANDARD_ITU_C:
1127211281 #endif
1127311282 		/* Do nothing */
....@@ -11301,8 +11310,8 @@
1130111310 		ext_attr->vsb_pga_cfg = gain * 13 + 140;
1130211311 		break;
1130311312 #ifndef DRXJ_VSB_ONLY
11304
-	case DRX_STANDARD_ITU_A:	/* fallthrough */
11305
-	case DRX_STANDARD_ITU_B:	/* fallthrough */
11313
+	case DRX_STANDARD_ITU_A:
11314
+	case DRX_STANDARD_ITU_B:
1130611315 	case DRX_STANDARD_ITU_C:
1130711316 		ext_attr->qam_pga_cfg = gain * 13 + 140;
1130811317 		break;
....@@ -12287,7 +12296,8 @@
1228712296 	if (state == NULL)
1228812297 		goto error;
1228912298 
12290
-	demod = kmalloc(sizeof(struct drx_demod_instance), GFP_KERNEL);
12299
+	demod = kmemdup(&drxj_default_demod_g,
12300
+			sizeof(struct drx_demod_instance), GFP_KERNEL);
1229112301 	if (demod == NULL)
1229212302 		goto error;
1229312303 
....@@ -12311,8 +12321,6 @@
1231112321 	state->demod = demod;
1231212322 
1231312323 	/* setup the demod data */
12314
-	memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance));
12315
-
1231612324 	demod->my_i2c_dev_addr = demod_addr;
1231712325 	demod->my_common_attr = demod_comm_attr;
1231812326 	demod->my_i2c_dev_addr->user_data = state;
....@@ -12367,7 +12375,7 @@
1236712375 
1236812376 	return NULL;
1236912377 }
12370
-EXPORT_SYMBOL(drx39xxj_attach);
12378
+EXPORT_SYMBOL_GPL(drx39xxj_attach);
1237112379 
1237212380 static const struct dvb_frontend_ops drx39xxj_ops = {
1237312381 	.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },