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| 67 | 67 | * (2 bytes). The DAP can operate in 3 modes: |
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| 68 | 68 | * (1) only short |
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| 69 | 69 | * (2) only long |
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| 70 | | -* (3) both long and short but short preferred and long only when necesarry |
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| 70 | +* (3) both long and short but short preferred and long only when necessary |
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| 71 | 71 | * |
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| 72 | 72 | * These modes must be selected compile time via compile switches. |
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| 73 | 73 | * Compile switch settings for the different modes: |
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| .. | .. |
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| 112 | 112 | * + single master mode means no use of repeated starts |
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| 113 | 113 | * + multi master mode means use of repeated starts |
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| 114 | 114 | * Default is single master. |
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| 115 | | -* Default can be overriden by setting the compile switch DRXDAP_SINGLE_MASTER. |
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| 115 | +* Default can be overridden by setting the compile switch DRXDAP_SINGLE_MASTER. |
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| 116 | 116 | * |
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| 117 | 117 | * Slave: |
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| 118 | 118 | * Single/multi master selected via the flags in the FASI protocol. |
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| 119 | 119 | * + single master means remember memory address between i2c packets |
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| 120 | 120 | * + multimaster means flush memory address between i2c packets |
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| 121 | 121 | * Default is single master, DAP FASI changes multi-master setting silently |
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| 122 | | -* into single master setting. This cannot be overrriden. |
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| 122 | +* into single master setting. This cannot be overridden. |
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| 123 | 123 | * |
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| 124 | 124 | */ |
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| 125 | 125 | /* set default */ |
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| .. | .. |
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| 139 | 139 | * In single master mode, data can be written by sending the register address |
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| 140 | 140 | * first, then two or four bytes of data in the next packet. |
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| 141 | 141 | * Because the device address plus a register address equals five bytes, |
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| 142 | | -* the mimimum chunk size must be five. |
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| 142 | +* the minimum chunk size must be five. |
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| 143 | 143 | * If ten-bit I2C device addresses are used, the minimum chunk size must be six, |
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| 144 | 144 | * because the I2C device address will then occupy two bytes when writing. |
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| 145 | 145 | * |
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