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| 1 | +# SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | # |
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2 | 3 | # Coresight configuration |
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3 | 4 | # |
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4 | 5 | menuconfig CORESIGHT |
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5 | | - bool "CoreSight Tracing Support" |
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| 6 | + tristate "CoreSight Tracing Support" |
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| 7 | + depends on ARM || ARM64 |
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| 8 | + depends on OF || ACPI |
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6 | 9 | select ARM_AMBA |
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7 | 10 | select PERF_EVENTS |
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8 | 11 | help |
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.. | .. |
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12 | 15 | specification and configure the right series of components when a |
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13 | 16 | trace source gets enabled. |
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14 | 17 | |
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| 18 | + To compile this driver as a module, choose M here: the |
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| 19 | + module will be called coresight. |
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| 20 | + |
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15 | 21 | if CORESIGHT |
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16 | 22 | config CORESIGHT_LINKS_AND_SINKS |
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17 | | - bool "CoreSight Link and Sink drivers" |
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| 23 | + tristate "CoreSight Link and Sink drivers" |
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18 | 24 | help |
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19 | 25 | This enables support for CoreSight link and sink drivers that are |
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20 | 26 | responsible for transporting and collecting the trace data |
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21 | 27 | respectively. Link and sinks are dynamically aggregated with a trace |
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22 | 28 | entity at run time to form a complete trace path. |
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23 | 29 | |
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| 30 | + To compile these drivers as modules, choose M here: the |
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| 31 | + modules will be called coresight-funnel and coresight-replicator. |
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| 32 | + |
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24 | 33 | config CORESIGHT_LINK_AND_SINK_TMC |
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25 | | - bool "Coresight generic TMC driver" |
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| 34 | + tristate "Coresight generic TMC driver" |
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| 35 | + |
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26 | 36 | depends on CORESIGHT_LINKS_AND_SINKS |
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27 | 37 | help |
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28 | 38 | This enables support for the Trace Memory Controller driver. |
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.. | .. |
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31 | 41 | complies with the generic implementation of the component without |
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32 | 42 | special enhancement or added features. |
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33 | 43 | |
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| 44 | + To compile this driver as a module, choose M here: the |
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| 45 | + module will be called coresight-tmc. |
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| 46 | + |
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34 | 47 | config CORESIGHT_CATU |
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35 | | - bool "Coresight Address Translation Unit (CATU) driver" |
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| 48 | + tristate "Coresight Address Translation Unit (CATU) driver" |
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36 | 49 | depends on CORESIGHT_LINK_AND_SINK_TMC |
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37 | 50 | help |
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38 | 51 | Enable support for the Coresight Address Translation Unit (CATU). |
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.. | .. |
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42 | 55 | by looking up the provided table. CATU can also be used in pass-through |
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43 | 56 | mode where the address is not translated. |
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44 | 57 | |
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| 58 | + To compile this driver as a module, choose M here: the |
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| 59 | + module will be called coresight-catu. |
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| 60 | + |
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45 | 61 | config CORESIGHT_SINK_TPIU |
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46 | | - bool "Coresight generic TPIU driver" |
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| 62 | + tristate "Coresight generic TPIU driver" |
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47 | 63 | depends on CORESIGHT_LINKS_AND_SINKS |
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48 | 64 | help |
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49 | 65 | This enables support for the Trace Port Interface Unit driver, |
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.. | .. |
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53 | 69 | connected to an external host for use case capturing more traces than |
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54 | 70 | the on-board coresight memory can handle. |
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55 | 71 | |
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| 72 | + To compile this driver as a module, choose M here: the |
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| 73 | + module will be called coresight-tpiu. |
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| 74 | + |
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56 | 75 | config CORESIGHT_SINK_ETBV10 |
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57 | | - bool "Coresight ETBv1.0 driver" |
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| 76 | + tristate "Coresight ETBv1.0 driver" |
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58 | 77 | depends on CORESIGHT_LINKS_AND_SINKS |
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59 | 78 | help |
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60 | 79 | This enables support for the Embedded Trace Buffer version 1.0 driver |
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61 | 80 | that complies with the generic implementation of the component without |
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62 | 81 | special enhancement or added features. |
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63 | 82 | |
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| 83 | + To compile this driver as a module, choose M here: the |
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| 84 | + module will be called coresight-etb10. |
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| 85 | + |
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64 | 86 | config CORESIGHT_SOURCE_ETM3X |
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65 | | - bool "CoreSight Embedded Trace Macrocell 3.x driver" |
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| 87 | + tristate "CoreSight Embedded Trace Macrocell 3.x driver" |
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66 | 88 | depends on !ARM64 |
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67 | 89 | select CORESIGHT_LINKS_AND_SINKS |
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68 | 90 | help |
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.. | .. |
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71 | 93 | This is primarily useful for instruction level tracing. Depending |
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72 | 94 | the ETM version data tracing may also be available. |
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73 | 95 | |
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| 96 | + To compile this driver as a module, choose M here: the |
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| 97 | + module will be called coresight-etm3x. |
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| 98 | + |
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74 | 99 | config CORESIGHT_SOURCE_ETM4X |
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75 | | - bool "CoreSight Embedded Trace Macrocell 4.x driver" |
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| 100 | + tristate "CoreSight ETMv4.x / ETE driver" |
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76 | 101 | depends on ARM64 |
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77 | 102 | select CORESIGHT_LINKS_AND_SINKS |
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78 | 103 | select PID_IN_CONTEXTIDR |
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79 | 104 | help |
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80 | | - This driver provides support for the ETM4.x tracer module, tracing the |
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81 | | - instructions that a processor is executing. This is primarily useful |
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82 | | - for instruction level tracing. Depending on the implemented version |
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83 | | - data tracing may also be available. |
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| 105 | + This driver provides support for the CoreSight Embedded Trace Macrocell |
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| 106 | + version 4.x and the Embedded Trace Extensions (ETE). Both are CPU tracer |
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| 107 | + modules, tracing the instructions that a processor is executing. This is |
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| 108 | + primarily useful for instruction level tracing. |
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84 | 109 | |
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85 | | -config CORESIGHT_DYNAMIC_REPLICATOR |
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86 | | - bool "CoreSight Programmable Replicator driver" |
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87 | | - depends on CORESIGHT_LINKS_AND_SINKS |
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| 110 | + To compile this driver as a module, choose M here: the |
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| 111 | + module will be called coresight-etm4x. |
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| 112 | + |
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| 113 | +config ETM4X_IMPDEF_FEATURE |
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| 114 | + bool "Control implementation defined overflow support in ETM 4.x driver" |
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| 115 | + depends on CORESIGHT_SOURCE_ETM4X |
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88 | 116 | help |
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89 | | - This enables support for dynamic CoreSight replicator link driver. |
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90 | | - The programmable ATB replicator allows independent filtering of the |
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91 | | - trace data based on the traceid. |
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| 117 | + This control provides implementation define control for CoreSight |
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| 118 | + ETM 4.x tracer module that can't reduce commit rate automatically. |
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| 119 | + This avoids overflow between the ETM tracer module and the cpu core. |
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92 | 120 | |
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93 | 121 | config CORESIGHT_STM |
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94 | | - bool "CoreSight System Trace Macrocell driver" |
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| 122 | + tristate "CoreSight System Trace Macrocell driver" |
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95 | 123 | depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 |
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96 | 124 | select CORESIGHT_LINKS_AND_SINKS |
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97 | 125 | select STM |
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.. | .. |
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100 | 128 | instrumentation based tracing. This is primarily used for |
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101 | 129 | logging useful software events or data coming from various entities |
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102 | 130 | in the system, possibly running different OSs |
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| 131 | + |
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| 132 | + To compile this driver as a module, choose M here: the |
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| 133 | + module will be called coresight-stm. |
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103 | 134 | |
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104 | 135 | config CORESIGHT_CPU_DEBUG |
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105 | 136 | tristate "CoreSight CPU Debug driver" |
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.. | .. |
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112 | 143 | can quickly get to know program counter (PC), secure state, |
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113 | 144 | exception level, etc. Before use debugging functionality, platform |
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114 | 145 | needs to ensure the clock domain and power domain are enabled |
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115 | | - properly, please refer Documentation/trace/coresight-cpu-debug.txt |
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| 146 | + properly, please refer Documentation/trace/coresight/coresight-cpu-debug.rst |
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116 | 147 | for detailed description and the example for usage. |
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117 | 148 | |
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| 149 | + To compile this driver as a module, choose M here: the |
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| 150 | + module will be called coresight-cpu-debug. |
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| 151 | + |
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| 152 | +config CORESIGHT_CTI |
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| 153 | + tristate "CoreSight Cross Trigger Interface (CTI) driver" |
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| 154 | + depends on ARM || ARM64 |
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| 155 | + help |
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| 156 | + This driver provides support for CoreSight CTI and CTM components. |
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| 157 | + These provide hardware triggering events between CoreSight trace |
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| 158 | + source and sink components. These can be used to halt trace or |
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| 159 | + inject events into the trace stream. CTI also provides a software |
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| 160 | + control to trigger the same halt events. This can provide fast trace |
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| 161 | + halt compared to disabling sources and sinks normally in driver |
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| 162 | + software. |
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| 163 | + |
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| 164 | + To compile this driver as a module, choose M here: the |
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| 165 | + module will be called coresight-cti. |
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| 166 | + |
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| 167 | +config CORESIGHT_CTI_INTEGRATION_REGS |
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| 168 | + bool "Access CTI CoreSight Integration Registers" |
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| 169 | + depends on CORESIGHT_CTI |
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| 170 | + help |
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| 171 | + This option adds support for the CoreSight integration registers on |
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| 172 | + this device. The integration registers allow the exploration of the |
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| 173 | + CTI trigger connections between this and other devices.These |
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| 174 | + registers are not used in normal operation and can leave devices in |
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| 175 | + an inconsistent state. |
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| 176 | + |
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| 177 | +config CORESIGHT_TRBE |
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| 178 | + tristate "Trace Buffer Extension (TRBE) driver" |
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| 179 | + depends on ARM64 && CORESIGHT_SOURCE_ETM4X |
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| 180 | + help |
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| 181 | + This driver provides support for percpu Trace Buffer Extension (TRBE). |
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| 182 | + TRBE always needs to be used along with it's corresponding percpu ETE |
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| 183 | + component. ETE generates trace data which is then captured with TRBE. |
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| 184 | + Unlike traditional sink devices, TRBE is a CPU feature accessible via |
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| 185 | + system registers. But it's explicit dependency with trace unit (ETE) |
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| 186 | + requires it to be plugged in as a coresight sink device. |
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| 187 | + |
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| 188 | + To compile this driver as a module, choose M here: the module will be |
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| 189 | + called coresight-trbe. |
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118 | 190 | endif |
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