disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
..
..
@@ -833,6 +833,16 @@
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 	0x1012110d, 0x1012110d, 0x1013110c, 0x1013110c,
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 };
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+static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
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+{
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+	if (mixer->cfg->is_de3)
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+		return DE3_VI_SCALER_UNIT_BASE +
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+		       DE3_VI_SCALER_UNIT_SIZE * channel;
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+	else
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+		return DE2_VI_SCALER_UNIT_BASE +
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+		       DE2_VI_SCALER_UNIT_SIZE * channel;
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+}
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+
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 static int sun8i_vi_scaler_coef_index(unsigned int step)
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 {
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 	unsigned int scale, int_part, float_part;
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@@ -857,7 +867,7 @@
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 	}
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 }
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-static void sun8i_vi_scaler_set_coeff(struct regmap *map, int layer,
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+static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base,
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 				      u32 hstep, u32 vstep,
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 				      const struct drm_format_info *format)
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 {
..
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@@ -877,29 +887,31 @@
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 	offset = sun8i_vi_scaler_coef_index(hstep) *
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 			SUN8I_VI_SCALER_COEFF_COUNT;
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 	for (i = 0; i < SUN8I_VI_SCALER_COEFF_COUNT; i++) {
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-		regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF0(layer, i),
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+		regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, i),
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 			     lan3coefftab32_left[offset + i]);
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-		regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF1(layer, i),
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+		regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF1(base, i),
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 			     lan3coefftab32_right[offset + i]);
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-		regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF0(layer, i),
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+		regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, i),
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 			     ch_left[offset + i]);
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-		regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF1(layer, i),
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+		regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF1(base, i),
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 			     ch_right[offset + i]);
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 	}
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 	offset = sun8i_vi_scaler_coef_index(hstep) *
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 			SUN8I_VI_SCALER_COEFF_COUNT;
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 	for (i = 0; i < SUN8I_VI_SCALER_COEFF_COUNT; i++) {
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-		regmap_write(map, SUN8I_SCALER_VSU_YVCOEFF(layer, i),
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+		regmap_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, i),
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 			     lan2coefftab32[offset + i]);
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-		regmap_write(map, SUN8I_SCALER_VSU_CVCOEFF(layer, i),
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+		regmap_write(map, SUN8I_SCALER_VSU_CVCOEFF(base, i),
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 			     cy[offset + i]);
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 	}
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 }
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 void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable)
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 {
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-	u32 val;
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+	u32 val, base;
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+
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+	base = sun8i_vi_scaler_base(mixer, layer);
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 	if (enable)
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 		val = SUN8I_SCALER_VSU_CTRL_EN |
..
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@@ -907,7 +919,8 @@
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 	else
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 		val = 0;
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-	regmap_write(mixer->engine.regs, SUN8I_SCALER_VSU_CTRL(layer), val);
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+	regmap_write(mixer->engine.regs,
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+		     SUN8I_SCALER_VSU_CTRL(base), val);
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 }
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 void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
..
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@@ -917,6 +930,9 @@
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 {
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 	u32 chphase, cvphase;
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 	u32 insize, outsize;
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+	u32 base;
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+
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+	base = sun8i_vi_scaler_base(mixer, layer);
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 	hphase <<= SUN8I_VI_SCALER_PHASE_FRAC - 16;
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 	vphase <<= SUN8I_VI_SCALER_PHASE_FRAC - 16;
..
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@@ -940,32 +956,44 @@
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 		cvphase = vphase;
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 	}
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+	if (mixer->cfg->is_de3) {
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+		u32 val;
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+
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+		if (format->hsub == 1 && format->vsub == 1)
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+			val = SUN50I_SCALER_VSU_SCALE_MODE_UI;
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+		else
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+			val = SUN50I_SCALER_VSU_SCALE_MODE_NORMAL;
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+
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+		regmap_write(mixer->engine.regs,
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+			     SUN50I_SCALER_VSU_SCALE_MODE(base), val);
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+	}
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+
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_VSU_OUTSIZE(layer), outsize);
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+		     SUN8I_SCALER_VSU_OUTSIZE(base), outsize);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_VSU_YINSIZE(layer), insize);
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+		     SUN8I_SCALER_VSU_YINSIZE(base), insize);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_VSU_YHSTEP(layer), hscale);
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+		     SUN8I_SCALER_VSU_YHSTEP(base), hscale);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_VSU_YVSTEP(layer), vscale);
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+		     SUN8I_SCALER_VSU_YVSTEP(base), vscale);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_VSU_YHPHASE(layer), hphase);
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+		     SUN8I_SCALER_VSU_YHPHASE(base), hphase);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_VSU_YVPHASE(layer), vphase);
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+		     SUN8I_SCALER_VSU_YVPHASE(base), vphase);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_VSU_CINSIZE(layer),
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+		     SUN8I_SCALER_VSU_CINSIZE(base),
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 		     SUN8I_VI_SCALER_SIZE(src_w / format->hsub,
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 					  src_h / format->vsub));
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_VSU_CHSTEP(layer),
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+		     SUN8I_SCALER_VSU_CHSTEP(base),
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 		     hscale / format->hsub);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_VSU_CVSTEP(layer),
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+		     SUN8I_SCALER_VSU_CVSTEP(base),
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 		     vscale / format->vsub);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_VSU_CHPHASE(layer), chphase);
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+		     SUN8I_SCALER_VSU_CHPHASE(base), chphase);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_VSU_CVPHASE(layer), cvphase);
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-	sun8i_vi_scaler_set_coeff(mixer->engine.regs, layer,
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+		     SUN8I_SCALER_VSU_CVPHASE(base), cvphase);
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+	sun8i_vi_scaler_set_coeff(mixer->engine.regs, base,
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 				  hscale, vscale, format);
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 }