disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
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@@ -10,6 +10,7 @@
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  */
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 #include "sun8i_ui_scaler.h"
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+#include "sun8i_vi_scaler.h"
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 static const u32 lan2coefftab16[240] = {
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 	0x00004000, 0x00033ffe, 0x00063efc, 0x000a3bfb,
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@@ -88,6 +89,20 @@
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 	0x0b1c1603, 0x0d1c1502, 0x0e1d1401, 0x0f1d1301,
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 };
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+static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel)
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+{
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+	int vi_num = mixer->cfg->vi_num;
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+
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+	if (mixer->cfg->is_de3)
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+		return DE3_VI_SCALER_UNIT_BASE +
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+		       DE3_VI_SCALER_UNIT_SIZE * vi_num +
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+		       DE3_UI_SCALER_UNIT_SIZE * (channel - vi_num);
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+	else
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+		return DE2_VI_SCALER_UNIT_BASE +
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+		       DE2_VI_SCALER_UNIT_SIZE * vi_num +
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+		       DE2_UI_SCALER_UNIT_SIZE * (channel - vi_num);
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+}
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+
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 static int sun8i_ui_scaler_coef_index(unsigned int step)
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 {
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 	unsigned int scale, int_part, float_part;
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@@ -114,11 +129,12 @@
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 void sun8i_ui_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable)
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 {
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-	int vi_cnt = mixer->cfg->vi_num;
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-	u32 val;
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+	u32 val, base;
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-	if (WARN_ON(layer < vi_cnt))
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+	if (WARN_ON(layer < mixer->cfg->vi_num))
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 		return;
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+
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+	base = sun8i_ui_scaler_base(mixer, layer);
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 	if (enable)
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 		val = SUN8I_SCALER_GSU_CTRL_EN |
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@@ -126,20 +142,21 @@
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 	else
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 		val = 0;
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-	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_GSU_CTRL(vi_cnt, layer - vi_cnt), val);
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+	regmap_write(mixer->engine.regs, SUN8I_SCALER_GSU_CTRL(base), val);
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 }
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 void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer,
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 			   u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
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 			   u32 hscale, u32 vscale, u32 hphase, u32 vphase)
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 {
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-	int vi_cnt = mixer->cfg->vi_num;
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 	u32 insize, outsize;
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 	int i, offset;
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+	u32 base;
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-	if (WARN_ON(layer < vi_cnt))
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+	if (WARN_ON(layer < mixer->cfg->vi_num))
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 		return;
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+
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+	base = sun8i_ui_scaler_base(mixer, layer);
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 	hphase <<= SUN8I_UI_SCALER_PHASE_FRAC - 16;
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 	vphase <<= SUN8I_UI_SCALER_PHASE_FRAC - 16;
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@@ -149,24 +166,22 @@
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 	insize = SUN8I_UI_SCALER_SIZE(src_w, src_h);
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 	outsize = SUN8I_UI_SCALER_SIZE(dst_w, dst_h);
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-	layer -= vi_cnt;
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-
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_GSU_OUTSIZE(vi_cnt, layer), outsize);
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+		     SUN8I_SCALER_GSU_OUTSIZE(base), outsize);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_GSU_INSIZE(vi_cnt, layer), insize);
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+		     SUN8I_SCALER_GSU_INSIZE(base), insize);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_GSU_HSTEP(vi_cnt, layer), hscale);
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+		     SUN8I_SCALER_GSU_HSTEP(base), hscale);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_GSU_VSTEP(vi_cnt, layer), vscale);
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+		     SUN8I_SCALER_GSU_VSTEP(base), vscale);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_GSU_HPHASE(vi_cnt, layer), hphase);
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+		     SUN8I_SCALER_GSU_HPHASE(base), hphase);
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 	regmap_write(mixer->engine.regs,
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-		     SUN8I_SCALER_GSU_VPHASE(vi_cnt, layer), vphase);
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+		     SUN8I_SCALER_GSU_VPHASE(base), vphase);
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 	offset = sun8i_ui_scaler_coef_index(hscale) *
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 			SUN8I_UI_SCALER_COEFF_COUNT;
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 	for (i = 0; i < SUN8I_UI_SCALER_COEFF_COUNT; i++)
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 		regmap_write(mixer->engine.regs,
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-			     SUN8I_SCALER_GSU_HCOEFF(vi_cnt, layer, i),
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+			     SUN8I_SCALER_GSU_HCOEFF(base, i),
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 			     lan2coefftab16[offset + i]);
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 }